CN109189135B

CN109189135B - Partition self-coupling compensation alternating current voltage stabilization control method

Info

Publication number: CN109189135B
Application number: CN201811356024.5A
Authority: CN
Inventors: 王炜; 凌云; 杨兴果
Original assignee: Hunan University of Technology
Current assignee: Ma Genying
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2020-10-30
Anticipated expiration: 2038-11-15
Also published as: CN109189135A

Abstract

A partitioned auto-coupling compensation alternating current voltage stabilization control method is realized by an alternating current voltage stabilizer comprising an auto-coupling compensation type main circuit, a sampling comparison unit, a time delay protection unit, a trigger gating control unit, a trigger unit, an error detection judging unit and a protection driving unit, wherein the auto-coupling compensation type main circuit comprises a compensation transformer, an auto-coupling transformer, a thyristor switch group and a relay protection switch. The sampling comparison unit samples the voltage of the alternating current power supply and outputs a trigger gating control value; the trigger gating control unit outputs a trigger control signal according to the delayed trigger gating control value and controls the on-off of the thyristors in the thyristor switch group by the trigger unit. According to the alternating current voltage stabilization control method, while the interlocking control is realized, the protection of the thyristor switch group is started/stopped by the error detection judging unit and the protection driving unit according to whether the trigger gating control value is effective or not, the power supply of the trigger unit is controlled, and the protection strength for the abnormity of the working process is effectively enhanced.

Description

Partition self-coupling compensation alternating current voltage stabilization control method

Technical Field

The invention relates to the technical field of power supplies, in particular to a partitioned self-coupling compensation alternating current voltage stabilization control method.

Background

The existing compensation type AC voltage stabilizer has the advantages of wide voltage stabilizing range, almost no distortion of waveform, high efficiency of the whole machine and strong load adaptability. The principle is that switching of different winding coils of a primary winding on a compensation transformer is automatically controlled according to the high-low condition of input voltage, bidirectional multi-gear voltage compensation is provided by utilizing the transformation ratio relation of a primary side working winding and a secondary winding or by adjusting the voltage applied to the primary winding, and therefore the purpose of voltage regulation and stabilization is achieved.

The existing compensation type alternating current voltage stabilizer has the following defects: when the motor is adopted to control the carbon brush to move to change the application of different voltages to the excitation coil of the compensation transformer, the carbon brush is easy to wear and often fails. Switching different winding coils of a primary winding on a compensation transformer by adopting an electronic switch switching mode, or when voltage applied to the primary winding is adjusted, the delayed turn-off of the electronic switch is easy to cause a power supply short-circuit fault; when the electronic switch is controlled to be switched by adopting a program mode of a singlechip, a PLC and the like, the problems of program runaway, dead halt and the like can also cause the failure of the voltage stabilizer or cause the short-circuit fault of a power supply due to the error of control logic.

Disclosure of Invention

In order to solve the problems of the existing compensation type alternating current voltage stabilizer, the invention provides a control method of a partitioned self-coupling compensation alternating current voltage stabilizer, which comprises the following steps:

dividing the voltage in the alternating current power supply voltage fluctuation interval range into a plurality of voltage grade intervals for compensation control; identifying the voltage grade interval of the alternating-current power supply voltage to obtain a trigger gating control value; triggering the gating control value to control the on-off combined state of the thyristors in the thyristor switch group; the on-off combined state of the thyristors in the thyristor switch group controls and selects 0 or 1 or the superposition of a plurality of voltages in a plurality of output voltages of the autotransformer as the excitation coil voltage of the compensation transformer to realize the voltage compensation state corresponding to the voltage grade interval; each voltage class interval of the alternating current power supply voltage corresponds to a voltage compensation state.

And judging whether the trigger gating control value is effective or not, and controlling the thyristor switch group to be in a protection state when the trigger gating control value is ineffective. Triggering a gating control value to be an M-bit binary value; judging whether the trigger gating control value is effective or not according to the fact that the trigger gating control value is effective when one bit is effective in M-bit binary values of the trigger gating control value; otherwise, triggering the gating control value to be invalid; and M is an integer greater than or equal to 2. Further, the bit in the trigger gating control value is 1 valid and 0 invalid, that is, the high level in the trigger gating control value signal is valid and the low level is invalid; or, the bit in the trigger gating control value is 0 valid and 1 invalid, that is, the low level in the trigger gating control value signal is valid and the high level is invalid; the M trigger gating control values are all effective, and M trigger gating control values are all effective.

And identifying the voltage grade interval of the alternating-current power supply voltage to obtain a trigger gating control value, wherein the trigger gating control value is realized by a sampling comparison unit. The sampling comparison unit comprises an alternating current power supply voltage sampling circuit and a multi-interval voltage comparator circuit, wherein the alternating current power supply voltage sampling circuit converts an effective value of alternating current power supply voltage into a sampling value of the alternating current power supply voltage; the input voltage of the multi-interval voltage comparator circuit is an alternating current power supply voltage sampling value, the input voltage, namely the alternating current power supply voltage sampling value is compared with M-1 threshold voltages to obtain an M-bit comparison output value, and the M-bit comparison output value forms a trigger gating control value. The M-1 threshold voltages are respectively alternating current power supply voltage sampling values corresponding to M-1 intermediate separation values of M voltage grade intervals of the alternating current power supply voltage. The multi-interval voltage comparator circuit comprises M-1 comparators, compares input voltage with M-1 different threshold voltages and outputs M-bit comparison output values; and the M-1 comparators are all powered by a positive single power supply. M-1 different threshold voltages are respectively connected to the non-inverting input ends of the M-1 comparators, and the input voltage is simultaneously connected to the inverting input ends of the M-1 comparators. The high level of the M-bit comparison output value output by the multi-interval voltage comparator is effective, and only one of the M-bit comparison output value is effective. Among the M-1 comparators, the comparator with the lowest threshold voltage directly adopts a positive single power supply to supply power, and other comparators adopt controllable power supplies to supply power; when the comparator is powered by a controllable power supply, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages lower than the threshold voltages output low levels, the output end of the comparator is connected with a pull-down resistor, and otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator. The comparator adopts a controllable power supply to supply power, and outputs low level when the controllable power supply stops supplying power to the positive power supply end. The M-bit comparison output value consists of output values of M-1 comparators and a highest interval judgment value; and when the output values of the M-1 comparators are all low levels, the highest interval judgment value is high level, otherwise, the highest interval judgment value is low level.

The multi-interval voltage comparator circuit comprises M comparators for comparing the input voltage with M different threshold voltages and outputting M-bit comparison output values; the M comparators are all powered by a positive single power supply. The M different threshold voltages are respectively connected to the non-inverting input ends of the M comparators, and the input voltage is simultaneously connected to the inverting input ends of the M comparators. The high level of the M-bit comparison output value output by the multi-interval voltage comparator is effective, and only one of the M-bit comparison output value is effective. Among the M comparators, the comparator with the lowest threshold voltage directly adopts a positive single power supply to supply power, and other comparators adopt controllable power supplies to supply power; when the comparator is powered by a controllable power supply, the output end of the comparator is connected with a pull-down resistor, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages lower than the threshold voltages output low levels, and otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator. The comparator adopts a controllable power supply to supply power, and outputs low level when the controllable power supply stops supplying power to the positive power supply end. The M-bit comparison output value consists of the output values of the M comparators. The M different threshold voltages are respectively the upper limit values of the interval voltages of the M interval voltages.

The positive power supply end of the comparator is connected to the output end of the NOR gate, and the input end of the NOR gate is respectively connected to the output ends of the comparators with the threshold voltages lower than that of the NOR gate. The comparators in the multi-interval voltage comparator circuit preferably adopt a low-power-consumption rail-to-rail operational amplifier powered by a single power supply.

The method for controlling the on-off combination state of the thyristors in the thyristor switch group by the trigger gating control value is that the diode trigger gating matrix selects and enables the corresponding trigger control signal to be effective according to the effective trigger gating control value to control the on-off combination state of the thyristors in the thyristor switch group.

The thyristor switch group is provided with N thyristors in total; the diode triggering gating matrix comprises M triggering gating control column lines, N triggering driving row lines and a plurality of diodes; m triggering gating control column lines correspond to M bit triggering gating control values one by one, and an effective triggering gating control value correspondingly enables a signal of one triggering gating control column line to be effective; the N trigger driving row lines correspond to the N thyristors one by one, and the effective correspondence of a trigger driving row line signal enables a trigger control signal of one thyristor to be effective; the trigger control signal effectively turns on the corresponding thyristor. And N is an integer greater than or equal to 4.

When each trigger gating control column line signal is effective, the on-off combination state of the thyristor in the corresponding thyristor switch group is controlled; and when a certain trigger gating control column line signal is effective, the diode enables a trigger driving column line signal which needs to control the conduction of the thyristor to be effective.

When the trigger gating control value is changed due to the change of the voltage grade interval and the on-off combination state of the thyristors in the thyristor switch group needs to be switched, maintaining a time without trigger area between the 2 on-off combination states, and switching off all the thyristors in the thyristor switch group. Maintaining a no-trigger zone time is accomplished by a no-trigger zone control signal. Controlling the control signal of the non-trigger area to output a single pulse after the trigger gating control value is changed; the control signal of the non-trigger area is effective in the period of outputting the single pulse and is ineffective in the period of not outputting the single pulse; and when the control signal of the non-trigger area is effective, maintaining a time of the non-trigger area. Further, after the trigger gating control value is changed, the width time of a single pulse in the non-trigger area control signal is selected from 10ms to 30 ms.

The trigger control signal for controlling the thyristor switch group is generated by the delayed trigger gating control value; the delayed signal change time of the trigger gating control value is later than the leading edge time of a single pulse in the non-trigger area control signal after the trigger gating control value is changed and earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the trigger gating control value is changed.

The functions of delaying the trigger gating control value and generating a control signal of a non-trigger area are realized by a delay protection unit; the error detection judging unit is used for inputting the delayed trigger gating control value, judging whether the delayed trigger gating control value is effective or not and outputting a trigger gating control value judging signal.

The method is realized by an alternating current voltage stabilizer comprising a self-coupling compensation type main circuit, a sampling comparison unit, a time delay protection unit, a trigger gating control unit, a trigger unit, an error detection judgment unit and a protection driving unit. The auto-coupling compensation type main circuit comprises a compensation transformer, an auto-coupling transformer and a thyristor switch group; the trigger unit controls the on-off of the thyristors in the thyristor switch group of the main circuit according to the input trigger control signal. The protection driving unit stops/starts protection of the thyristor switch group according to whether the trigger gating control value is effective or not, and the specific method is that when the trigger gating control value is ineffective, the input side power supply voltage of the autotransformer is controlled to be disconnected to enable the thyristor switch group to be in a protection state; when the thyristor switch group is in a protection state, and the error detection judging unit judges that the input trigger gating control value is recovered to be effective, the protection driving unit automatically stops the protection state of the thyristor switch group.

The trigger gating control unit includes a diode trigger gating matrix. The method for enabling the trigger control signal of the thyristor to be effective by enabling the trigger drive row line signal to be effective is that N trigger drive row line signals are directly used as the trigger control signals of N thyristors in a one-to-one correspondence manner; a trigger driving row line signal is effective and corresponds to a method for enabling a trigger control signal of a thyristor to be effective, or the trigger gating control unit further comprises a trigger control signal driving circuit; the input of the trigger control signal driving circuit is N signals for triggering and driving the row lines, and the output is trigger control signals of N thyristors in one-to-one correspondence.

The protection driving unit controls the power supply of the triggering unit according to whether the triggering gating control value is effective or not and whether the control signal of the non-triggering area is effective or not, and the specific method is that only when the triggering gating control value is effective and the control signal of the non-triggering area is ineffective, the power supply of the triggering unit is controlled to be switched on, the triggering unit works normally, and triggering pulse is sent out according to the input triggering control signal; otherwise, the power supply of the trigger unit is cut off, and all trigger pulses are stopped to be sent out.

The thyristors in the thyristor switch group are bidirectional thyristors or thyristor alternating current switches formed by connecting 2 unidirectional thyristors in reverse parallel.

The invention has the beneficial effects that: the partitioned self-coupling compensation alternating current voltage stabilization control method for voltage compensation by adopting the compensation transformer group and the thyristor switch group adopts only one effective and different trigger gating control value, realizes gating control on different on-off combination states of the thyristors in the thyristor switch group by the diode trigger gating matrix, and ensures that the thyristors at the same side in the thyristor switch group are not conducted at the same time, namely, realizes interlocking control of the thyristors. Meanwhile, when an invalid trigger gating control value is output due to an error occurring during the identification of the voltage grade interval of the alternating-current power supply voltage, the trigger pulse is stopped being sent out, the power supply voltage at the input side of the autotransformer is cut off, and the thyristor switch group is protected, so that the protection strength for the abnormity of the alternating-current voltage stabilization working process is effectively enhanced; when the thyristor switch group is in a protection state, if the trigger gating control value is recovered to be effective, the protection state of the thyristor switch group can be automatically stopped and the thyristor switch group is in a compensation working state again; the on-off switching of the thyristor is controlled without adopting a program mode of a singlechip, a PLC and the like, so that the voltage stabilization fault caused by the problems of program runaway, dead halt and the like is avoided. The function ensures that the working process of the partition self-coupling compensation alternating current voltage stabilization control method is more stable and reliable.

Drawings

FIG. 1 is a block diagram of an AC voltage regulator implementing a partitioned auto-compensation AC voltage regulation control method;

FIG. 2 shows an embodiment of a self-coupled compensated main circuit 1;

FIG. 3 illustrates an embodiment of a self-coupled compensated main circuit 2;

FIG. 4 shows a sample comparison unit of example 1;

FIG. 5 shows a sample comparison unit of example 2;

FIG. 6 is a block diagram of an embodiment of a delay protection unit;

FIG. 7 is a diagram of an embodiment of a delay detection circuit 1 of the delay detection module for triggering the strobe control value signal Y10;

FIG. 8 is a circuit diagram of embodiment 2 of the delay detection circuit for triggering the strobe control value signal Y10 in the delay detection module;

FIG. 9 is a block diagram of an embodiment of a delay detection circuit 3 for triggering the strobe control value signal Y10 in the delay detection module;

FIG. 10 is a block diagram of an embodiment of a no trigger area control signal generation module;

FIG. 11 is a diagram illustrating a partial correlation waveform in the delay protection unit;

FIG. 12 is an embodiment of a trigger circuit for triggering the triac SR1 in the trigger unit;

FIG. 13 shows an embodiment of a trigger strobe control unit 1;

FIG. 14 shows an embodiment of a trigger strobe control unit 2;

FIG. 15 shows a trigger strobe control unit embodiment 3;

FIG. 16 shows an embodiment of an error detection and determination unit;

fig. 17 is a protection drive unit embodiment.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of an AC voltage stabilizer for implementing a partitioned auto-compensation AC voltage stabilization control method, in which a sampling comparison unit samples the voltage of an AC power supply and outputs a trigger gating control value P2; the delay protection unit inputs a trigger gating control value P2 and outputs a delayed trigger gating control value P3 and a non-trigger area control signal P4; the trigger gating control unit inputs the delayed trigger gating control value P3 and outputs a trigger control signal P5; the trigger unit sends a trigger signal P6 to the self-coupling compensation type main circuit according to an input trigger control signal P5 to control the on-off of the bidirectional thyristor in the thyristor switch group; the error detection judging unit inputs the delayed trigger gating control value P3 and outputs a trigger gating control value judging signal P7; the protection driving unit inputs a non-trigger area control signal P4 and a trigger gating control value judging signal P7, stops/starts protection of the thyristor switch group according to whether the trigger gating control value judging signal P7 is effective, and controls the power supply of the trigger unit according to whether the trigger gating control value judging signal P7 is effective and whether the non-trigger area control signal P4 is effective.

Fig. 2 is an embodiment 1 of the self-coupling compensation type main circuit, which comprises a compensation transformer TB1 and a self-coupling transformer TB2, wherein 6 bidirectional thyristors SR1-SR6 jointly form a thyristor switch group, and a fuse FU1, a relay normally-open switch KA-1 and a relay normally-closed switch KA-2 form a relay protection circuit.

In fig. 2, the compensation coil of the compensation transformer TB1 is connected in series to the phase line, where the input end of the phase line is LA1 and the output end is LA 2. The voltage on the excitation coil of TB1 is controlled by the thyristor switch group. The autotransformer TB2 is provided with 3 output taps C1, C2 and C3, one ends of bidirectional thyristors SR1, SR3 and SR5 are connected in parallel and then connected to one end of a TB1 excitation coil, and the other ends of SR1, SR3 and SR5 are connected to taps C1, C2 and C3 respectively; one ends of the bidirectional thyristors SR2, SR4 and SR6 are connected in parallel and then connected to the other end of the excitation coil of TB1, and the other ends of SR2, SR4 and SR6 are respectively connected to taps C1, C2 and C3. The output voltage U12 between a tap C1 and a tap C2 of the autotransformer TB2 is different from the output voltage U23 between a tap C2 and a tap C3, and the voltage U23 is 2 times of the voltage U12; the thyristor switch group has 6 excitation coil voltage compensation states of forward direction U12, forward direction U23, forward direction U12+ U23, reverse direction U12, reverse direction U23 and reverse direction U12+ U23 at most, and a0 voltage compensation state when the input voltage is within the normal range is applied, so that the alternating current power supply voltage input by the phase line input end LA1 can be divided into 7 voltage intervals for compensation control at most. In fig. 2, N is a zero line, and G11, G12 to G61, and G62 are trigger signal input ends of the triacs SR1 to SR6, respectively. In fig. 2, the bidirectional thyristors SR1, SR3, and SR5 constitute the same-side thyristor, and the bidirectional thyristors SR2, SR4, and SR6 constitute the other same-side thyristor; in order to avoid short circuit, 2 or more than 2 thyristors in the thyristors at the same time can not be conducted simultaneously; for example, SR1, SR3 cannot be turned on simultaneously, SR4, SR6 cannot be turned on simultaneously, and so on.

FIG. 3 shows an embodiment 2 of the auto-coupling compensation type main circuit, which includes a compensation transformer TB1 and an auto-coupling transformer TB2, 8 bidirectional thyristors SR1-SR8 jointly form a thyristor switch group, and a fuse FU1, a relay normally-open switch KA-1 and a relay normally-closed switch KA-2 form a relay protection circuit.

In fig. 3, the compensation coil of the compensation transformer TB1 is connected in series to the phase line, where the input end of the phase line is LA1 and the output end is LA 2. The voltage on the excitation coil of TB1 is controlled by the thyristor switch group. The autotransformer TB2 is provided with 4 output taps C1, C2, C3 and C4, one ends of the bidirectional thyristors SR1, SR3, SR5 and SR7 are connected in parallel and then connected to one end of a TB1 excitation coil, and the other ends of the SR1, SR3, SR5 and SR7 are respectively connected to the taps C1, C2, C3 and C4; one ends of the bidirectional thyristors SR2, SR4, SR6 and SR8 are connected in parallel and then connected to the other end of the excitation coil of TB1, and the other ends of the SR2, SR4, SR6 and SR8 are respectively connected to the taps C1, C2, C3 and C4. The output voltage U12 between a tap C1 and a tap C2 of an autotransformer TB2, the output voltage U23 between the tap C2 and the tap C3, and the output voltage U34 between the tap C3 and the tap C4 are different, the voltage U23 is 3 times of the voltage U12, and the voltage U34 is 2 times of the voltage U12; the thyristor switch group comprises 12 excitation coil voltage compensation states of forward direction U12, forward direction U23, forward direction U34, forward direction U12+ U23, forward direction U23+ U34, forward direction U12+ U23+ U34, reverse direction U12, reverse direction U23, reverse direction U34, reverse direction U12+ U23, reverse direction U23+ U34 and reverse direction U12+ U23+ U34, and when an input voltage is in a normal range, the 0 voltage compensation state is applied, and the alternating current power supply voltage input by the phase line input end LA1 can be divided into at most 13 voltage intervals for compensation control. In fig. 3, N is a zero line, and G11, G12 to G81, and G82 are trigger signal input terminals of the triacs SR1 to SR8, respectively. In fig. 3, the bidirectional thyristors SR1, SR3, SR5 and SR7 constitute the same-side thyristor, and the bidirectional thyristors SR2, SR4, SR6 and SR8 constitute the other same-side thyristor; in order to avoid short circuit, 2 or more than 2 thyristors in the thyristors at the same time can not be conducted simultaneously; for example, SR1, SR7 cannot be turned on simultaneously, SR4, SR8 cannot be turned on simultaneously, and so on.

Each of the triacs of fig. 2 and 3 may be replaced by 2 antiparallel triacs. In fig. 2 and 3, the relay normally open switch and the relay normally closed switch form a relay protection switch.

Dividing the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals, sampling the alternating current power supply voltage by a sampling comparison unit to obtain an alternating current power supply voltage sampling value, comparing the alternating current power supply voltage sampling value by M comparators, and outputting a trigger gating control value formed by M binary digits; when the alternating current power supply voltage is in one of the M voltage grade intervals, the M bits trigger the corresponding one bit in the gating control value to be valid, and the other bits are invalid. The effective bit of the M bit trigger gating control value is high level, namely binary 1; the invalid bit is low level, i.e. binary 0; or, the effective bit of the M-bit trigger gating control value is low level, namely binary 0; the invalid bit is high, i.e. binary 1.

Fig. 4 shows an embodiment 1 of a sampling comparison unit, and compensation control is performed on the embodiment 1 of the self-coupled compensation type main circuit. In the alternating current power supply voltage sampling circuit, alternating current power supply voltage input from a phase line LA1 and a zero line N is subjected to voltage reduction through a transformer TV, is rectified by a rectifier bridge consisting of diodes DV1-DV4, and is subjected to filtering through a capacitor CV1 and voltage division through resistors RV1 and RV2, so that an alternating current power supply voltage sampling value U1 in a positive proportional relation with an effective value of the input alternating current power supply voltage is obtained.

In the multi-interval voltage comparator circuit shown in fig. 4, resistors RF1-RF8 form a voltage divider circuit, and 7 threshold voltages UF1-UF7 are obtained after voltage division of the power supply + VCC 1. The 7 comparators FA1-FA7 realize the comparison of the AC power supply voltage sampling value U1 and 7 threshold voltages UF1-UF7, the output trigger gate control value P2 is composed of the outputs Y11-Y17 of the 7 comparators FA1-FA7, and the voltage in the fluctuation range of the AC power supply voltage is divided into 7 voltage level ranges 1-7. The operational amplifier FA0 forms a follower, and an alternating current power supply voltage sampling value U1 is driven by the follower FA0 and then is simultaneously sent to the inverting input end of the comparator FA1-FA 7; the sampled value U1 of the AC power supply voltage can also be directly and simultaneously sent to the inverting input ends of the comparators FA1-FA7 without being driven by the follower FA 0; 7 threshold voltages UF1-UF7 are respectively supplied to the non-inverting inputs of the comparators FA1-FA 7. In fig. 4, the power supply + VCC1 may be replaced by another precision power supply, and the voltage divider circuit divides the precision power supply to make the threshold voltage more accurate. The operational amplifier FA0 and the comparators FA1-FA7 are preferably low-power single-power-supply rail-to-rail operational amplifiers, for example, single-channel rail-to-rail operational amplifiers with the static working power supply current smaller than 1mA, such as OPA317, AD8517, MCP6291, TLV2450, TLV2451, TLV2460 and TLV2461, are selected.

In FIG. 4, the NOR gates FH2-FH7 constitute controllable power supplies for the comparators FA2-FA7, i.e., the power supplies for the comparators FA2-FA7 are controlled by the outputs Y11-Y16, respectively; the resistors RB2-RB7 are pull-down resistors of the outputs Y12-Y17 respectively, and when the power supply of the corresponding comparator is close to 0V and the output of the corresponding comparator is in a high-impedance state, the level is pulled to be low. The power supply of the comparator FA1 is connected to the power supply + VCC1, and is in a normal working state, and the output Y11 controls the power supplies of the comparators FA2-FA 7. For example, when the input ac power supply voltage is low and is in the lowest voltage class section 1 of 7 voltage class sections, Y11 outputs high level, all the outputs of nor gates FH2-FH7 are low level, all the single power supply sources of comparators FA2-FA7 are close to 0V, all the outputs are close to 0V or high resistance state, and resistors RB2-RB7 pull the outputs Y12-Y17 low level, respectively. When the input alternating current power supply voltage is higher than the lowest voltage grade interval 1 of 7 voltage grade intervals, Y11 outputs low level, NOR gate FH2 outputs high level to provide power supply for comparator FA2, at this time, if the input alternating current power supply voltage is in voltage grade interval 2, Y12 outputs high level, NOR gates FH3-FH7 all output low level, single power supply for comparators FA3-FA7 all approach 0V, the output all approach 0V or high impedance state, and resistors RB3-RB7 respectively pull output Y13-Y17 low level. When the input alternating current power supply voltage is higher than the voltage grade interval 2, Y11 and Y12 both output low level, NOR gates FH2 and FH3 both output high level, and power supplies are respectively provided for comparators FA2 and FA3, at this time, if the input alternating current power supply voltage is in the voltage grade interval 3, Y13 outputs high level, NOR gates FH4-FH7 all output low level, single power supplies of comparators FA4-FA7 all approach 0V, the outputs all approach 0V or are in high resistance state, and resistors RB4-RB7 respectively pull the outputs Y14-Y17 to low level. By analogy, when the input alternating-current power supply voltage is in the voltage class interval 4, the Y14 outputs high level, and other outputs are low level; when the input alternating current power supply voltage is in a voltage level interval 5, Y15 outputs high level, and other outputs are low level; when the input alternating current power supply voltage is in a voltage class interval 6, Y16 outputs high level, and other outputs are low level; when the input ac power supply voltage is in the voltage class interval 7, Y17 outputs a high level, and the other outputs are low levels. When the nor gate FH2-FH7 selects a 74HC series high-speed CMOS gate, for example, when the 8-input nor gate 74HC4078, the three-input nor gate 74HC27, the four-input nor gate 74HC02, etc. are selected, or when the nor gate function is realized by a 74HC series high-speed CMOS or nor gate, the high-level driving current of the 74HC series high-speed CMOS can reach 4mA, which is enough to drive a single-channel rail-to-rail operational amplifier with the static operating power supply current less than 1 mA. The power supply of the NOR gate FH2-FH7 is power supply + VCC 1.

The fluctuation range of the input alternating current power supply voltage is set as 220V +/-10%, and the input alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. By adopting the sampling comparison unit embodiment 1 in fig. 4, the voltage input between 242V and 198V can be divided into 7 voltage class intervals with the interval voltage size of 6.4V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of the 3 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 6.4V is not more than 220V +/-1.5 percent, and the requirement that the output is controlled within 220V +/-2 percent is met; the fluctuation interval of the alternating current power supply voltage corresponding to 7 voltage class intervals of 6.4V is 242.4V to 197.6V, and the actual fluctuation range is covered. The compensation is carried out by adopting the embodiment 1 of the self-coupling compensation type main circuit of FIG. 2, the input voltage of the autotransformer TB2 is alternating current 220V, and the compensation voltage of the TB1 is 6.4V when the output voltage U12 is used as the excitation coil voltage of the TB 1; when the output voltage U23 is only used as the excitation coil voltage of TB1, the TB1 compensation voltage is 12.8V; when the output voltages U12 and U23 are used as the excitation coil voltage of TB1, the compensation voltage of TB1 is 19.2V. The selection of the threshold voltages UF1-UF7 is related to the ratio between the sampled values of the AC supply voltage U1 and the AC supply voltage; setting the proportion of the alternating current power supply voltage sampling value U1 to the alternating current power supply voltage to be 0.01, namely the alternating current power supply voltage sampling value U1 is 1% of the effective value of the alternating current power supply voltage, and the voltage sampling value range corresponding to the voltage input between 242V and 198V is 2.42V to 1.98V; when the alternating current power supply voltage is divided into 7 voltage class intervals with interval voltage of 6.4V, 7 threshold voltages UF7-UF1 are 2.424V, 2.36V, 2.296V, 2.232V, 2.168V, 2.104V and 2.04V respectively, and correspond to voltage sampling values for dividing the voltage range from 242.4V to 197.6V into the upper limit values of the 7 voltage class intervals respectively; the size of the resistors RF1-RF8 can be calculated according to the size of the 7 threshold voltages UF1-UF7 and + VCC 1.

Since the compensation mode of the self-coupled compensation type main circuit embodiment 1 automatically has the schmitt characteristic, the comparator FA1 to the comparator FA7 do not constitute a schmitt comparator. The trigger strobe control value output in FIG. 4 is active high; and a stage of inverter is added at the output ends of the comparators FA1-FA7, and the output trigger gating control value becomes active low.

In embodiment 1 of the sampling comparison unit in fig. 4, when the input ac power voltage is lower than the minimum voltage level interval range, the output signal corresponding to the minimum voltage level interval in the output trigger gate control value is valid, that is, the output is Y11 valid; at the moment, the main circuit performs corresponding voltage reduction compensation according to the condition that the input alternating current power supply voltage is in the minimum voltage grade interval. When the voltage of the input alternating current power supply is higher than the range of the maximum voltage level interval, all signals in the output trigger gating control value are invalid, and the main circuit does not perform voltage compensation at the moment. If the comparator FA7 in the sampling comparison unit embodiment 1 of fig. 4 is removed, the 6 threshold voltages UF6-UF1 of the comparators FA6-FA1 are unchanged, being 7 intermediate divided voltage values of the voltage sample values corresponding to the alternating current power supply voltage values divided by 7 voltage class intervals; the output signal of the nor gate FH7, namely the highest interval judgment value Y17-1, is directly used as Y17 in the trigger gating control value, so that when the input alternating current power supply voltage is in or higher than the range of the maximum voltage class interval, the output of the Y17 is effective, and the main circuit performs corresponding voltage reduction compensation according to the condition that the input alternating current power supply voltage is in the maximum voltage class interval.

Embodiment 1 of fig. 4 can also be performed for the self-coupled compensation type main circuit embodiment 2, and in this case, the voltage in the fluctuation interval range of the ac power supply voltage needs to be divided into more voltage class intervals. For example, when the voltage in the fluctuation interval of the ac power supply voltage is divided into 13 voltage class intervals, the circuit of fig. 4 should be extended to 13 comparators for comparison with 13 threshold voltages of different sizes; or 12 comparators are adopted to compare with 12 threshold voltages with different sizes; the output trigger strobe control value P2 will consist of 13 bits, e.g., Y11-Y113.

Fig. 5 shows an embodiment 2 of a sampling comparison unit, which is used for performing compensation control on an embodiment 2 of a self-coupling compensation type main circuit. In fig. 5, FD1 is a true effective value detection device LTC1966, and the LTC1966, a transformer TV1, a capacitor CV2, and a capacitor CV3 constitute an ac power supply voltage sampling circuit, and the ac power supply voltage input from a phase line LA1 and a neutral line N is measured to obtain an ac power supply voltage sampling value U2. UIN1 and UIN2 of LTC1966 are alternating voltage differential input terminals, USS is a negative power input terminal capable of being grounded, UDD is a positive power input terminal, GND is a ground terminal, EN is a low-level effective enable control input terminal, UOUT is a voltage output terminal, and COM is an output voltage return terminal.

In fig. 5, FD2, resistor RD1, resistor RD2, and inverters FB1-FB10 form a multi-section voltage comparator circuit; FD2 is a 10-level comparison display driver LM3914, and the inside of the LM3914 includes 10 internal divider circuits formed by connecting 1k Ω precision resistors in series, and 10 comparison threshold voltages are formed and connected to the positive input ends of the 10 comparators in the LM respectively, and the voltage within the fluctuation range of the ac power supply voltage is divided into 10 voltage class ranges 1-10. Pin 6 is the high end of the internal divider circuit and is connected to the internal standard power supply output VREF of pin 7 through a resistor RD 1; pin 4 is the low end of the internal voltage divider circuit and is connected to the ground through a resistor RD 2; pin 8 is the low end of the internal standard power supply and is connected to the ground; pin 2 is a negative power supply end and is connected to the ground; pin 3 is a positive power supply terminal and is connected to a power supply + VCC 1; pin 5 is a signal input end, is connected to an alternating current power supply voltage sampling value U2 and is internally connected to the negative input ends of 10 comparators; signals L10-L1 output by pins 10-18 and pin 1 are output results of 10 comparators, wherein L10 has the highest comparison threshold voltage and is sequentially reduced, and L1 has the lowest comparison threshold voltage; L1-L10 are all active low; the mode control terminal of the 9 pins is floating, so that the point-like output from L1 to L10 is realized, namely, single low level output is effective. In fig. 5, the high side of the inner divider circuit can also be connected to other power supplies, such as power supply + VCC1, via resistor RD 1.

In fig. 5, 10 inverters FB1-FB10 are used to invert the output signals L1-L10, respectively, to obtain the active high-level trigger gate control value P2 composed of 10-bit binary Y11-Y110. When the ac power supply voltage is in one of 10 voltage class intervals 1 to 10, one bit of Y11 to Y110 is at a high level, and the other bits are at a low level. For example, when the input ac power supply voltage is in the voltage class section 10, Y110 outputs a high level, and the other outputs are low levels; when the input alternating current power supply voltage is in a voltage level interval 9, Y19 outputs high level, and other outputs are low level; when the input alternating current power supply voltage is in a voltage level interval 5, Y15 outputs high level, and other outputs are low level; when the input ac power supply voltage is in voltage class interval 1, Y11 outputs a high level, and the other outputs are low levels. The trigger gate control value is active low when the inverters FB1-FB10 in FIG. 5 are eliminated and the output signals L1-L10 are used directly as the trigger gate control values Y11-Y110. The inverters FB1-FB10 are all powered by the power supply + VCC 1.

In fig. 5, 10 comparators inside LM3914 are used to compare voltages in the input ac power supply voltage fluctuation interval range into 10 voltage class intervals. The input alternating current power supply voltage fluctuation range is set to be 220V + 10% to 220V-20%, and the output is required to be stabilized within the range of 220V +/-2%. By adopting the sampling comparison unit embodiment 2 of fig. 5, the voltage input between 242V and 176V is divided into 10 voltage class intervals with the interval voltage size of 7V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of the 6 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 7V is 220V +/-1.6%, the requirement that the output is controlled within 220V +/-2% is met, the alternating current power supply voltage fluctuation interval corresponding to 10 voltage class intervals of 7V is 244.5V to 174.5V, and the actual fluctuation range is covered. The compensation is carried out by adopting the embodiment 2 of the self-coupling compensation type main circuit shown in FIG. 3, the input voltage of the autotransformer TB2 is alternating current 220V, and the compensation voltage of the TB1 is 7V when the output voltage U12 is used as the excitation coil voltage of the TB 1; when the output voltage U23 is only used as the excitation coil voltage of TB1, the TB1 compensation voltage is 21V; when the output voltage U34 is only used as the excitation coil voltage of TB1, the TB1 compensation voltage is 14V; meanwhile, when the output voltages U12 and U23 are used as the excitation coil voltage of TB1, the compensation voltage of TB1 is 28V; and so on. The selection of the threshold voltage is related to the ratio between the sampled value of the ac supply voltage U2 and the ac supply voltage; if the ratio of the ac power supply voltage sampling value U2 to the ac power supply voltage is 0.005, that is, the ac power supply voltage sampling value U2 is 0.5% of the effective value of the ac power supply voltage, when the ac power supply voltage is divided into 10 voltage class intervals with interval voltage of 7V, the range of voltage sampling values corresponding to the voltage input between 242V and 176V is 1.21V to 0.88V; the 10 threshold voltages are respectively 1.1875V, 1.1525V, 1.1175V, 1.0825V, 1.0475V, 1.0125V, 0.9775V, 0.9425V, 0.9075V and 0.8725V, and respectively correspond to voltage sampling values for dividing a voltage in the range of 244.5V to 174.5V into lower limit values of 10 voltage class intervals; the voltage at the high end of the inner voltage divider circuit is connected to the positive input end of the highest comparator, so that the voltage at the 6 pin is 1.1875V. From the 10 threshold voltages and the magnitude of the internal standard power supply output VREF (1.2V or 1.25V), and the magnitude of the internal 10 precision resistors, the magnitudes of the resistors RD1, RD2 can be calculated. If the precision of voltage compensation is required to be improved or the fluctuation range of the input voltage is required to be larger, the sampling comparison unit in embodiment 2 of fig. 5 is required to divide the voltage class into more voltage class intervals, for example, when the voltage in the fluctuation range of the ac power supply voltage needs to be divided into 13 voltage class intervals, 2 LM3914 slices can be adopted for implementation, and the inner voltage divider circuits in the 2 LM3914 slices are connected in series to form 20 comparison threshold voltages, so as to form a 20-stage comparator circuit; with 13 of the comparison outputs selected, the output trigger strobe control value P2 will consist of 13 bits, e.g., Y11-Y113.

In embodiment 2 of the sampling comparing unit in fig. 5, when the input ac power voltage is higher than the range of the maximum voltage class interval, the output trigger strobe control value is valid for the output signal corresponding to the maximum voltage class interval, that is, the output is valid for Y110, and the main circuit performs corresponding voltage step-down compensation according to the ac power voltage in the maximum voltage class interval. When the input alternating current power supply voltage is lower than the range of the minimum voltage grade interval, all signals in the output trigger gating control value are invalid, and the main circuit does not perform voltage compensation at the moment.

In fig. 5, 10 comparators out of 10 comparators in LM3914 are used to divide the ac power supply voltage comparison into 10 voltage class intervals. Only 9 comparators in 10 comparators in LM3914 can be adopted to compare and divide the alternating current power supply voltage into 10 voltage grade intervals; for example, the comparison threshold voltage of each comparator is not changed, and the comparison threshold voltages of 9 comparators are 9 middle division voltage values of the voltage sampling values corresponding to the alternating-current power supply voltage values divided by 10 voltage class intervals; instead of using the inverted output L1 of LM3914 in FIG. 5 as Y11 in the trigger gate control value, Y11 is selected and generated by Y12-Y110 in the trigger gate control value, namely Y11 is enabled when all Y12-Y110 are disabled, otherwise Y11 is disabled; at the moment, when the input alternating current power supply voltage is in or is higher than the range of the maximum voltage grade interval, the output trigger gating control value is Y110 valid, and the main circuit performs corresponding voltage reduction compensation according to the situation that the alternating current power supply voltage is in the maximum voltage grade interval; when the input alternating current power supply voltage is in or lower than the range of the minimum voltage class interval, Y11 output is effective, and the main circuit performs corresponding voltage boosting compensation according to the fact that the input alternating current power supply voltage is in the range of the minimum voltage class interval.

The sampling comparison unit embodiment 2 in fig. 5 can also perform compensation control on the self-coupling compensation type main circuit embodiment 1, and at this time, only the voltages within the fluctuation interval range of the input ac power voltage need to be divided into intervals of no more than 7 voltage levels, that is, the comparison output of no more than 7 levels is selected.

In addition to the sampling comparison unit embodiment shown in fig. 4 or 5, when compensation control is performed on the self-coupled compensation type main circuit embodiment 1 or embodiment 2, another ac power supply voltage sampling circuit and comparison circuit may be selected to implement the required functions. The ac power voltage sampling value U1 output by the ac power voltage sampling circuit of fig. 4 may be sent to the multi-interval voltage comparator circuit of fig. 5 for comparison, and a trigger gating control value is output; the sampled value U2 of the ac power voltage output by the ac power voltage sampling circuit of fig. 5 may be sent to the multi-interval voltage comparator circuit of fig. 4 for comparison, and a trigger gating control value is output.

Fig. 6 is a block diagram of an embodiment of a delay protection unit, wherein a delay detection module YC1 respectively delays an input trigger gate control value Y11-Y1M to obtain delayed trigger gate control values Y21-Y2M, and Y21-Y2M form P3; the YC1 module simultaneously and respectively carries out edge detection on signals Y11-Y1M of the trigger gating control value to obtain edge detection signals Y31-Y3M; the no-trigger area control signal generation module YC2 converts the input edge detection signals Y31-Y3M into the no-trigger area control signal P4 for output. In the block diagram of the embodiment in fig. 6, when the input of the delay detection module YC1 is the trigger gating control value output by the embodiment 1 of the sampling comparison unit in fig. 4, M is equal to 7; in the block diagram of the embodiment in fig. 6, when the input of the delay detection module YC1 is the trigger gating control value output by the embodiment 2 of the sampling comparison unit in fig. 5, M is equal to 10.

Fig. 7 shows an embodiment 1 of the delay detection circuit for the trigger strobe control value signal Y11 in the delay detection module. The resistor RY0, the capacitor CY0 and the driving gate FY0 realize signal delay of Y11, and a delayed signal Y21 of Y11 is obtained. The resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1 form a rising edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is output in the output signal YP1 of the inverter FY 1. The resistor RY2, the capacitor CY2, the diode DY2, the inverters FY2 and FY3 constitute a falling edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the falling edge of Y11 is output in the output signal YP2 of the inverter FY 3. The nand gate FY4 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY4, that is, when the input signal Y11 changes, the nand gate FY4 outputs a single pulse in the form of a positive pulse. In fig. 7, the drive gate FY0, inverter FY1, inverter FY3 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; the drive gate FY0 may consist of 2 inverters with schmitt inputs.

Fig. 8 shows an embodiment 2 of the delay detection circuit for the trigger strobe control value signal Y11 in the delay detection module. The inverter FY5, the resistor RY3 and the capacitor CY3 invert and delay the input signal Y11 to obtain a delayed inverted signal YP0 of Y11; the inverter FY6 inverts YP0 to obtain a delayed Y11 signal Y21. The signal input by the nand gate FY7 is a delayed inverted signal YP0 of Y11 and Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is generated in the output signal YP 1; the or gate FY8 receives the inverted signals YP0 of Y11 and Y11, and the output signal YP2 generates a single pulse in the form of a negative pulse corresponding to the falling edge of Y11. The nand gate FY9 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY9, that is, when the input signal Y11 changes, the nand gate FY9 outputs a single pulse in the form of a positive pulse. In fig. 8, inverter FY6, nand gate FY7, or gate FY8 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; nand gate select 74HC132, CD4093, etc.; or gate select 74HC7032 or 2 inverters with schmitt inputs and 1 nand gate to implement the or gate function.

Fig. 9 is a delay detection circuit embodiment 3 of the delay detection module for the trigger gate control value signal Y11, in which a rising edge detection circuit for the input signal Y11 is composed of a resistor RY1, a capacitor CY1, a diode DY1 and an inverter FY1, and a falling edge detection circuit for the input signal Y11 is composed of a resistor RY2, a capacitor CY2, a diode DY2, an inverter FY2 and an FY3, and a circuit for outputting the edge detection signal Y31 by using a nand gate FY4 is the same as in embodiment 1 of fig. 7. In fig. 9, the signal delay of Y11 is realized by inverters FY11, FY12, FY13, and FY14, and a delayed signal Y21 of Y11 is obtained.

The embodiments 1 to 3 in fig. 7, 8 and 9 are all delay detection circuits for the signal Y11 in the trigger strobe control value, and delay detection circuits for the other signals Y12 to Y1M in the trigger strobe control value, and the circuit structure and function of the delay detection circuit for the input signal Y11 in the corresponding embodiments are the same. The delay detection circuit may also adopt other circuits meeting the requirements to realize the functions thereof.

The function of the no-trigger area control signal generation module is to output a single pulse in the no-trigger area control signal when any one or more of the input edge detection signals for triggering the strobe control value generate a single pulse related to an edge. Fig. 10 shows an embodiment of the no-trigger area control signal generation module, in which a nor gate FY10 including M inputs performs corresponding functions, and the inputs of the nor gate FY10 are edge detection signals Y31-Y3M, and the output is a no-trigger area control signal P4. In the embodiment of fig. 10, the single pulse that does not trigger the output of the zone control signal is a negative pulse, i.e., the low level of the zone control signal is not active; when the nor gate FY10 is replaced by an or gate, the single pulse that does not trigger the zone control signal output is a positive pulse. If the single pulse associated with an edge generated in the input edge detection signals Y31-Y3M is a negative pulse, the nor gate FY10 in fig. 10 should be changed to a nand gate or an and gate to implement an or logic function under negative logic.

All gates in the delay protection unit are powered by a single power supply + VCC 1. Fig. 11 is a schematic diagram of a partial correlation waveform in the delay protection unit. From the principle and requirements of the sampling comparison unit, when the output trigger strobe control value is changed normally, 2 bits are changed every time. In fig. 11, Y11 in the trigger strobe control values has a rising edge change and a falling edge change respectively, and Y21 is the trigger strobe control value of Y11 delayed by T1 time; in embodiment 1 of the delay detection circuit in fig. 7, T1 is determined by the magnitude of the product of the resistor RY0 and the capacitor CY0 (i.e., the magnitude of the time constant); in embodiment 2 of the delay detection circuit in fig. 8, T1 is determined by the product of the resistor RY3 and the capacitor CY 3; in the embodiment 3 of the delay detection circuit in fig. 9, T1 is determined by the gate delay time of the inverters FY11, FY12, FY13 and FY 14. In fig. 11, the negative pulse width of the signal YP1 due to the rising edge of Y11 is T2; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T2 is determined by the magnitude of the product of the resistor RY1 and the capacitor CY 1; in embodiment 2 of the delay detection circuit in fig. 8, T2 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, the negative pulse width generated by the falling edge of Y11 in the signal YP2 is T3; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T3 is determined by the magnitude of the product of the resistor RY2 and the capacitor CY 2; in embodiment 2 of the delay detection circuit in fig. 8, T3 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, 2 positive pulses in the edge detection signal Y31 correspond to a negative pulse due to a rising edge of Y11 in the signal YP1 and a negative pulse due to a falling edge of Y11 in the signal YP2, respectively. When Y11 in the trigger gate control value in fig. 11 changes in rising edge, Y12 in the trigger gate control value changes in falling edge, and the corresponding edge detection signal Y32 generates a positive pulse correspondingly; when Y11 is changed by a falling edge, Y12 in the trigger gate control value is changed by a rising edge at the same time, and a positive pulse is correspondingly generated in the corresponding edge detection signal Y32; during this period, the other trigger gate control value signals except Y11 and Y12 are unchanged, and the edge detection signals corresponding to the other trigger gate control value signals except Y11 and Y12 are all at low level, which is not shown in fig. 11. According to the logical or function of the non-trigger area control signal generation module, the width of the single pulse output by the non-trigger area control signal generation module is the same as the widest pulse width of the input pulses in the input edge detection signals, and the width difference is caused by the difference between the resistance and capacitance values of T2 and T3 determined in the different delay detection circuits. In fig. 11, the 1 st positive pulse in Y31 is wider than the 1 st positive pulse in Y32, the 2 nd positive pulse in Y31 is narrower than the 2 nd positive pulse in Y32, the 1 st negative pulse width in the no-trigger-region control signal P4 coincides with the 1 st positive pulse width in the edge detection signal Y31, and the 2 nd negative pulse width in the no-trigger-region control signal P4 coincides with the 2 nd positive pulse width in the edge detection signal Y32.

In the embodiment 1 of the delay detection circuit of the delay protection unit in fig. 7, the delay time for the trigger gating control value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY1 and FY4 and FY10 in fig. 10, or the sum of the delay times of the gates FY3 and FY4 and FY10 in fig. 10; the selection range of the signal delay time T1 of the trigger gate control value determined by the product of the resistor RY0 and the capacitor CY0 is ms order of magnitude, obviously, is greater than the delay time of the trigger gate control value changing to the leading edge of the corresponding single pulse of the no-trigger area control signal, that is, the time of the delay change of the trigger gate control value signal is later than the leading edge time of the single pulse output after the trigger gate control value changes. Strictly speaking, T1 actually includes the sum of the delay time caused by resistor RY0 and capacitor CY0, and the delay time of gate FY 0. In embodiment 1 of fig. 7, when selecting parameters, the value of T2 and the value of T3 are both greater than the value of T1, so that the time of delayed change of the trigger gate control value signal meets the requirement of earlier time of the trailing edge of a single pulse of the control signal of the non-trigger area output after the change of the trigger gate control value.

In the embodiment 2 of the delay detection circuit in the delay protection unit in fig. 8, the delay time for the trigger gate control value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY7 and FY9 and FY10 in fig. 10, or the sum of the delay times of the gates FY8 and FY9 and FY10 in fig. 10; t1 is a value of ms magnitude, and it is obvious that the signal delay time T1 of the trigger gate control value determined by the product of the resistor RY3 and the capacitor CY3 is longer than the delay time of the trigger gate control value changing to the leading edge of the corresponding single pulse of the non-trigger area control signal, i.e. the time of the trigger gate control value signal delay changing is later than the leading edge of the single pulse output after the trigger gate control value changing. In the embodiment 2 of the delay detection circuit in fig. 8, both the time when the trigger gate control value signal changes in delay and the time when the trailing edge of the output single pulse after the trigger gate control value changes are affected by the change of the signal YP 0; the time when the delay of the trigger gating control value signal changes is the delay of the gate circuit FY6 after the signal YP0 changes; the trailing edge time of the single pulse output after the trigger gating control value is the sum of the delay time of the gate circuits FY7 and FY9 after the signal YP0 is changed and FY10 in the graph 10, or the sum of the delay time of the gate circuits FY8 and FY9 after the signal YP0 is changed and FY10 in the graph 10; obviously, the time of the delayed change of the trigger gating control value signal is less than the time of the back edge of the output single pulse after the change of the trigger gating control value by 2 gate circuits, and the requirement that the time of the delayed change of the trigger gating control value signal is earlier than the time of the back edge of the output single pulse after the change of the trigger gating control value is met.

Fig. 12 is a trigger circuit embodiment for triggering the self-coupling compensation type main circuit embodiment 1 in fig. 2 or triggering the triac SR1 in the self-coupling compensation type main circuit embodiment 2 in fig. 3, and the trigger circuit embodiment is composed of an ac trigger optocoupler UG1, a resistor RG1, and a resistor RG2, and the trigger control signal P51 is active at a low level. The alternating current trigger optocoupler UG1 can be selected from phase-shifting bidirectional thyristor output optocouplers such as MOC3022, MOC3023, MOC3052 and MOC 3053. Power supply + VCCK is the controlled power supply controlled by the protected drive unit. The circuit structure of the trigger circuit for triggering the bidirectional thyristors SR2-SR6 in the embodiment 1 of the self-coupling compensation type main circuit in FIG. 2 or the bidirectional thyristors SR2-SR8 in the embodiment 2 of the self-coupling compensation type main circuit in FIG. 3 is the same as that of the trigger bidirectional thyristor SR 1. The trigger pulses output by the alternating current trigger optocoupler UG1 in fig. 12 from G11 and G12 and the trigger pulses output by other alternating current trigger optocouplers in the trigger unit jointly form a trigger signal P6.

Fig. 13 shows an embodiment 1 of a trigger gate control unit, and compensation control is performed on the embodiment 1 of the self-coupling compensation type main circuit in fig. 2, wherein the fluctuation range of the ac power voltage is 220V ± 10%, and it is required to be stabilized within a range of 220V ± 2% for output. In fig. 13, the trigger gate control values Y21-Y27 inputted by the trigger gate control unit are active at high level, 14 diodes D11-D72, trigger gate control column lines Y21-Y27, and trigger drive row lines VK1-VK6 form a diode trigger gate matrix, resistors RS1-RS6 and triodes VS1-VS6 form a drive circuit of trigger control signals P51-P56, and at this time, P51-P56 form a trigger control signal P5.

Table 1 is a trigger gating control function table of the trigger gating control unit in embodiment 1, and lists 7 valid bits in 7 trigger gating control values, that is, on-off combination states of the bidirectional thyristors in the thyristor switch group corresponding to the 7 valid trigger gating control values. The 7 effective trigger gating control values correspond to the voltage level interval 1-7, and the trigger gating control unit controls the on-off state of the bidirectional thyristor in the self-coupling compensation type main circuit embodiment 1 to perform corresponding voltage compensation according to the trigger gating control values; in table 1, 1 represents that the corresponding triac needs to be in the on state, and 0 represents that the corresponding triac is in the off state. The diode-triggered gating matrix of FIG. 13 is functionally connected as required in Table 1, controlled by the trigger gating control values Y21-Y27; when a certain trigger gating control column line is effective, the diode enables a signal of the trigger driving column line which needs to be conducted with the bidirectional thyristor to be effective. For example, when the input voltage is at the lowest voltage level 1, that is, Y21 is at a high level, diodes D11 and D12 in the trigger gating matrix are turned on, triodes VS1 and VS6 are respectively controlled to be turned on when trigger driving row lines VK1 and VK6 are at a high level, so that P51 and P56 effectively turn on bidirectional thyristors SR1 and SR6, other diodes in the trigger gating matrix are turned off, other bidirectional thyristors are controlled to be turned off, and the output voltage U12+ U23 is used as the excitation coil voltage of TB1 for forward compensation; when the input voltage is in a voltage class 2, namely Y22 is effectively in a high level, diodes D21 and D22 in the trigger gating matrix are conducted, triodes VS3 and VS6 are respectively controlled to be conducted by the trigger driving row lines VK3 and VK6 in a high level, so that the P53 and P56 effectively turn on the bidirectional thyristors SR3 and SR6, other diodes in the trigger gating matrix are turned off, other bidirectional thyristors are controlled to be turned off, and the output voltage U23 is only used for forward compensation of the excitation coil voltage of the TB 1; when the input voltage is in a voltage level of 4, namely Y24 is effectively in a high level, diodes D41 and D42 in the trigger gating matrix are conducted, triodes VS5 and VS6 are respectively controlled to be conducted by the trigger driving row lines VK5 and VK6 in a high level, so that the P55 and P56 effectively turn on the bidirectional thyristors SR5 and SR6, other diodes in the trigger gating matrix are turned off, other bidirectional thyristors are controlled to be turned off, and 0-voltage compensation is realized, namely the voltage of the magnet exciting coil of the TB1 is 0; when the input voltage is at voltage level 5, namely Y25 is effectively at high level, diodes D51 and D52 in the trigger gating matrix are conducted, triodes VS2 and VS3 are respectively controlled to be conducted by the trigger driving row lines VK2 and VK3 at high level, so that the P52 and P53 effectively turn on the bidirectional thyristors SR2 and SR3, other diodes in the trigger gating matrix are turned off, other bidirectional thyristors are controlled to be turned off, and the reverse output voltage U12 is only used for carrying out reverse compensation on the excitation coil voltage of TB 1; and so on.

TABLE 1

Fig. 14 is embodiment 2 of a trigger gate control unit, and compensation control is also performed on embodiment 1 of the self-coupled compensation type main circuit of fig. 2; the fluctuation range of the alternating current power supply voltage is 220V +/-10%, and the alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. In fig. 14, the trigger gate control values Y21-Y27 inputted by the trigger gate control unit are active at low level, 14 diodes D11-D72, trigger gate control column lines Y21-Y27, and trigger drive row lines P51-P56 form a diode trigger gate matrix, and the trigger gate matrix directly outputs active low level trigger control signals P51-P56. In this embodiment 2, there is no driving circuit for triggering the control signals P51-P56.

The diode-triggered gating matrix of FIG. 14 is functionally connected as required in Table 1, controlled by the trigger gating control values Y21-Y27; for example, when the input voltage is the lowest voltage level 1, that is, Y21 is at a low level, diodes D11 and D12 in the trigger gating matrix are turned on to make P51 and P56 become effective low levels to turn on bidirectional thyristors SR1 and SR6, respectively, other diodes in the trigger gating matrix are turned off to control and turn off other bidirectional thyristors, and the output voltage U12+ U23 is used as the excitation coil voltage of TB1 for forward compensation; when the input voltage is in a voltage class 2, namely Y22 is effectively in a low level, diodes D21 and D22 in the gating matrix are triggered to be conducted, P53 and P56 are enabled to become effective low levels to turn on bidirectional thyristors SR3 and SR6 respectively, other diodes in the gating matrix are triggered to be cut off, other bidirectional thyristors are controlled to be turned off, and only the output voltage U23 is adopted to carry out forward compensation on the excitation coil voltage of TB 1; when the input voltage is in a voltage level of 4, namely Y24 is effectively in a low level, diodes D41 and D42 in the gating matrix are triggered to be conducted, P55 and P56 are changed into effective low levels to turn on bidirectional thyristors SR5 and SR6 respectively, other diodes in the gating matrix are triggered to be cut off, and other bidirectional thyristors are controlled to be turned off, so that 0 voltage compensation is realized; when the input voltage is in the voltage class 7, namely Y27 is effectively in a low level, diodes D71 and D72 in the gating matrix are triggered to be conducted, P52 and P55 are changed into effective low levels to turn on bidirectional thyristors SR2 and SR5 respectively, other diodes in the gating matrix are triggered to be cut off, other bidirectional thyristors are controlled to be turned off, and reverse output voltage U12+ U23 is adopted to be as excitation coil voltage of TB1 for reverse compensation; and so on.

In fig. 14, the low level in the trigger gating control value Y21-Y27 needs to directly drive the input end leds of 2 ac trigger optocouplers to emit light; when the alternating current trigger optocoupler selects MOC3022, MOC3052 and the like, a driving current of 20mA is needed; when the alternating current trigger optocoupler selects MOC3023, MOC3053 and the like, 10mA of driving current is needed.

FIG. 15 shows an embodiment 3 of a trigger gate control unit, which performs compensation control on the embodiment 2 of the self-coupled compensation type main circuit of FIG. 3, wherein the fluctuation range of the AC power voltage is 220V + 10% to 220V-20%, and the AC power voltage is required to be stabilized within the range of 220V + -2% for output. In fig. 15, the trigger gate control values Y21-Y210 input by the trigger gate control unit are active at high level, 20 diodes D01-D92, trigger gate control column lines Y21-Y210, and trigger drive row lines VK1-VK8 form a diode trigger gate matrix, resistors RS1-RS8 and transistors VS1-VS8 form a drive circuit of trigger control signals P51-P58, and at this time, the trigger control signals P5 are formed by P51-P58.

Table 2 is a trigger gating control function table of the trigger gating control unit in embodiment 3, and lists 10 valid bits in the 10-bit trigger gating control values, that is, the on-off combination state of the bidirectional thyristor in the thyristor switch group corresponding to the 10 valid trigger gating control values. The 10 effective trigger gating control values correspond to the voltage levels of 1-10, and the trigger gating control unit controls the on-off state of the bidirectional thyristor in the self-coupling compensation type main circuit embodiment 2 to perform corresponding voltage compensation according to the trigger gating control values; in table 2, 1 represents that the corresponding triac needs to be in the on state, and 0 represents that the corresponding triac needs to be in the off state. The diode triggered gating matrix of fig. 15 is functionally connected as required in table 2, controlled by triggered gating control values Y21-Y210; for example, when the input voltage is at voltage level 7, that is, Y27 is at high level, diodes D71 and D72 in the trigger gating matrix are turned on, transistors VS7 and VS8 are controlled to be turned on to trigger and drive row lines VK7 and VK8 to be at high level respectively, so that thyristors SR7 and SR8 are effectively turned on by P57 and P58, and other diodes in the trigger gating matrix are turned off to turn off other thyristors, thereby realizing 0-voltage compensation, that is, the field coil voltage of TB1 is 0; when the input voltage is at a voltage level of 8, namely Y28 is effectively at a high level, diodes D81 and D82 in the trigger gating matrix are switched on, triodes VS2 and VS3 are respectively controlled to be switched on by triggering and driving row lines VK2 and VK3 to be at a high level, so that the P52 and P53 effectively switch on the bidirectional thyristors SR2 and SR3, other diodes in the trigger gating matrix are switched off, other bidirectional thyristors are switched off, and the reverse output voltage U12 is only adopted to carry out reverse compensation on the excitation coil voltage of the TB 1; when the input voltage is in a voltage class of 9, namely Y29 is effectively in a high level, diodes D91 and D92 in the trigger gating matrix are conducted, triodes VS6 and VS7 are respectively controlled to be conducted by the trigger driving row lines VK6 and VK7 in a high level, so that the P56 and P57 effectively turn on the bidirectional thyristors SR6 and SR7, other diodes in the trigger gating matrix are turned off, other bidirectional thyristors are turned off, and the reverse output voltage U34 is only used for carrying out reverse compensation on the excitation coil voltage of the TB 1; when the input voltage is in a voltage level of 10, namely Y210 is effectively in a high level, diodes D01 and D02 in the trigger gating matrix are conducted, triodes VS4 and VS5 are respectively controlled to be conducted by trigger driving row lines VK4 and VK5 to be in a high level, so that the P54 and P55 effectively turn on the bidirectional thyristors SR4 and SR5, other diodes in the trigger gating matrix are turned off, other bidirectional thyristors are turned off, and the reverse output voltage U23 is only used for carrying out reverse compensation on the excitation coil voltage of TB 1; when the input voltage is at voltage level 6, namely Y26 is effectively at high level, diodes D61 and D62 in the trigger gating matrix are switched on, triodes VS1 and VS4 are respectively controlled to be switched on by the trigger driving row lines VK1 and VK4 at high level, so that the P51 and P54 effectively turn on the bidirectional thyristors SR1 and SR4, other diodes in the trigger gating matrix are switched off, other bidirectional thyristors are switched off, and the output voltage U12 is only used for forward compensation of the excitation coil voltage of TB 1; when the input voltage is in a voltage level of 4, namely Y24 is effectively in a high level, diodes D41 and D42 in the trigger gating matrix are conducted, triodes VS3 and VS6 are respectively controlled to be conducted by the trigger driving row lines VK3 and VK6 in a high level, so that the P53 and P56 effectively turn on the bidirectional thyristors SR3 and SR6, other diodes in the trigger gating matrix are turned off, other bidirectional thyristors are turned off, and the output voltage U23 is only used for forward compensation of the excitation coil voltage of TB 1; when the input voltage is in a voltage class of 3, namely Y23 is effectively in a high level, diodes D31 and D32 in a trigger gating matrix are switched on, triodes VS1 and VS6 are respectively controlled to be switched on by triggering and driving row lines VK1 and VK6 to be in a high level, so that the P51 and the P56 effectively turn on the bidirectional thyristors SR1 and SR6, other diodes in the trigger gating matrix are switched off, other bidirectional thyristors are switched off, and the output voltage U12+ U23 is used as excitation coil voltage of the TB1 for forward compensation; when the input voltage is in a voltage level 1, namely Y21 is effectively in a high level, diodes D11 and D12 in a trigger gating matrix are conducted, triodes VS1 and VS8 are respectively controlled to be conducted by the trigger driving row lines VK1 and VK8 in a high level, so that the P51 and P58 effectively turn on the bidirectional thyristors SR1 and R8, other diodes in the trigger gating matrix are cut off, other bidirectional thyristors are turned off, and the output voltage U12+ U23+ U34 is used for forward compensation of the excitation coil voltage of TB 1; and so on.

TABLE 2

When the trigger gate control values Y21-Y210 in table 2 are active at low level, a trigger gate matrix is composed of 20 diodes D01-D92, trigger gate control column lines Y21-Y210, and trigger control row lines P51-P58, and the trigger gate matrix directly outputs active low level trigger control signals P51-P58, according to the method of embodiment 2 of the trigger gate control unit in fig. 14. At this time, the low level in the trigger gating control value Y21-Y210 also needs to directly drive the input end light emitting diodes of the 2 alternating current trigger optocouplers to emit light; when the alternating current trigger optocoupler selects MOC3022, MOC3052 and the like, a driving current of 20mA is needed; when the alternating current trigger optocoupler selects MOC3023, MOC3053 and the like, 10mA of driving current is needed.

FIG. 16 is a diagram of an embodiment of an error detection and determination unit, which determines the trigger strobe control value P3, i.e. the high-level valid 10-bit trigger strobe control values Y21-Y210, and outputs a trigger strobe control value determination signal P7 with valid high level and invalid low level; that is, the output P7 is 1, indicating that the trigger strobe control value is valid; the output P7 is 0 indicating that the trigger strobe control value is invalid. In FIG. 16, the full adder FJ1-FJ8 constitutes a circuit for counting the number of "1" in the 10-bit trigger strobe control values Y21-Y210; wherein n2 and n1 are the number statistical values of '1' in Y21-Y23, m2 and m1 are the number statistical values of '1' in Y24-Y26, j3, j2 and j1 are the number statistical values of '1' in Y21-Y27, and q4, q3, q2 and q1 are the number statistical values of '1' in Y21-Y210. The AND gate FY20 judges the number statistics values q4, q3, q2 and q1 of ' 1 ' in Y21-Y210, and only when q4, q3, q2 and q1 are respectively 0, 0 and 1, the output trigger gate control value judgment signal P7 is valid, namely P7 is 1, which means that only 1 ' exists in the 10-bit trigger gate control values Y21-Y210, namely only one bit of the output is high level, and the trigger gate control value is valid; when the output trigger strobe control value decision signal P7 is invalid, i.e., P7 is 0, it indicates that there are not 1 "in the 10-bit trigger strobe control values Y21-Y210, indicating that the trigger strobe control value is invalid. If the effective 10-bit trigger gate control value Y21-Y210 with low level needs to be judged, only one stage of inverter needs to be added behind the input 10-bit trigger gate control value Y21-Y210, and the output q4, q3, q2 and q1 are the number statistical value of '0' in the 10-bit trigger gate control value Y21-Y210; similarly, only when q4, q3, q2 and q1 are respectively 0, 0 and 1, the trigger strobe control value discrimination signal P7 is enabled, that is, P7 is 1, which means that only 1 "0" is provided in the 10-bit trigger strobe control values Y21-Y210, that is, only one bit is output at low level, and the trigger strobe control value is enabled; when the output P7 is 0 invalid, it indicates that there are not 1 "0" in the 10-bit trigger strobe control values Y21-Y210, indicating that the trigger strobe control value is invalid.

If the AND gate FY20 in FIG. 16 is changed into a NAND gate, the strobe control value is triggered to judge that the low level of the signal is effective and the high level is ineffective; that is, the output P7 is 1, indicating that the trigger strobe control value is invalid; the output P7 is 0 indicating that the trigger strobe control value is valid.

When the trigger strobe control value P3 is 7 bits and it is necessary to determine the 7-bit trigger strobe control values Y21-Y27 which are active at high level, the method is to connect all Y28-Y210 in FIG. 16 to 0, and determine whether the trigger strobe control values are active by determining whether q4, q3, q2 and q1 are 0, 0 and 1. The second method is to remove the full adder FJ5-FJ8 in FIG. 16, and judge whether the trigger gating control value is valid or not by using the number statistical values j3, j2 and j1 of '1' in Y21-Y27 as 0, 0 and 1; only when j3, j2 and j1 are respectively 0, 0 and 1, the trigger strobe control value is only 1 'in 7-bit trigger strobe control values Y21-Y27, namely only one bit of the output is high level, the trigger strobe control value is valid, the output P7 is 1, otherwise, the trigger strobe control value is not 1' in 7-bit trigger strobe control values Y21-Y27, the trigger strobe control value is invalid, and the output P7 is 0. The logic devices such as the full adder, the NAND gate and the like in the circuit diagram of the power supply circuit in FIG. 16 are all powered by a single power supply + VCC 1.

The function of the error detection judging unit is to enable the output trigger gating control value judging signal P7 to be effective when judging that only one of M bits of the trigger gating control value is effective, or to enable the output trigger gating control value judging signal P7 to be ineffective; that is, when not only one of the M bits of the trigger strobe control value is valid, or when no one of the M bits of the trigger strobe control value is valid, the output trigger strobe control value determination signal P7 is invalidated. The logic functions may also be implemented in other ways, for example in ROM memory, or in a combination of and, or, not logic gates.

FIG. 17 shows an embodiment of the protection driving unit, wherein the high level of the input trigger gate control value determining signal P7 is asserted, i.e. P7 is 1 to indicate that the trigger gate control value is asserted; the P7 is inactive low, i.e., P7 is 0, indicating that the trigger strobe control value is inactive. The low level of an input control signal P4 of the non-trigger area is effective, namely when P4 is equal to 0, the control value of the trigger gating is changed due to the fact that the alternating current power supply voltage fluctuates, switching of the on-off state of a bidirectional thyristor in a thyristor switch group is needed, and a compensation mode is changed; in the switching process, in order to avoid that 2 or more than 2 thyristors are simultaneously conducted in the thyristors at the same side due to the delayed turn-off factor of the bidirectional thyristors, so as to cause a power supply short circuit, all the bidirectional thyristors in the thyristor switch group are turned off in the effective period of the control signal of the non-trigger area, namely when the P4 of the embodiment is equal to 0.

In fig. 17, a transistor VT, a relay coil KA, a freewheeling diode VD, and a resistor RK1 form a protection control circuit, a transistor VK1, a transistor VK2, a resistor RK2, a resistor RK3, and an and gate FY21 form a trigger unit controlled power control circuit, and the and gate FY21 is powered by a single power supply + VCC 1. The + VCC2 is the power supply for the relay coil and the source supply for the controlled power supply + VCCK in the trigger unit. When the input trigger gating control value judging signal P7 is at a low level, namely the trigger gating control value is invalid, the AND gate FY21 outputs a low level, the triodes VK1 and VK2 are cut off, the controlled power supply + VCCK loses power, the trigger unit does not have a power supply and does not work, namely, the trigger unit does not send out trigger pulses for triggering the bidirectional thyristor; p7 is low level and controls the transistor VT to stop, the relay coil KA loses power, so that the self-coupling compensation type main circuit embodiment 1 in fig. 2 or the relay normally open switch KA-1 in the self-coupling compensation type main circuit embodiment 2 in fig. 3 is turned off, that is, the input side power supply voltage of the autotransformer is controlled to be turned off, the voltage between all taps of the autotransformer is 0, and the protection of the thyristor switch group is realized; the normally closed relay switch KA-2 is closed, and the voltage applied to the excitation coil of TB1 is set to 0. When the sampling comparison unit fails to work to cause the trigger gating control value to be invalid, or the input alternating current power supply voltage is lower than the range of the minimum voltage level interval to cause the output trigger gating control value to be invalid, the protection driving unit cuts off the power supply of the trigger unit no matter whether the input non-trigger area control signal P4 is valid or not, stops sending out trigger pulses of all the bidirectional thyristors, and controls to cut off the input side power supply voltage of the autotransformer to realize the protection of the thyristor switch group. When the input trigger gating control value judging signal P7 is at a high level, that is, the trigger gating control value is valid, the control triode VT is turned on, and the relay coil KA is powered on, so that the self-coupling compensation type main circuit embodiment 1 shown in fig. 2 or the relay normally-open switch KA-1 shown in the self-coupling compensation type main circuit embodiment 2 shown in fig. 3 is turned on, the relay normally-closed switch KA-2 is turned off, and the circuit is in a compensation working state. When the trigger gating control value is valid, namely P7 is 1, and the control signal of the non-trigger area is valid, namely P4 is equal to 0, the AND gate FY21 outputs low level, the triodes VK1 and VK2 are cut off, the controlled power supply + VCCK loses power, the trigger unit does not work, namely the trigger pulse for triggering the bidirectional thyristor is not sent out, all the bidirectional thyristors in the thyristor switch group are cut off, the alternating-current power supply voltage at the moment is fluctuated, the trigger gating control value is changed, the electronic switch of the thyristor needs to be switched, and the compensation mode is changed. When the trigger gating control value is valid, namely P7 is 1, and the control signal of the non-trigger area is invalid, namely P4 is equal to 1, the AND gate FY21 outputs high level, the triodes VK1 and VK2 are both conducted, the controlled power supply + VCCK is electrified, the trigger unit works normally, the trigger gating control unit selects the corresponding trigger control signal to be valid according to the valid trigger gating control value corresponding to a certain voltage grade interval, the trigger unit sends out trigger pulse to control the on-off state of the bidirectional thyristors in the thyristor switch group, and the main circuit is in a compensation working state corresponding to the voltage grade interval.

When the error detection judging unit judges that the input trigger gating control value is invalid, the protection driving unit sends a protection control signal to the main circuit, so that the thyristor switch group is in a protection state, the alternating current voltage stabilizer does not compensate the input voltage, and the voltage output by the voltage stabilizer is the input alternating current power supply voltage. When the thyristor switch group is in the protection state, if the error detection judging unit judges that the input trigger gating control value is recovered to be an effective signal, the protection driving unit automatically stops the protection state of the thyristor switch group, and the thyristor switch group is in the compensation working state again.

As can be known from the above embodiments and the working process thereof, when the input is the effective trigger gating control value, the trigger gating control unit ensures that the thyristors at the same side in the self-coupling compensation type main circuit thyristor switch group are not conducted at the same time, thereby realizing the interlocking control of the thyristors; when the trigger gating control value is invalid, the protection driving unit simultaneously cuts off the power supply of the autotransformer on the basis of rapidly cutting off the power supply of the trigger unit and avoiding short circuit caused by error conduction of the bidirectional thyristor, so that the thyristor switch group is in a protection state. When the thyristor switch group is in the protection state, if the error detection judging unit judges that the alternating current voltage stabilizer enters the normal logic control state again, namely the error detection judging unit judges that the input trigger gating control value is recovered to be an effective signal, the protection driving unit can automatically stop the protection state of the thyristor switch group and enable the thyristor switch group to be in the compensation working state again. The function effectively strengthens the protection force of the alternating current voltage stabilizer against the abnormity of the working process, so that the working process of the partition self-coupling compensation alternating current voltage stabilization control method is more reliable.

Besides the technical features described in the specification, other techniques of the partitioned self-coupled compensation ac voltage stabilization control method are conventional techniques known to those skilled in the art.

Claims

1. A control method for partitioned self-coupling compensation alternating current voltage stabilization is characterized in that: dividing the voltage in the alternating current power supply voltage fluctuation interval range into a plurality of voltage grade intervals for compensation control; identifying the voltage grade interval of the alternating-current power supply voltage to obtain a trigger gating control value; controlling the on-off combination state of the thyristors in the thyristor switch group by the delayed trigger gating control value; the on-off combined state of the thyristors in the thyristor switch group controls and selects 0 or 1 or the superposition of a plurality of voltages in a plurality of output voltages of the autotransformer as the excitation coil voltage of the compensation transformer to realize the voltage compensation state corresponding to the voltage grade interval; each voltage grade interval of the alternating current power supply voltage corresponds to a voltage compensation state;

identifying the voltage grade interval of the alternating-current power supply voltage to obtain a trigger gating control value, wherein the trigger gating control value is realized by a sampling comparison unit; judging whether the delayed trigger gating control value is effective or not by an error detection judging unit which is a logic circuit; when the trigger gating control value is invalid, the thyristor switch group is controlled to be in a protection state by the protection driving unit; the delay protection unit inputs a trigger gating control value and outputs the delayed trigger gating control value;

trigger gating control value ofMA bit binary value; the criterion for judging whether the trigger gating control value is valid is thatMIf one and only one bit in the binary bit values is valid, the gating control value is triggered to be valid; otherwise, triggering the gating control value to be invalid; the above-mentionedMIs an integer of 2 or more;

the protection driving unit stops/starts protection of the thyristor switch group according to whether the trigger gating control value is effective or not, and the specific method is that when the trigger gating control value is ineffective, the input side power supply voltage of the autotransformer is controlled to be disconnected to enable the thyristor switch group to be in a protection state;

the sampling comparison unit comprises an AC power supply voltage sampling circuit and multiple regionsThe alternating-current power supply voltage sampling circuit converts the effective value of the alternating-current power supply voltage into a sampling value of the alternating-current power supply voltage; sampling value of multi-interval voltage comparator circuit to AC power supply voltage andM-1 threshold voltage is compared to obtainMA bit triggered gating control value;

the method for controlling the on-off combination state of the thyristor switch group by the trigger gating control value is that the diode trigger gating matrix selects and enables the corresponding trigger control signal according to the trigger gating control value to control the on-off combination state of the thyristor switch group.

2. The partitioned self-coupling compensation alternating-current voltage stabilization control method according to claim 1, characterized by comprising the following steps of: a multi-interval voltage comparator circuit includesM-1 number of comparators to be compared,M-1 comparator is powered by a positive single power supply;M-1 different threshold voltages are connected toM-1 non-inverting input of comparators with simultaneous connection of sampled values of the AC supply voltageM-1 inverting input of a comparator;Mamong the 1 comparators, the comparator with the lowest threshold voltage is directly powered by a positive single power supply, and the other comparators are powered by controllable power supplies; when the comparator is powered by a controllable power supply, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages lower than the threshold voltages output low levels, otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator; the comparator adopts a controllable power supply to supply power, and outputs a low level when the controllable power supply stops supplying power to the positive power supply end;Mbit-triggered gating control valueM-1 comparator output value and highest interval decision value; when in useM-when all of the output values of the 1 comparators are at low level, the highest interval judgment value is at high level, otherwise, the highest interval judgment value is at low level.

3. The partitioned self-coupling compensation alternating-current voltage stabilization control method according to claim 1, characterized by comprising the following steps of: in common in thyristor switch groupsNA plurality of thyristors; the diode triggered gating matrix comprisesMA root trigger gating control column line,NRoot triggered driving rowA wire and a plurality of diodes;Mroot-triggered strobe control column line andMthe bit trigger gating control values correspond to one another, and one trigger gating control value correspondingly enables one trigger gating control column line signal to be effective; the N trigger driving row lines correspond to the N thyristors one by one, and the effective correspondence of a trigger driving row line signal enables a trigger control signal of one thyristor to be effective;

when each trigger gating control column line signal is effective, the on-off combination state of the thyristor in the corresponding thyristor switch group is controlled; when each trigger gating control column line is effective with the column line signal, a diode is arranged between the trigger driving row lines which are required to control the conduction of the thyristor and are in a corresponding on-off combination state for connection, and when a certain trigger gating control column line signal is effective, the diode enables the trigger driving row line signal which is required to control the conduction of the thyristor to be effective.

4. The sectional self-coupling compensation alternating current voltage stabilization control method according to claim 3, characterized in that: when the trigger gating control value changes and the thyristor switch group needs to be switched to be in different on-off combination states, maintaining a non-trigger area time between the 2 on-off combination states, and turning off all thyristors in the thyristor switch group.

5. The sectional self-coupling compensation alternating current voltage stabilization control method according to claim 4, characterized in that: the maintaining of the one non-trigger area time is realized by a non-trigger area control signal; controlling the control signal of the non-trigger area to output a single pulse after the trigger gating control value is changed; the control signal of the non-trigger area is effective in the period of outputting the single pulse and is ineffective in the period of not outputting the single pulse; and when the control signal of the non-trigger area is effective, maintaining a time of the non-trigger area.

6. The sectional self-coupling compensation alternating current voltage stabilization control method according to claim 5, characterized in that: the trigger control signal for controlling the thyristor switch group is generated by the delayed trigger gating control value; the delayed signal change time of the trigger gating control value is later than the leading edge time of a single pulse in the non-trigger area control signal after the trigger gating control value is changed and earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the trigger gating control value is changed.