CN109346581B - Epitaxial wafer of light emitting diode and preparation method thereof - Google Patents

Epitaxial wafer of light emitting diode and preparation method thereof Download PDF

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CN109346581B
CN109346581B CN201810919463.6A CN201810919463A CN109346581B CN 109346581 B CN109346581 B CN 109346581B CN 201810919463 A CN201810919463 A CN 201810919463A CN 109346581 B CN109346581 B CN 109346581B
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layer
superlattice structure
epitaxial wafer
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emitting diode
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CN109346581A (en
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程丁
韦春余
周飚
胡加辉
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure

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Abstract

The invention discloses an epitaxial wafer of a light-emitting diode and a preparation method thereof, belonging to the field of light-emitting diode manufacturing. A superlattice structure comprising indium nitride and gallium nitride which are alternately stacked is arranged between the electron blocking layer and the P-type GaN layer, the superlattice structure of the indium nitride and the gallium nitride can play a role in reducing dislocation and defects in the epitaxial layer, and the overall quality of the epitaxial wafer can be improved. And because the potential barrier of the indium nitride in the superlattice structure is low, a large amount of holes can be accumulated at the indium nitride in the superlattice structure before the holes move into the active layer, and the large amount of holes accumulated in the superlattice structure provide a large hole base number, so that the number of the holes which can enter the active layer at the same time is increased, the number of the holes which can be compounded with electrons in the active layer is increased, the compounding efficiency of the electrons in the active layer is improved, and the light emitting efficiency of the light emitting diode is improved.

Description

Epitaxial wafer of light emitting diode and preparation method thereof
Technical Field
The invention relates to the field of light emitting diode manufacturing, in particular to an epitaxial wafer of a light emitting diode and a preparation method thereof.
Background
The light emitting diode is a semiconductor diode capable of converting electric energy into light energy, has the advantages of small volume, long service life, low power consumption and the like, and is widely applied to automobile signal lamps, traffic signal lamps, display screens and lighting equipment at present. The epitaxial wafer is a basic structure for manufacturing the light emitting diode, and the structure of the epitaxial wafer comprises a substrate and an epitaxial layer grown on the substrate. Wherein, the structure of epitaxial layer mainly includes: the buffer layer, the N-type GaN layer, the active layer, the electron blocking layer and the P-type GaN layer are sequentially grown on the substrate.
When a certain voltage is applied to the epitaxial wafer, electrons in the N-type GaN layer and holes in the P-type GaN layer move to the active layer and recombine in the active layer to emit light. However, since the number of electrons provided by the N-type GaN layer is much larger than the number of holes provided by the P-type GaN layer, the number of holes moving into the active layer is much smaller than the number of electrons moving into the active layer, and the recombination efficiency of electrons in the active layer is low, which leads to low light emitting efficiency of the light emitting diode.
Disclosure of Invention
The embodiment of the invention provides an epitaxial wafer of a light-emitting diode and a preparation method thereof, which can improve the light-emitting efficiency of the light-emitting diode. The technical scheme is as follows:
the embodiment of the invention provides an epitaxial wafer of a light-emitting diode, which comprises a substrate, and a buffer layer, an N-type GaN layer, an active layer, an electron blocking layer, a superlattice structure and a P-type GaN layer which are sequentially stacked on the substrate,
the superlattice structure comprises indium nitride layers and gallium nitride layers which are alternately stacked.
Optionally, the epitaxial wafer further comprises a magnesium nitride layer disposed between the superlattice structure and the P-type GaN layer.
Optionally, the indium component in the indium nitride layer is in a molar content of 0.05 to 0.1.
Optionally, the number of the indium nitride layers is 3 to 9.
Optionally, the thickness of the indium nitride layer is 5-20 nm, and the thickness of the gallium nitride layer is 10-40 nm.
Optionally, the thickness of the magnesium nitride layer is 1-10 nm.
Optionally, the magnesium component in the magnesium nitride layer has a molar content of 0.005-0.01.
The embodiment of the invention provides a preparation method of an epitaxial wafer of a light-emitting diode, which comprises the following steps:
providing a substrate;
growing a buffer layer on the substrate;
growing an N-type GaN layer on the buffer layer;
growing an active layer on the N-type GaN layer;
growing an electron blocking layer on the active layer;
growing a superlattice structure on the electron blocking layer;
growing a P-type GaN layer on the superlattice structure,
wherein the superlattice structure comprises indium nitride layers and gallium nitride layers which are alternately stacked.
Optionally, the growth temperature of the superlattice structure is 600 ℃ to 1000 ℃.
Optionally, when the superlattice structure is grown on the electron blocking layer, the flow rate of indium introduced into the reaction chamber is 300-700 sccm.
The technical scheme provided by the embodiment of the invention has the following beneficial effects: a superlattice structure comprising indium nitride and gallium nitride which are alternately stacked is arranged between the electron blocking layer and the P-type GaN layer, the superlattice structure of the indium nitride and the gallium nitride can play a role in reducing dislocation and defects in the epitaxial layer, and the overall quality of the epitaxial wafer can be improved. And because the potential barrier of the indium nitride in the superlattice structure is low, a large amount of holes can be accumulated at the indium nitride in the superlattice structure before the holes move into the active layer, and the large amount of holes accumulated in the superlattice structure provide a large hole base number, so that the number of the holes which can enter the active layer at the same time is increased, the number of the holes which can be compounded with electrons in the active layer is increased, the compounding efficiency of the electrons in the active layer is improved, and the light emitting efficiency of the light emitting diode is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an epitaxial wafer of another light emitting diode according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;
fig. 4 is a flowchart of another method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;
fig. 5 to 6 are flowcharts of structures of an epitaxial wafer of another light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an epitaxial wafer of a light emitting diode according to an embodiment of the present invention. As shown in fig. 1, the epitaxial wafer includes a substrate 1, and a buffer layer 2, an N-type GaN layer 3, an active layer 4, an electron blocking layer 5, a superlattice structure 6, and a P-type GaN layer 7 sequentially stacked on the substrate 1. The superlattice structure 6 includes indium nitride layers 61 and gallium nitride layers 62 alternately stacked.
A superlattice structure comprising indium nitride and gallium nitride which are alternately stacked is arranged between the electron blocking layer and the P-type GaN layer, the superlattice structure of the indium nitride and the gallium nitride can play a role in reducing dislocation and defects in the epitaxial layer, and the overall quality of the epitaxial wafer can be improved. And because the potential barrier of the indium nitride in the superlattice structure is low, a large amount of holes can be accumulated at the indium nitride in the superlattice structure before the holes move into the active layer, and the large amount of holes accumulated in the superlattice structure provide a large hole base number, so that the number of the holes which can enter the active layer at the same time is increased, the number of the holes which can be compounded with electrons in the active layer is increased, the compounding efficiency of the electrons in the active layer is improved, and the light emitting efficiency of the light emitting diode is improved.
Fig. 2 is a schematic structural diagram of another epitaxial wafer of a light emitting diode according to an embodiment of the present invention, and as shown in fig. 2, the epitaxial wafer includes a substrate 1, and a buffer layer 2, an N-type GaN layer 3, an active layer 4, an electron blocking layer 5, a superlattice structure 6, a magnesium nitride layer 8, a P-type GaN layer 7, and a P-type contact layer 9 sequentially stacked on the substrate 1.
Alternatively, the buffer layer 2 may include a low temperature GaN buffer layer 21 and an undoped GaN layer 22 stacked in this order, the low temperature GaN buffer layer 21 may have a thickness of 15 to 35nm, and the undoped GaN layer 22 may have a thickness of 0.1 to 2.0 μm. This arrangement can reduce lattice mismatch between the substrate 1 and the epitaxial layer grown on the undoped GaN layer 22, ensuring the film-forming quality of the epitaxial layer.
Alternatively, in other embodiments of the present invention, the buffer layer 2 may also include an AlN buffer layer or only a GaN buffer layer, which is not limited by the present invention.
Illustratively, the doping element in the N-type GaN layer 3 may be Si, and the doping concentration of Si may be 1018cm-3-1019cm-3. Further, the thickness of the N-type GaN layer 3 may be 1 to 5 μm.
In the embodiment, the active layer 4 may include InGaN well layers 41 and GaN barrier layers 42 alternately stacked, the thickness of the InGaN well layers 41 may be 2 to 3nm, and the thickness of the GaN barrier layers 42 may be 9 to 20 nm.
The number of layers of the InGaN well layer 41 can be 5-11, and the number of layers of the GaN barrier layer 42 is the same as that of the InGaN well layer 41.
Exemplarily, in the embodiment of the present invention, the electron blocking layer 5 may include an aluminum gallium nitride layer 51 and an indium gallium nitride layer 52 that are alternately stacked, and while the electron blocking layer 5 in this form plays a role in blocking electrons, the periodic structure may also play a role in releasing stress in the epitaxial wafer to ensure the crystal quality of the light emitting diode.
Wherein the thickness of the AlGaN layer 51 may be 20 to 60 nm. The thickness of the InGaN layer 52 may be 30-90 nm. The number of AlGaN layers 51 may be 7 to 12. This arrangement can ensure the overall quality of the epitaxial wafer while effectively blocking electrons.
Optionally, the molar content of the indium component and the aluminum component in the electron blocking layer 5 can be 0.5-1.
Alternatively, in other cases provided by the embodiment of the present invention, the electron blocking layer may also be configured as a single-layer structure of the aluminum gallium nitride layer or other structures, which is not limited by the present invention.
Illustratively, the molar content of the indium component in the indium nitride layer 61 in the superlattice structure 6 may be 0.05 to 0.1. The molar content of the indium component in the indium nitride layer is set to be in the range, so that the whole quality of the epitaxial wafer is prevented from being influenced while the large accumulation of holes in the superlattice structure is ensured, and the luminous efficiency of the light-emitting diode is favorably ensured.
The number of the indium nitride layers 61 may be 3 to 9. The number of indium nitride layers 61 set in the above range ensures that the superlattice structure 6 can effectively accumulate a large number of holes, thereby ensuring the number of holes that can enter the active layer at the same time.
Furthermore, the thickness of the indium nitride layer can be 5-20 nm, and the thickness of the gallium nitride layer can be 10-40 nm. The thickness of the indium nitride layer and the thickness of the gallium nitride layer in the superlattice structure are respectively arranged in the above range, so that the superlattice structure can be guaranteed to provide a certain space for accumulating holes while the effect of the superlattice structure on stress release in the epitaxial layer is guaranteed, and the light emitting efficiency of the light emitting diode is improved.
Optionally, the thickness of the P-type GaN layer 7 may be 100-200 nm.
As shown in fig. 2, the epitaxial wafer may include a magnesium nitride layer 8, and the magnesium nitride layer 8 may be disposed between the superlattice structure 6 and the P-type GaN layer 7. The magnesium nitride layer can increase the number of overall holes in the epitaxial layer, increase the number of holes accumulated in the superlattice structure 6, further increase the number of holes which enter the active layer and are combined with electrons, and improve the light emitting efficiency of the light emitting diode. And because the magnesium nitride layer is uniformly arranged on the superlattice structure, holes can more uniformly enter the active layer due to the increase of the magnesium nitride layer, and the light emitting uniformity of the light emitting diode is improved.
Wherein the thickness of the magnesium nitride layer is 1-10 nm. The thickness of the magnesium nitride layer is set within the range, so that the number of holes in the whole epitaxial layer can be effectively increased.
Further, the magnesium component in the magnesium nitride layer may be contained in an amount of 0.005 to 0.01 mol%. The arrangement can ensure the effective improvement of the number of holes in the whole epitaxial layer under the condition of not influencing the quality of the whole crystal of the epitaxial layer.
In the embodiment of the present invention, the P-type contact layer 9 may be provided for the subsequent fabrication of the light emitting diode, which is not limited by the present invention. And the thickness of the P-type contact layer can be 5-300 nm.
Fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention, and as shown in fig. 3, the method includes:
s11: a substrate is provided.
S12: a buffer layer is grown on a substrate.
S13: and growing an N-type GaN layer on the buffer layer.
S14: and growing an active layer on the N-type GaN layer.
S15: an electron blocking layer is grown on the active layer.
S16: a superlattice structure is grown on the electron blocking layer.
The superlattice structure comprises indium nitride layers and gallium nitride layers which are alternately stacked.
S17: and growing a P-type GaN layer on the superlattice structure.
A superlattice structure comprising indium nitride and gallium nitride which are alternately stacked is arranged between the electron blocking layer and the P-type GaN layer, the superlattice structure of the indium nitride and the gallium nitride can play a role in reducing dislocation and defects in the epitaxial layer, and the overall quality of the epitaxial wafer can be improved. And because the potential barrier of the indium nitride in the superlattice structure is low, a large amount of holes can be accumulated at the indium nitride in the superlattice structure before the holes move into the active layer, and the large amount of holes accumulated in the superlattice structure provide a large hole base number, so that the number of the holes which can enter the active layer at the same time is increased, the number of the holes which can be compounded with electrons in the active layer is increased, the compounding efficiency of the electrons in the active layer is improved, and the light emitting efficiency of the light emitting diode is improved.
The structure of the epitaxial wafer after step S17 is completed can be seen in fig. 1, and the epitaxial wafer includes a substrate 1, and a buffer layer 2, an N-type GaN layer 3, an active layer 4, an electron blocking layer 5, a superlattice structure 6, and a P-type GaN layer 7 sequentially stacked on the substrate 1. The superlattice structure 6 includes indium nitride layers 61 and gallium nitride layers 62 alternately stacked.
Fig. 4 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to another embodiment of the present invention, as shown in fig. 4, the method includes:
s21: a substrate is provided.
Among them, a sapphire substrate may be used as the substrate.
S22: a buffer layer is grown on a substrate.
The buffer layer may include a low-temperature GaN buffer layer and an undoped GaN layer, which are sequentially grown.
The growth pressure of the low-temperature GaN buffer layer can be controlled within 400-600 torr, and the growth temperature of the buffer layer can be 400-600 ℃.
Optionally, the growth thickness of the low-temperature GaN buffer layer can be 15-35 nm.
Illustratively, the growth temperature of the undoped GaN layer can be 1000-1100 ℃, and the growth pressure can be 100-300 Torr. The quality of the undoped GaN layer grown under the condition is better.
Illustratively, the thickness of the undoped GaN layer may be 1-5 μm.
S23: and growing an N-type GaN layer on the buffer layer.
The thickness of the N-type GaN layer can be 1-5 μm.
Optionally, the doping element of the N-type GaN layer is a Si element, and the doping concentration of the Si element is 2 × 1017cm-3。
The structure of the epitaxial layer after step S23 is shown in fig. 5, and a buffer layer 2, an undoped GaN layer 3, and an N-type GaN layer 4 are sequentially stacked on the substrate 1.
Wherein the growth temperature of the N-type GaN layer can be 1000-1200 deg.C, and the growth pressure can be 100-300 Torr.
S24: and growing an active layer on the N-type GaN layer.
The active layer may include InGaN well layers and GaN barrier layers alternately stacked. The growth temperature of the InGaN well layer can be 720-829 ℃, the growth pressure of the InGaN well layer can be 100-500 Torr, and the growth thickness of the InGaN well layer can be 2-3 nm; the growth temperature of the GaN barrier layer can be 850-959 ℃, the growth pressure of the GaN barrier layer can be 100-500 Torr, and the growth thickness of the GaN barrier layer can be 9-20 nm.
S25: an electron blocking layer is grown on the active layer.
The electron blocking layer may include aluminum gallium nitride layers and indium gallium nitride layers that are alternately stacked. Wherein the growth temperature of the aluminum gallium nitride layer can be 750-980 ℃, and the growth temperature of the indium gallium nitride layer can be 750-980 ℃. The electron blocking layer of the band obtained under this condition has better quality.
The electron blocking layer may include aluminum gallium nitride layers and indium gallium nitride layers that are alternately stacked. Wherein the growth pressure of the AlGaN layer can be 50 to 200Torr, and the growth pressure of the InGaN layer can be 50 to 200 Torr.
The thickness of the AlGaN layer can be 20-60 nm. The thickness of the InGaN layer may be 30-90 nm.
The number of AlGaN layers can be 7-12.
The structural diagram of the epitaxial wafer after step S25 is completed may be as shown in fig. 5, where the epitaxial wafer includes a substrate 1, and a buffer layer 2, an N-type GaN layer 3, an active layer 4, and an electron blocking layer 5 sequentially stacked on the substrate 1. The buffer layer 2 includes a low-temperature GaN buffer layer 21 and an undoped GaN layer 22 stacked in this order, and the electron blocking layer 5 includes an aluminum gallium nitride layer 51 and an indium gallium nitride layer 52 stacked alternately.
S26: a superlattice structure is grown on the electron blocking layer.
The superlattice structure comprises indium nitride layers and gallium nitride layers which are alternately stacked.
Optionally, the growth temperature of the superlattice structure is 600-1000 ℃. The superlattice structure grown at the temperature has good quality, and a certain number of holes can be effectively accumulated.
Illustratively, the growth temperature of the indium nitride layer in the superlattice structure may be 600-1000 ℃, and the growth temperature of the gallium nitride layer in the superlattice structure may be 600-1000 ℃.
Optionally, the growth pressure of the indium nitride layer and the growth pressure of the gallium nitride layer can both be 100 to 300 Torr.
Illustratively, the flow rate of indium introduced into the reaction chamber is 300-700 sccm when the superlattice structure is grown. The arrangement can ensure the quality of the superlattice structure of the finally grown band, thereby ensuring the luminous efficiency of the light-emitting diode.
The structure of the epitaxial wafer after step S26 is completed may be as shown in fig. 6, in which a superlattice structure 6 is grown on the electron blocking layer 5, and the superlattice structure 6 includes indium nitride layers 61 and gallium nitride layers 62 which are alternately stacked.
S27: and growing a magnesium nitride layer on the superlattice structure.
Wherein the growth temperature of the magnesium nitride layer can be 600-1000 ℃. The growth pressure of the magnesium nitride layer can be 100 to 300 Torr.
Illustratively, when the magnesium nitride layer grows, the flow rate of magnesium introduced into the reaction chamber is 300-700 sccm. The arrangement can ensure the quality of the magnesium nitride layer of the finally grown band, thereby ensuring the luminous efficiency of the light-emitting diode.
S28: and growing a P-type GaN layer on the magnesium nitride layer.
In the present embodiment, the growth temperature of the P-type GaN layer can be 750-1050 ℃, and the growth pressure can be 200-600 Torr.
The growth thickness of the P-type GaN layer can be 5-300 nm.
S29: and growing a P-type contact layer on the P-type GaN layer.
The thickness of the P-type contact layer is 5nm to 300nm, the growth temperature range is 850 to 1050 ℃, and the growth pressure range is 100 to 600 Torr.
A schematic structural diagram of the epitaxial wafer after step S29 is completed may be as shown in fig. 2, where the epitaxial wafer includes a substrate 1, and a buffer layer 2, an N-type GaN layer 3, an active layer 4, an electron blocking layer 5, a superlattice structure 6, a magnesium nitride layer 8, a P-type GaN layer 7, and a P-type contact layer 9 sequentially stacked on the substrate 1.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (9)

1. An epitaxial wafer of a light emitting diode is characterized by comprising a substrate, and a buffer layer, an N-type GaN layer, an active layer, an electron blocking layer, a superlattice structure, a P-type GaN layer and a P-type contact layer which are sequentially stacked on the substrate,
the superlattice structure comprises indium nitride layers and gallium nitride layers which are alternately stacked,
the epitaxial wafer further comprises a magnesium nitride layer, the magnesium nitride layer is arranged between the superlattice structure and the P-type GaN layer, and the thickness of the P-type GaN layer is 100-200 nm.
2. The epitaxial wafer of claim 1, wherein the molar content of the indium component in the indium nitride layer is 0.05 to 0.1.
3. The epitaxial wafer of claim 1 or 2, wherein the number of layers of the indium nitride layer is 3 to 9.
4. The epitaxial wafer of claim 1, wherein the indium nitride layer has a thickness of 5 to 20nm and the gallium nitride layer has a thickness of 10 to 40 nm.
5. The epitaxial wafer of claim 1, wherein the magnesium nitride layer has a thickness of 1 to 10 nm.
6. The epitaxial wafer according to claim 1, wherein the magnesium component in the magnesium nitride layer is contained in an amount of 0.005 to 0.01 mol%.
7. A preparation method of an epitaxial wafer of a light-emitting diode is characterized by comprising the following steps:
providing a substrate;
growing a buffer layer on the substrate;
growing an N-type GaN layer on the buffer layer;
growing an active layer on the N-type GaN layer;
growing an electron blocking layer on the active layer;
growing a superlattice structure on the electron blocking layer;
growing a P-type GaN layer on the superlattice structure,
the superlattice structure comprises indium nitride layers and gallium nitride layers which are stacked alternately, the epitaxial wafer further comprises a magnesium nitride layer, the magnesium nitride layer is arranged between the superlattice structure and the P-type GaN layers, the thickness of the P-type GaN layers is 100-200 nm, and the P-type contact layers are arranged on the P-type GaN layers.
8. The method of claim 7, wherein the superlattice structure is grown at a temperature of 600 ℃ to 1000 ℃.
9. The method according to claim 7, wherein indium is introduced into the reaction chamber at a flow rate of 300to 700sccm when the superlattice structure is grown on the electron blocking layer.
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