CN109343825A - A kind of johnoson counter device - Google Patents
A kind of johnoson counter device Download PDFInfo
- Publication number
- CN109343825A CN109343825A CN201810945752.3A CN201810945752A CN109343825A CN 109343825 A CN109343825 A CN 109343825A CN 201810945752 A CN201810945752 A CN 201810945752A CN 109343825 A CN109343825 A CN 109343825A
- Authority
- CN
- China
- Prior art keywords
- clock
- johnoson counter
- johnoson
- register
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention provides a kind of johnoson counter device, comprising: johnoson counter, the johnoson counter work is under the first clock, and the count value for depositing present clock period of the johnoson counter device in the first clock；And accumulator, it is connected to the johnoson counter, count value of the accumulator to the johnoson counter in the present clock period of the first clock carries out after johnoson counter code domain makees accumulation process, feed back to count value of the johnoson counter as the following clock cycle of the first clock, wherein, the bit wide of the johnoson counter and the accumulator is defined by parameter, and the bit wide of the johnoson counter is more than or equal to the bit wide of the accumulator.Johnoson counter device provided by the invention can reduce hardware resource and system delay response, while also have flexibility.
Description
Technical field
The present invention relates to electronic circuit field more particularly to a kind of johnoson counter devices.
Background technique
Existing counter is the adder based on binary field, and one of addend is fixed as 1, does cumulative realization, is led to
The implementation method being often used is ripple adder or carry lookahead adder by turn.Both adders are in logic circuit reality
There are some limitations on now, for example timing performance limits or hardware resource directly proportional with bit wide and bit wide is linear.
Hardware resource and system delay response are increased, meanwhile, counter circuit addend is fixed, and does not have flexibility.
Summary of the invention
The present invention provides a kind of johnoson counter device, can subtract to overcome the problems of the above-mentioned prior art
Few hardware resource and system delay response, while also there is flexibility.
According to an aspect of the present invention, a kind of johnoson counter device is provided, comprising:
Johnoson counter, the johnoson counter work under the first clock, and by depositing based on described Johnson
Count value of the number device device in the present clock period of the first clock；And
Accumulator is connected to the johnoson counter, and the accumulator is to the johnoson counter in the first clock
The count value of present clock period carry out after johnoson counter code domain makees accumulation process, feed back to described Johnson and count
Count value of the device as the following clock cycle of the first clock, the bit wide of the johnoson counter and the accumulator is by joining
Number definition, and the bit wide of the johnoson counter is more than or equal to the bit wide of the accumulator.
Optionally, further includes:
First register, for first registers under second clock, first register connects described John
Inferior counter, and for depositing the johnoson counter in the count value of the present clock period of second clock.
Optionally, the clock cycle of the second clock is less than or equal to the clock cycle of first clock.
Optionally, further includes:
Second register, second registers are posted in third clock, the second register connection described first
Storage, and the count value for depositing present clock period of first register in third clock.
Optionally, the second clock is multiplexed with the third clock.
Optionally, the clock cycle of the third clock is less than or equal to the clock cycle of the second clock.
Optionally, the counting that second register is used to provide the johnoson counter device to external circuit is defeated
Out.
Optionally, further includes:
N number of register, N are positive integer greater than 2, in N number of register:
First register connects the johnoson counter；
I+1 register connects i-th of register, and i is the integer for being less than or equal to N-1 more than or equal to 1；
Wherein, the clock cycle of i+1 registers is less than or equal to the clock cycle of i-th of registers.
Optionally, the johnoson counter is realized by register sequence circuit.
Optionally, the accumulator is realized by combinational logic circuit.
Johnoson counter device provided by the invention has the advantage that
Generic logic hardware, which is used only, in the present invention can be realized the accumulated counts of Johnson's code domain, do not need johnoson code and
Binary mutual conversion；Due to the particularity of Johnson's coding, the hard-wired timing limitation of johnoson counter device
(most complicated timing is a reverser and corresponding register) unrelated with digit increases slower；And binary system need not be made
With the exchange of johnoson code, reduce hardware resource and delay response；Meanwhile the accumulator bit wide of johnoson counter device can
Parameter definition increases flexibility.The two of the exportable johnoson code expression of johnoson counter device provided by the invention as a result,
System number, and be that can satisfy the needs of embedded system complicated applications in strict accordance with synchronous working clock output.
Detailed description of the invention
Its example embodiment is described in detail by referring to accompanying drawing, above and other feature of the invention and advantage will become
It is more obvious.
Fig. 1 shows the schematic diagram of johnoson counter device according to a first embodiment of the present invention.
Fig. 2 shows the schematic diagrames of johnoson counter device according to a second embodiment of the present invention.
Fig. 3 shows the schematic diagram of johnoson counter device according to a third embodiment of the present invention.
Fig. 4 shows the schematic diagram of johnoson counter device according to a fourth embodiment of the present invention.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.
In addition, attached drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale.Identical attached drawing mark in figure
Note indicates same or similar part, thus will omit repetition thereof.Some block diagrams shown in the drawings are function
Energy entity, not necessarily must be corresponding with physically or logically independent entity.These function can be realized using software form
Energy entity, or these functional entitys are realized in one or more hardware modules or integrated circuit, or at heterogeneous networks and/or place
These functional entitys are realized in reason device device and/or microcontroller device.
Johnoson counter device is by cyclic shift and negates binary tired under realization johnoson counter code domain
Add, binary add up under johnoson counter code domain first moves datacycle left/right, hereafter negates to minimum/high position.
For example, a 4 bit johnoson counter status switches are as follows: 0000,1000,1100,1110,1111,0111,0011,
0001,0000 ....
The schematic diagram of johnoson counter device according to a first embodiment of the present invention is shown referring first to Fig. 1, Fig. 1.
Johnoson counter device includes johnoson counter 110 and accumulator 120.
The work of johnoson counter 110 is at the first clock CLK1.The johnoson counter 110 is for depositing institute
Johnoson counter device is stated in the count value of the present clock period of the first clock CLK1.Specifically, Johnson's meter
Number device 110 is realized by register sequence circuit.
Accumulator 120 is connected to the johnoson counter 110.The accumulator 120 is to the johnoson counter 110
It carries out after johnoson counter code domain makees accumulation process, feeds back in the count value of the present clock period of the first clock CLK1
Count value of the johnoson counter 110 as the following clock cycle of the first clock CLK1.In each implementation of the invention
In example, the bit wide of the johnoson counter 110 and the accumulator 120 is defined by parameter, so that johnoson counter
Device is more flexible.For example, the bit wide of johnoson counter can be 64 for the case where count range is 0~127, this
Invention is not limited thereto, and the combination of the register of different bit wides also can be set into johnoson counter.Specifically, described
The bit wide of johnoson counter need to be more than or equal to the bit wide of the accumulator.Optionally, the accumulator 120 can be patrolled by combination
Circuit is collected to realize.
In a specific embodiment, such as johnoson counter 110 is posted in the first clock cycle of the first clock CLK1
It deposits state 0000, exports to accumulator 120 and carry out binary cumulative under johnoson counter code domain, obtain 1000, the
The second clock period of one clock CLK1, johnoson counter 110 deposit the output 1000 of accumulator 120, and so on.
On the one hand, the johnoson counter 110 in johnoson counter device can provide johnoson counter (such as can
To be shift register) twice of count status of digit (i.e. n bit shift register can provide 2n state, and n is positive whole
Number)；On the other hand, johnoson counter device can voluntarily be initialized since all-zero state, without existing on startup
The first meter digital of outside injection.Johnoson counter device can also generate Gray code, wherein two adjacent interblocks are only
There is a difference.
Referring to Fig. 2, Fig. 2 shows the schematic diagrames of johnoson counter device according to a second embodiment of the present invention.
In the embodiment shown in Figure 2, johnoson counter device includes johnoson counter 110, accumulator 120 and the first register
130.The connection and control of johnoson counter 110 and accumulator 120 are identical as Fig. 1.
First register 130 works at second clock CLK2, and first register 130 connects described Johnson and counts
Device 110, and the count value for depositing present clock period of the johnoson counter 110 in second clock CLK2.One
In a little embodiments, clock cycle of the clock cycle equal to the first clock CLK1 of the second clock CLK2, such first
Numerical value in the numerical value of register 130 and johnoson counter 110 is essentially identical in the case where not malfunctioning.In some implementations
In example, the clock cycle of the second clock CLK2 is less than the clock cycle of the first clock CLK1, complete can obtain
110 data of johnoson counter.The present invention is not limited thereto, in further embodiments, the second clock CLK2's
Clock cycle is greater than the clock cycle of the first clock CLK1, the first register 130 Johnson's meter that only storage unit timesharing is carved
The numerical value of number device 110.For example, in some embodiments, the clock cycle of the second clock CLK2 is first clock
Twice of the clock cycle of CLK1, first clock cycle registered state 0000 of the johnoson counter 110 in the first clock CLK1；
In the second clock period registered state 1000 of the first clock CLK1；In the third clock cycle registered state of the first clock CLK1
1100；In the 4th clock cycle registered state 1110 of the first clock CLK1, and so on.Correspondingly, the first register 130 exists
The first clock cycle (the second clock period for being equivalent to the first clock CLK1) registered state 1000 of second clock CLK2；?
Second clock period (the 4th clock cycle for being equivalent to the first clock CLK1) registered state 1110 of two clock CLK2, with such
It pushes away.Those skilled in the art can adjust the first clock CLK1 and second clock CLK2 according to actual needs.
The schematic diagram of johnoson counter device according to a third embodiment of the present invention is shown referring to Fig. 3, Fig. 3.
In the embodiment shown in fig. 3, johnoson counter device includes johnoson counter 110, accumulator 120,
One register 130 and the second register 140.The connection and control of johnoson counter 110, accumulator 120 and the first register 130
It makes identical as Fig. 2.
The work of second register 140 is in third clock CLK3.Second register 140 connects first deposit
Device 130, and for depositing first register 130 in the count value of the present clock period of third clock CLK3.Described
Two registers 140 can be used for providing the counting output of the johnoson counter device to external circuit.In some embodiments
In, the second clock CLK2 is multiplexed with the third clock CLK3.That is the first register 130 and the second register 140 share
Second clock CLK2.In view of data transmission may malfunction between the first register 130 and johnoson counter 110, error is general
Rate is m% (m is the constant greater than zero and less than 100), it is contemplated that data between the first register 130 and the second register 140
Transmission may also malfunction, and error probability is s% (s is the constant greater than zero and less than 100), as a result, from johnoson counter 110
The total error probability of data to the second register 140 is m%*s%, and total error probability is less than m%, while again smaller than s%, into one
Step reduces the probability of error, can reduce the probability of the data loading error occurring of cross clock domain by two registers as a result,.?
In other realizations of the present embodiment, clock cycle of the third clock CLK3 less than or equal to the second clock CLK2 when
The clock period is different.In such embodiments, first register 130 and the second register 140 can be respectively to different
External circuit provides the counting output of the johnoson counter device.Those skilled in the art can adjust according to actual needs
Second clock CLK2 and third clock CLK3.
In one particular embodiment of the present invention, the present invention provides johnoson counter device and can be not limited to two and post
Storage.Referring to fig. 4, Fig. 4 shows the schematic diagram of johnoson counter device according to a fourth embodiment of the present invention.Johnson's meter
Number device device includes johnoson counter 110, accumulator 120 and N number of register 150, and N is the positive integer greater than 2, is posted N number of
First register 150 in storage connects the johnoson counter 110.The i+1 register 150 in N number of register
I-th of register 150 is connected, i is the integer for being less than or equal to N-1 more than or equal to 1.The clock cycle of 150 work of i+1 register
The clock cycle of less than or equal to i-th 150 work of register.
For example, johnoson counter device may include 3 registers.First register connection in 3 registers
The johnoson counter.Second register connects first register, third register connection second in 3 registers
A register, and the clock cycle of third registers be less than or equal to second registers clock cycle be less than etc.
In the clock cycle of first registers.When there are three above register, it can connect in the same manner as described above
And work.
The quantity of register is more as a result, and the error probability of johnoson counter device provided by the invention is smaller.
It will be understood by those skilled in the art that the respective embodiments described above are to realize specific embodiments of the present invention,
And in practical applications, can to it, various changes can be made in the form and details, without departing from the spirit and scope of the present invention.
Johnoson counter device provided by the invention has the advantage that
Generic logic hardware, which is used only, in the present invention can be realized the accumulated counts of Johnson's code domain, do not need johnoson code and
Binary mutual conversion；Due to the particularity of Johnson's coding, the hard-wired timing limitation of johnoson counter device
(most complicated timing is a reverser and corresponding register) unrelated with digit increases slower；And binary system need not be made
With the exchange of johnoson code, reduce hardware resource and delay response；Meanwhile the accumulator bit wide of johnoson counter device can
Parameter definition increases flexibility.The two of the exportable johnoson code expression of johnoson counter device provided by the invention as a result,
System number, and be that can satisfy the needs of embedded system complicated applications in strict accordance with synchronous working clock output.
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the disclosure
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are by appended
Claim is pointed out.
Claims (10)
1. a kind of johnoson counter device characterized by comprising
Johnoson counter, the johnoson counter work are used to deposit the johnoson counter under the first clock
Count value of the device in the present clock period of the first clock；And
Accumulator, is connected to the johnoson counter, and the accumulator works as the johnoson counter in the first clock
The count value of preceding clock cycle carries out after johnoson counter code domain makees accumulation process, feeds back to the johnoson counter and makees
For the count value of the following clock cycle of the first clock, wherein the bit wide of the johnoson counter and the accumulator is by joining
Number definition, and the bit wide of the johnoson counter is more than or equal to the bit wide of the accumulator.
2. johnoson counter device as described in claim 1, which is characterized in that further include:
First register, for first registers under second clock, first register connects Johnson's meter
Number device, and for depositing the johnoson counter in the count value of the present clock period of second clock.
3. johnoson counter device as claimed in claim 2, which is characterized in that the clock cycle of the second clock is less than
Equal to the clock cycle of first clock.
4. johnoson counter device as claimed in claim 2, which is characterized in that further include:
Second register, second registers connect first register in third clock, second register,
And the count value for depositing present clock period of first register in third clock.
5. johnoson counter device as claimed in claim 4, which is characterized in that the second clock is multiplexed with the third
Clock.
6. johnoson counter device as claimed in claim 4, which is characterized in that the clock cycle of the third clock is less than
Equal to the clock cycle of the second clock.
7. johnoson counter device as claimed in claim 4, which is characterized in that second register is used for external electrical
Road provides the counting output of the johnoson counter device.
8. johnoson counter device as described in claim 1, which is characterized in that further include:
N number of register, N are positive integer greater than 2, in N number of register:
First register connects the johnoson counter；
I+1 register connects i-th of register, and i is the integer for being less than or equal to N-1 more than or equal to 1；
Wherein, the clock cycle of i+1 registers is less than or equal to the clock cycle of i-th of registers.
9. johnoson counter device as claimed in any one of claims 1 to 8, which is characterized in that the johnoson counter
It is realized by register sequence circuit.
10. johnoson counter device as claimed in any one of claims 1 to 8, which is characterized in that the accumulator is by combining
Logic circuit is realized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810945752.3A CN109343825B (en) | 2018-08-20 | 2018-08-20 | Johnson counter device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810945752.3A CN109343825B (en) | 2018-08-20 | 2018-08-20 | Johnson counter device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109343825A true CN109343825A (en) | 2019-02-15 |
| CN109343825B CN109343825B (en) | 2023-06-30 |
Family
ID=65291720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810945752.3A Active CN109343825B (en) | 2018-08-20 | 2018-08-20 | Johnson counter device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109343825B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5425074A (en) * | 1993-12-17 | 1995-06-13 | Intel Corporation | Fast programmable/resettable CMOS Johnson counters |
| CN1475046A (en) * | 2000-09-14 | 2004-02-11 | �����ɷ� | Double-edge M/N counter |
| CN104052487A (en) * | 2013-03-13 | 2014-09-17 | 英飞凌科技奥地利有限公司 | System and Method for an Oversampled Data Converter |
| CN106662980A (en) * | 2014-05-29 | 2017-05-10 | 桑迪士克科技有限责任公司 | System And Method For Distributed Computing In Non-Volatile Memory |
-
2018
- 2018-08-20 CN CN201810945752.3A patent/CN109343825B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5425074A (en) * | 1993-12-17 | 1995-06-13 | Intel Corporation | Fast programmable/resettable CMOS Johnson counters |
| CN1475046A (en) * | 2000-09-14 | 2004-02-11 | �����ɷ� | Double-edge M/N counter |
| CN104052487A (en) * | 2013-03-13 | 2014-09-17 | 英飞凌科技奥地利有限公司 | System and Method for an Oversampled Data Converter |
| CN106662980A (en) * | 2014-05-29 | 2017-05-10 | 桑迪士克科技有限责任公司 | System And Method For Distributed Computing In Non-Volatile Memory |
Non-Patent Citations (1)
| Title |
|---|
| 梁华国等: "一种基于折叠计数器重新播种的确定自测试方案", 《计算机研究与发展》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109343825B (en) | 2023-06-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102916687A (en) | Ternary clock generator based on CMOS (complementary metal oxide semiconductor) technology | |
| TW200915173A (en) | Data bus inversion detection mechanism | |
| CN109407550A (en) | A kind of building and its FPGA circuitry realization of conservative hyperchaotic system | |
| Najafi et al. | Power and area efficient sorting networks using unary processing | |
| CN109815619A (en) | A method of asynchronous circuit is converted by synchronous circuit | |
| CN103853524A (en) | Multiplier device and multiplying method | |
| CN109343825A (en) | A kind of johnoson counter device | |
| CN103684423A (en) | Variable synchronous clock frequency division circuit | |
| CN106374898B (en) | Multichannel exports gating switch timing and generates structure | |
| CN102916691B (en) | BCD (binary-coded decimal) decimal counter based on reversible logic | |
| CN105653238B (en) | A kind of clocking method and device | |
| Solov’ev | Implementation of finite-state machines based on programmable logic ICs with the help of the merged model of Mealy and Moore machines | |
| CN102355231A (en) | Probability-calculation-based low-power consumption digital filter and realization method | |
| RU2284655C1 (en) | Parallel counter of singular signals | |
| CN103647528B (en) | Non-overlapping clock generation circuit | |
| CN103593628B (en) | A kind of method of logic compound register system and opposing power analysis | |
| CN102955682B (en) | Modular(23n-2n)multiplier | |
| CA1291267C (en) | Counter | |
| CN103377690A (en) | Data sending and receiving device and system and method for data transmission | |
| CN100571092C (en) | Method for forming pseudo mask register in the scrambling code phase deviation | |
| Lee et al. | Decomposing Fredkin Gate into simple reversible elements with memory | |
| CN111666063A (en) | Increasing function implementation device based on random computation | |
| CN203457135U (en) | Gray code counter device | |
| CN101109801B (en) | Correlator circuit for global positioning system | |
| CN201054020Y (en) | GPS system correlator circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |