CN109326568A - A kind of Schottky diode and production method - Google Patents
A kind of Schottky diode and production method Download PDFInfo
- Publication number
- CN109326568A CN109326568A CN201811093071.5A CN201811093071A CN109326568A CN 109326568 A CN109326568 A CN 109326568A CN 201811093071 A CN201811093071 A CN 201811093071A CN 109326568 A CN109326568 A CN 109326568A
- Authority
- CN
- China
- Prior art keywords
- layer
- schottky diode
- opening
- phosphorosilicate glass
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- 239000002184 metal Substances 0.000 claims abstract description 52
- 239000011521 glass Substances 0.000 claims abstract description 38
- 239000004642 Polyimide Substances 0.000 claims abstract description 34
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 34
- 229920001721 polyimide Polymers 0.000 claims abstract description 34
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 33
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 238000001459 lithography Methods 0.000 claims description 10
- 238000003466 welding Methods 0.000 claims description 6
- 238000005036 potential barrier Methods 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 151
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 229910001415 sodium ion Inorganic materials 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention relates to semiconductor crystal wafer technical fields, in particular to a kind of Schottky diode and production method.A kind of Schottky diode, it includes PN junction, back layer, barrier layer, metal layer and oxide layer, oxide layer and back layer are separately positioned on the both ends of PN junction, oxide layer has active area window, barrier layer and metal layer are successively set on active area window, and PN junction, barrier layer and metal layer are successively connected with each other, and further include phosphorosilicate glass layer, silicon nitride layer and polyimide layer；Phosphorosilicate glass layer is arranged between metal layer and oxide layer；Silicon nitride layer and polyimide layer are successively set on side of the metal layer far from PN junction.
Description
Technical field
The present invention relates to semiconductor crystal wafer technical fields, in particular to a kind of Schottky diode and production method.
Background technique
The prior art generallys use passivation film to protect Schottky diode, and mainly includes phosphorus silicon using passivation film
Glass, silicon nitride, silicon oxynitride, polyimides (Polyimide) and glass etc..
But due to the silicon nitride of single layer, silicon oxynitride etc. there is a problem of stress it is big there are hidden with metal layer adhesive force
Suffer from, and then causes silicon nitride to fall off, reduces the reliability of semiconductor power device；And the thermal expansion coefficient of polyimides is lower,
With the unmatched problem of the coefficient of expansion of metal layer material.Therefore, the chip structure of current solution PCT appraisal problem and preparation
Method is not able to satisfy the high reliability standards of product.
Summary of the invention
The purpose of the present invention includes providing a kind of Schottky diode, and it is thin to be able to solve silica present in chip
Film cannot prevent electron accumulation, impurity pickup, moisture absorption etc. from influencing the process of PCT examination as passivation layer, effectively stop
Objectionable impurities ion or steam, sodium ion are spread to substrate surface and terminal, to improve the reliability of semiconductor power device.
Another object of the present invention includes providing the production method for making above-mentioned Schottky diode, simple and convenient, energy
Enough efficiently, above-mentioned Schottky diode is economically made.
The embodiment of the present invention is achieved through the following technical solutions:
A kind of Schottky diode comprising PN junction, back layer, barrier layer, metal layer and oxide layer, oxide layer and the back side
Layer is separately positioned on the both ends of PN junction, and oxide layer has active area window, and barrier layer and metal layer are successively set on active area window
Mouthful, and PN junction, barrier layer and metal layer are successively connected with each other, further include:
Phosphorosilicate glass layer, silicon nitride layer and polyimide layer；
Phosphorosilicate glass layer is arranged between metal layer and oxide layer；
Silicon nitride layer and polyimide layer are successively set on side of the metal layer far from PN junction.
The solution of the present invention is passivated by using the isolation to silica and to terminal MULTILAYER COMPOSITE, effectively stops to have
Evil foreign ion or steam, sodium ion are spread to substrate surface and terminal, to improve the reliability of semiconductor power device.And
Such Schottky diode, which can solve silica membrane present in chip as passivation layer, cannot prevent electron accumulation, miscellaneous
Matter pickup, moisture absorption etc. influence the process of PCT examination.
To sum up, such Schottky diode structure is simple and convenient to operate, and can significantly improve protective performance, and make
It makes conveniently, is conducive to large-scale pipeline production.
In an embodiment of the present invention:
The active area window of above-mentioned oxide layer includes First stage and second step section；
The First stage extends to the inner wall of oxide layer from the distal end of oxide layer；
Second step section extends to the bottom of active area window from the inner wall of oxide layer；
Phosphorosilicate glass layer was arranged in the First stage.
In an embodiment of the present invention:
Above-mentioned phosphorosilicate glass layer is evenly arranged on distal end and the inner wall in First stage of oxide layer；And phosphorosilicate glass layer and oxidation
The width of layer is equal.
In an embodiment of the present invention:
The side of above-mentioned silicon nitride layer is connect with metal layer, phosphorosilicate glass layer respectively；
Polyimide layer is only connect with silicon nitride layer.
In an embodiment of the present invention:
Above-mentioned silicon nitride layer has opposite L shape step and L shape opening；
L shape opening is clamped with metal layer, and L shape step is connect with polyimide layer.
In an embodiment of the present invention:
Above-mentioned polyimide layer includes L shape protrusion；
L shape protrusion is chimeric with L shape step.
In an embodiment of the present invention:
Above-mentioned polyimide layer is provided with the first opening, and silicon nitride layer is provided with the second opening；First opening is opened with second
Mouth is mutually communicated；
Second opening extends to layer on surface of metal；
Welding window is collectively formed with the second opening in first opening.
In an embodiment of the present invention:
Above-mentioned first opening is identical as the second opening inside diameter.
In an embodiment of the present invention:
The internal diameter of above-mentioned first opening is less than active area window.
A kind of production method of Schottky diode comprising following steps
Oxide layer is grown on the surface of the silicon substrate of semiconductor power device, lithography and etching is carried out to oxide layer and is formed with
Source region window is injected by particle and high temperature knot formation PN junction is doped and passed through to silicon substrate；
It in oxide layer and its deposits phosphorosilicate glass in the plane and forms phosphorosilicate glass layer, and light is carried out to phosphorosilicate glass layer
It carves and etching forms contact hole；
Barrier layer is deposited on phosphorosilicate glass layer, barrier layer inserts downwards contact hole and the active region contact with silicon substrate,
And potential barrier is formed by vacuum alloy；
The deposited metal on barrier layer, and lithography and etching is carried out to metal layer and forms metal electrode；
Sequentially deposit silicon nitride, polyimides on the metal layer, to form the passivation for including silicon nitride layer, polyimide layer
Layer；And lithography and etching is carried out to passivation layer and forms welding window.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is the structural schematic diagram of the prior art；
Fig. 2 is Schottky diode first structure diagram provided in an embodiment of the present invention；
Fig. 3 is the second structural schematic diagram of Schottky diode provided in an embodiment of the present invention；
Fig. 4 is Schottky diode third structural schematic diagram provided in an embodiment of the present invention.
Icon: 10-PN knot；11- back layer；12- barrier layer；13- metal layer；14- oxide layer；20-PN knot；The back side 21-
Layer；22- barrier layer；23- metal layer；24- oxide layer；100- active area window；The 110- First stage；120- second step
Section；200- phosphorosilicate glass layer；300- silicon nitride layer；310-L shape step；320-L shape opening；400- polyimide layer；500- weldering
Connect window.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being usually described and illustrated herein in the accompanying drawings is implemented
The component of example can be arranged and be designed with a variety of different configurations.
Therefore, the detailed description of the embodiment of the present invention provided in the accompanying drawings is not intended to limit below claimed
The scope of the present invention, but be merely representative of selected embodiment of the invention.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without creative efforts belongs to the model that the present invention protects
It encloses.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.
In the description of the present invention, it should be noted that if occur term " center ", "upper", "lower", "left", "right",
The orientation or positional relationship of the instructions such as "vertical", "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings,
Either the invention product using when the orientation or positional relationship usually put, be merely for convenience of the description present invention and simplification retouched
It states, rather than the device or element of indication or suggestion meaning must have a particular orientation, be constructed and operated in a specific orientation,
Therefore it is not considered as limiting the invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and
It cannot be understood as indicating or implying relative importance.
In addition, being not offered as requiring component abswolute level or outstanding if there are the terms such as term "horizontal", "vertical", " pendency "
It hangs down, but can be slightly tilted.It is not to indicate to be somebody's turn to do if "horizontal" only refers to that its direction is more horizontal with respect to for "vertical"
Structure is had to fully horizontally, but can be slightly tilted.
In the description of the present invention, it is also necessary to which explanation is unless specifically defined or limited otherwise, if there is term
" setting ", " installation ", " connected ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, be also possible to detachably connect
It connects, or is integrally connected；It can be mechanical connection, be also possible to be electrically connected；It can be directly connected, intermediate matchmaker can also be passed through
Jie is indirectly connected, and can be the connection inside two elements.It for the ordinary skill in the art, can be with concrete condition
Understand the concrete meaning of above-mentioned term in the present invention.
Fig. 1 is please referred to, Fig. 2 is the structural schematic diagram of the Schottky diode of the prior art.It can be seen from the figure that Xiao Te
Based diode comprising PN junction 10, back layer 11, barrier layer 12, metal layer 13 and oxide layer 14.
Oxide layer 14 and back layer 11 are separately positioned on the both ends of PN junction 10, and oxide layer 14 has active area window, potential barrier
Layer 12 and metal layer 13 are successively set on active area window, and PN junction 10, barrier layer 12 and metal layer 13 are successively connected with each other.
The prior art generallys use passivation film to protect Schottky diode, and mainly includes phosphorus silicon using passivation film
Glass, silicon nitride, silicon oxynitride, polyimides (Polyimide) and glass etc..
But due to the silicon nitride of single layer, silicon oxynitride etc. there is a problem of stress it is big there are hidden with metal layer adhesive force
Suffer from, and then causes silicon nitride to fall off, reduces the reliability of semiconductor power device；And the thermal expansion coefficient of polyimides is lower,
With the unmatched problem of the coefficient of expansion of metal layer material.Therefore, the chip structure of current solution PCT appraisal problem and preparation
Method is not able to satisfy the high reliability standards of product, and the present invention can solve this problem.
Embodiment
Fig. 1 is please referred to, Fig. 1 is a kind of structural schematic diagram of Schottky diode provided in an embodiment of the present invention.From Fig. 1
It can be seen that a kind of Schottky diode comprising PN junction 20, back layer 21, barrier layer 22, metal layer 23 and oxide layer 24, oxygen
Change layer 24 and back layer 21 is separately positioned on the both ends of PN junction 20, oxide layer 24 has active area window 100, barrier layer 22 and gold
Belong to layer 23 and be successively set on active area window 100, and PN junction 20, barrier layer 22 and metal layer 23 are successively connected with each other, and are also wrapped
Include phosphorosilicate glass layer 200, silicon nitride layer 300 and polyimide layer 400.
Phosphorosilicate glass layer 200 is arranged between metal layer 23 and oxide layer 24；
Silicon nitride layer 300 and polyimide layer 400 are successively set on side of the metal layer 23 far from PN junction 20.
The solution of the present invention is passivated by using the isolation to silica and to terminal MULTILAYER COMPOSITE, effectively stops to have
Evil foreign ion or steam, sodium ion are spread to substrate surface and terminal, to improve the reliability of semiconductor power device.And
Such Schottky diode, which can solve silica membrane present in chip as passivation layer, cannot prevent electron accumulation, miscellaneous
Matter pickup, moisture absorption etc. influence the process of PCT examination.Such Schottky diode structure is simple and convenient to operate, Neng Gouming
Protective performance is improved aobviously, and easily manufactured, be conducive to large-scale pipeline production.
Specifically, the present invention increases separation layer under metal layer 23 first, it is contemplated that exist in silica membrane solid
Electron accumulation can be generated by determining charge；Or silica membrane as separation layer when cannot be effectively prevented electron accumulation and nocuousness is miscellaneous
The pollution problem of matter ion；Therefore phosphorosilicate glass (TEOS) is deposited again on the basis of original silica by thermal oxide, increased
The protection to silica and the isolation to objectionable impurities are added.
Then the present invention includes: silicon nitride, polyimides (Polyimide) shape by deposit passivation layer on metal layer 23
At layer compound passivation, passivation layer caused by former passivation layer adhesion or the larger problem of coefficient of expansion difference is avoided by the big shadow of stress
The loud and problem that falls off；And the diffusion of objectionable impurities, steam, sodium ion to substrate is effectively blocked, improve semiconductor devices
Parametric stability and high reliability.
Further, the active area window 100 of above-mentioned oxide layer 24 includes First stage 110 and second step section 120；
The First stage 110 extends to the inner wall of oxide layer 24 from the distal end of oxide layer 24；Second step section 120 is out of oxide layer 24
Wall extends to the bottom of active area window 100；Phosphorosilicate glass layer 200 was arranged in the First stage 110.
Optionally, above-mentioned phosphorosilicate glass layer 200 is evenly arranged on distal end and the inner wall in First stage 110 of oxide layer 24；And
Phosphorosilicate glass layer 200 is equal with the width of oxide layer 24.
Further, the side of above-mentioned silicon nitride layer 300 is connect with metal layer 23, phosphorosilicate glass layer 200 respectively；Polyamides is sub-
Amine layer 400 is only connect with silicon nitride layer 300.
In an embodiment of the present invention, above-mentioned silicon nitride layer 300 has opposite L shape step 310 and L shape opening 320；L
Shape opening 320 is clamped with metal layer 23, and L shape step 310 is connect with polyimide layer 400.
Optionally, above-mentioned polyimide layer 400 includes L shape protrusion；L shape protrusion is chimeric with L shape step 310.
In the present embodiment of the invention, above-mentioned polyimide layer 400 is provided with the first opening, and silicon nitride layer 300 is arranged
There is the second opening；First opening is mutually communicated with the second opening；Second opening extends to 23 surface of metal layer；First opening and the
Welding window 500 is collectively formed in two openings.
Further, above-mentioned first opening is identical as the second opening inside diameter.
In the present embodiment, the internal diameter of above-mentioned first opening is less than active area window 100.
It is of the invention the present embodiment provides a kind of production method of Schottky diode, be used to make above-mentioned Schottky two
Pole pipe comprising following steps
Oxide layer 24 is grown on the surface of the silicon substrate of semiconductor power device, lithography and etching shape is carried out to oxide layer 24
At active area window 100, is injected by particle and high temperature knot formation PN junction 20 is doped and passed through to silicon substrate；
It in oxide layer 24 and its deposits phosphorosilicate glass in the plane and forms phosphorosilicate glass layer 200, and to phosphorosilicate glass layer
200, which carry out lithography and etching, forms contact hole；
Deposit barrier layer 22 on phosphorosilicate glass layer 200, the filling contact hole and active with silicon substrate downwards of barrier layer 22
Area's contact, and potential barrier is formed by vacuum alloy；
The deposited metal 23 on barrier layer 22, and lithography and etching is carried out to metal layer 23 and forms metal electrode；
Sequentially deposit silicon nitride, polyimides on metal layer 23 include silicon nitride layer 300, polyimide layer to be formed
400 passivation layer；And lithography and etching is carried out to passivation layer and forms welding window 500.
Mesh improves the sealing performance of chip, blocks nocuousness by the passivation layer on the separation layer and metal under metal
The diffusion of impurity, steam, sodium ion to substrate and terminal；It supplies simultaneously to more clients and carries out PCT examination, be 100% logical
It crosses, to improve the parametric stability and high reliability of semiconductor devices.
These are only the preferred embodiment of the present invention, is not intended to restrict the invention, for those skilled in the art
For member, the invention may be variously modified and varied.All within the spirits and principles of the present invention, it is made it is any modification,
Equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of Schottky diode comprising PN junction, back layer, barrier layer, metal layer and oxide layer, the oxide layer and institute
The both ends that back layer is separately positioned on the PN junction are stated, the oxide layer has active area window, the barrier layer and the gold
Belong to layer and be successively set on the active area window, and the PN junction, the barrier layer and the metal layer are successively connected with each other,
It is characterized in that, comprising:
Phosphorosilicate glass layer, silicon nitride layer and polyimide layer；
The phosphorosilicate glass layer is arranged between the metal layer and the oxide layer；
The silicon nitride layer and the polyimide layer are successively set on side of the metal layer far from PN junction.
2. Schottky diode according to claim 1, it is characterised in that:
The active area window of the oxide layer includes First stage and second step section；
The First stage extends to the inner wall of the oxide layer from the distal end of the oxide layer；
The second step section extends to the bottom of active area window from the inner wall of the oxide layer；
The phosphorosilicate glass layer was arranged in the First stage.
3. Schottky diode according to claim 2, it is characterised in that:
The phosphorosilicate glass layer is evenly arranged on distal end and the inner wall in the First stage of the oxide layer；
And the phosphorosilicate glass layer is equal with the width of the oxide layer.
4. Schottky diode according to claim 1, it is characterised in that:
The side of the silicon nitride layer is connect with the metal layer, the phosphorosilicate glass layer respectively；
The polyimide layer is only connect with the silicon nitride layer.
5. Schottky diode according to claim 4, it is characterised in that:
The silicon nitride layer has opposite L shape step and L shape opening；
The L shape opening is clamped with the metal layer, and the L shape step is connect with the polyimide layer.
6. Schottky diode according to claim 5, it is characterised in that:
The polyimide layer includes L shape protrusion；
The L shape protrusion is chimeric with the L shape step.
7. Schottky diode according to claim 1 to 6, it is characterised in that:
The polyimide layer is provided with the first opening, and the silicon nitride layer is provided with the second opening；
First opening is mutually communicated with second opening；
Second opening extends to the layer on surface of metal；
Welding window is collectively formed with second opening in first opening.
8. Schottky diode according to claim 7, it is characterised in that:
First opening is identical as second opening inside diameter.
9. Schottky diode according to claim 8, it is characterised in that:
The internal diameter of first opening is less than the active area window.
10. a kind of production method of Schottky diode, it is characterised in that:
The production method of the Schottky diode includes at least following steps:
Oxide layer is grown on the surface of the silicon substrate of semiconductor power device, lithography and etching is carried out to the oxide layer and is formed with
Source region window is injected by particle and high temperature knot formation PN junction is doped and passed through to silicon substrate；
It in the oxide layer and its deposits phosphorosilicate glass in the plane and forms phosphorosilicate glass layer, and light is carried out to phosphorosilicate glass layer
It carves and etching forms contact hole；
Deposit barrier layer on the phosphorosilicate glass layer, the barrier layer insert downwards the contact hole and with the silicon substrate
Active region contact, and potential barrier is formed by vacuum alloy；
The deposited metal on the barrier layer, and lithography and etching is carried out to the metal layer and forms metal electrode；
Sequentially deposit silicon nitride, polyimides on the metal layer, to form the passivation for including silicon nitride layer, polyimide layer
Layer；And lithography and etching is carried out to the passivation layer and forms welding window.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811093071.5A CN109326568A (en) | 2018-09-19 | 2018-09-19 | A kind of Schottky diode and production method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811093071.5A CN109326568A (en) | 2018-09-19 | 2018-09-19 | A kind of Schottky diode and production method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109326568A true CN109326568A (en) | 2019-02-12 |
Family
ID=65266374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811093071.5A Pending CN109326568A (en) | 2018-09-19 | 2018-09-19 | A kind of Schottky diode and production method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109326568A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109920764A (en) * | 2019-03-14 | 2019-06-21 | 福建安特微电子有限公司 | Multi-layer film structure, application and the technique of semiconductor chip surface passivation protection |
| CN113871467A (en) * | 2021-09-28 | 2021-12-31 | 吉林华微电子股份有限公司 | Schottky diode and manufacturing method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105244382A (en) * | 2015-07-02 | 2016-01-13 | 天津天物金佰微电子有限公司 | Variode core and preparation method thereof |
| CN106298973A (en) * | 2015-05-18 | 2017-01-04 | 北京大学 | The manufacture method of a kind of Schottky diode and Schottky diode |
| CN205984943U (en) * | 2016-08-23 | 2017-02-22 | 全球能源互联网研究院 | High pressure semiconductor power device |
| CN206340552U (en) * | 2016-12-20 | 2017-07-18 | 上海芯石微电子有限公司 | A kind of low-temperature-rise high-air-tightness Schottky diode |
| CN107104045A (en) * | 2016-02-23 | 2017-08-29 | 北京大学 | The preparation method of pressure-resistant gallium nitride Schottky diode |
| CN107768260A (en) * | 2016-08-22 | 2018-03-06 | 全球能源互联网研究院 | A kind of plane terminal passivating method and semiconductor power device |
| CN108063090A (en) * | 2017-12-14 | 2018-05-22 | 北京世纪金光半导体有限公司 | A kind of low barrier Schottky diode and preparation method thereof |
-
2018
- 2018-09-19 CN CN201811093071.5A patent/CN109326568A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298973A (en) * | 2015-05-18 | 2017-01-04 | 北京大学 | The manufacture method of a kind of Schottky diode and Schottky diode |
| CN105244382A (en) * | 2015-07-02 | 2016-01-13 | 天津天物金佰微电子有限公司 | Variode core and preparation method thereof |
| CN107104045A (en) * | 2016-02-23 | 2017-08-29 | 北京大学 | The preparation method of pressure-resistant gallium nitride Schottky diode |
| CN107768260A (en) * | 2016-08-22 | 2018-03-06 | 全球能源互联网研究院 | A kind of plane terminal passivating method and semiconductor power device |
| CN205984943U (en) * | 2016-08-23 | 2017-02-22 | 全球能源互联网研究院 | High pressure semiconductor power device |
| CN206340552U (en) * | 2016-12-20 | 2017-07-18 | 上海芯石微电子有限公司 | A kind of low-temperature-rise high-air-tightness Schottky diode |
| CN108063090A (en) * | 2017-12-14 | 2018-05-22 | 北京世纪金光半导体有限公司 | A kind of low barrier Schottky diode and preparation method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109920764A (en) * | 2019-03-14 | 2019-06-21 | 福建安特微电子有限公司 | Multi-layer film structure, application and the technique of semiconductor chip surface passivation protection |
| CN113871467A (en) * | 2021-09-28 | 2021-12-31 | 吉林华微电子股份有限公司 | Schottky diode and manufacturing method thereof |
| CN113871467B (en) * | 2021-09-28 | 2023-08-04 | 吉林华微电子股份有限公司 | Schottky diode and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105091730B (en) | A kind of DSOI strain gauge and preparation method thereof | |
| CN109326568A (en) | A kind of Schottky diode and production method | |
| CN110047944A (en) | A kind of the TMBS device architecture and manufacturing method of low cost | |
| CN108529553A (en) | A kind of graphene high-temp pressure sensor packaging method | |
| CN106024623B (en) | A kind of gallium nitride Schottky diode and preparation method thereof | |
| JPS5984467A (en) | Monolithic infrared ray charge transfer element | |
| JPS58115859A (en) | Manufacture of semiconductor device | |
| JPS60138434A (en) | Manufacture of semiconductor electrostatic capacity type pressure sensor | |
| CN209087910U (en) | A kind of hall device of integrated amplifier part | |
| CN111627980A (en) | Preparation method of anti-irradiation bipolar device | |
| CN203643063U (en) | SOI pressure strain meter | |
| KR101299079B1 (en) | V-type trench nanowire sensor | |
| CN109192727A (en) | Transient voltage suppressor and preparation method thereof | |
| JP2021100012A (en) | Epitaxial silicon wafer, manufacturing method thereof, and x-ray detection sensor | |
| JPH0314228B2 (en) | ||
| JP2001077024A (en) | Semiconductor substrate and manufacture thereof | |
| KR100235994B1 (en) | A light emiting diode and a method of fabricating the same | |
| CN109119415A (en) | The monolithic die including active electrical component and passive electrical components with chip edge rock-steady structure | |
| CN216849916U (en) | Device for optimizing contact hole | |
| CN218941675U (en) | Three-dimensional silicon magneto-dependent triode with planarized electrode structure | |
| JP2007292658A (en) | Pressure sensor and manufacturing method of same | |
| JP2003332616A (en) | Compound semiconductor element and its manufacturing method | |
| WO2024094195A1 (en) | Semiconductor structure preparation method, semiconductor structure, and electronic device | |
| CN214625049U (en) | All-dielectric isolation silicon magnetic sensitive triode | |
| JPH07170000A (en) | Semiconductor device and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190212 |
|
| RJ01 | Rejection of invention patent application after publication |