JPS60138434A - Manufacture of semiconductor electrostatic capacity type pressure sensor - Google Patents
Manufacture of semiconductor electrostatic capacity type pressure sensorInfo
- Publication number
- JPS60138434A JPS60138434A JP24478383A JP24478383A JPS60138434A JP S60138434 A JPS60138434 A JP S60138434A JP 24478383 A JP24478383 A JP 24478383A JP 24478383 A JP24478383 A JP 24478383A JP S60138434 A JPS60138434 A JP S60138434A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- low resistance
- forming
- insulating layer
- diaphragm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
- G01L9/0041—Transmitting or indicating the displacement of flexible diaphragms
- G01L9/0072—Transmitting or indicating the displacement of flexible diaphragms using variations in capacitance
- G01L9/0073—Transmitting or indicating the displacement of flexible diaphragms using variations in capacitance using a semiconductive diaphragm
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measuring Fluid Pressure (AREA)
- Pressure Sensors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
この発明は、測定すべき圧力変化を静電容量的に検出す
る半導体センサの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor sensor that capacitively detects a pressure change to be measured.
第１図はかかるセンサの従来例を示す断面図、第２図は
ダイアフラム部の形成方法を説明するための説明図であ
る。第１図において、１は金属層、２．９は絶縁層、３
は開口、４は金属電極リード、５はＳｉエピタキシャル
層、６は低抵抗埋込み層、７はＰ 層、８はＳｉ単結晶
基板、１０社表面安定化層、１１はダイアプラム部、１
２は空洞である。FIG. 1 is a sectional view showing a conventional example of such a sensor, and FIG. 2 is an explanatory view for explaining a method of forming a diaphragm portion. In FIG. 1, 1 is a metal layer, 2.9 is an insulating layer, and 3
4 is an opening, 4 is a metal electrode lead, 5 is a Si epitaxial layer, 6 is a low resistance buried layer, 7 is a P layer, 8 is a Si single crystal substrate, 10 is a surface stabilization layer, 11 is a diaphragm part, 1
2 is hollow.
Ｓ１単結晶基板８は主表面が（１００）面であり、これ
にＰ 拡散層（１０ｍｌ当たりの濃度が１０Ｍ′程度）
７が形成され曵いて、ダイアフラム部１１および空洞１
２を形成する際のストップ層となる。基板８の一方の面
には窒化シリコン（ＳｉａＮ４）等の絶線層９が形、成
され、この絶縁層９と基板８の薄肉部との表面には、ガ
ラス等の表面安定化層１０が形成される。基板８の他面
にはエピタキシャル層５が形成され、その一部はくりぬ
かれて空洞になっており、さらに他の部分には、Ｐｌ−
拡散層７と金属電極部４との接触を図るための低抵抗埋
込み層６が形成されている。また、Ｓｉエピタキシャル
層５の上には、絶縁層９と同様にＳｉ３Ｎ４等よりなる
絶縁層２が形成され、さらにその上には金属層１が形成
される。こ５して、金属層１とダイアフラム部１１との
間にキャパシタンスが形成すれ、測定圧力にてダイアプ
ラム部１１が変位すると、これに応じ又キャパシタンス
が変化するので、圧力を容量の変化として測定すること
ができる。The main surface of the S1 single crystal substrate 8 is a (100) plane, and a P diffusion layer (concentration of about 10M' per 10ml) is formed on this.
7 is formed and drawn, the diaphragm part 11 and the cavity 1
It becomes a stop layer when forming 2. An insulating layer 9 made of silicon nitride (SiaN4) or the like is formed on one surface of the substrate 8, and a surface stabilizing layer 10 made of glass or the like is formed on the surface between this insulating layer 9 and the thin part of the substrate 8. It is formed. An epitaxial layer 5 is formed on the other surface of the substrate 8, a part of which is hollowed out, and a Pl-
A low resistance buried layer 6 is formed to establish contact between the diffusion layer 7 and the metal electrode portion 4. Further, on the Si epitaxial layer 5, an insulating layer 2 made of Si3N4 or the like is formed similarly to the insulating layer 9, and a metal layer 1 is further formed thereon. As a result, capacitance is formed between the metal layer 1 and the diaphragm part 11, and when the diaphragm part 11 is displaced by the measurement pressure, the capacitance changes accordingly, so the pressure is measured as a change in capacitance. be able to.
こ〜で、金属層１と絶縁層２とを貫通する開口６は、ア
ルカリ系の異方性エツチングによって空洞１２を形成す
るときに、エツチング液を供給するためのものとして形
成される。つまり、開口６を通してＳｉエピタキシャル
層５の異方性エツチング（ＫＯＩＩ系やエチレンジアミ
ン・ピロカテコール系等が使用ぎれる。）を行なうと、
先ず開口６付近からエツチングが始まり、徐々にエツチ
ングが進む。そして、第２図に示されるよプに、幾何学
的形状によって決まる（１１１）面が表われると、そこ
でエツチングは殆んど進行しなくなる。Here, the opening 6 penetrating the metal layer 1 and the insulating layer 2 is formed to supply an etching solution when the cavity 12 is formed by alkaline anisotropic etching. In other words, if anisotropic etching (KOII-based, ethylenediamine-pyrocatechol-based, etc.) is performed on the Si epitaxial layer 5 through the opening 6,
First, etching begins near the opening 6 and gradually progresses. When a (111) plane determined by the geometric shape appears as shown in FIG. 2, etching hardly progresses there.
これは、異方性エツチング液が（１１１）面を侵し難い
からであり、したがって、エピタキシャル層５に現われ
る、エツチングされた面は（１１１）面と等価な面とな
る。このように、第２図にオｄける横方向のエツチング
は（１１１）面によって抑制されるのに対し、縦方向は
横方向のエツチングが抑制された後も進行するが、最後
的にはＰ＋層７によって抑制される。Ｓｉ単結晶基板８
のエツチングもこれと同様にして行なわれ、その結果、
Ｓｉ単結晶基板８に表われる面は（１１１）面と等価で
あり、これによってエツチングの進行が制限される。な
お、ダイアフラム部１１の形状は、開口５と絶縁層９の
開口との形状によって決まる。This is because the anisotropic etching solution hardly attacks the (111) plane, and therefore the etched plane appearing in the epitaxial layer 5 is a plane equivalent to the (111) plane. In this way, while the horizontal etching shown in FIG. 2 is suppressed by the (111) plane, the vertical etching continues even after the horizontal etching has been suppressed, but eventually P+ suppressed by layer 7. Si single crystal substrate 8
Etching is done in the same way, and as a result,
The plane appearing on the Si single crystal substrate 8 is equivalent to the (111) plane, which limits the progress of etching. Note that the shape of the diaphragm portion 11 is determined by the shapes of the opening 5 and the opening of the insulating layer 9.
しかしながら、かかる構造のセンナには、次のような欠
点がある。すなわち、上述の如く、異方性化学エツチン
グ液を用いて空洞１２を形成する際、発泡を伴う反応が
生じて金属層１および絶縁層２の一方または双方が破壊
されたり、製造過程の取り扱い中に破壊されるため、歩
留まりが悪くなるという点である。その原因は、金属層
１および絶縁層２の厚さが１〜２μｍ程度に非常に薄い
ためである。このよ５な欠点を除去すべく絶縁層２を厚
くすると、測定容量に対する直列誤差分が増加するため
、測定誤差が犠牲となる一方、金属層１を厚（すれば、
金属層１．絶縁層２およびＳｉエピタキシャル層５間の
熱膨張係数の差のために、温度変化によって絶縁層２に
割れが生じたり、各層間の熱応力によってダイアフラム
部の圧力−変位特性が大きく変化するという問題が生じ
る。However, the senna having such a structure has the following drawbacks. That is, as described above, when forming the cavity 12 using an anisotropic chemical etching solution, a reaction accompanied by foaming may occur and one or both of the metal layer 1 and the insulating layer 2 may be destroyed, or during handling during the manufacturing process. The problem is that the yield rate deteriorates because the parts are destroyed. The reason for this is that the metal layer 1 and the insulating layer 2 have very thin thicknesses of about 1 to 2 μm. If the insulating layer 2 is made thicker in order to eliminate these five defects, the series error with respect to the measurement capacitance will increase, so the measurement error will be sacrificed.
Metal layer 1. Due to the difference in thermal expansion coefficient between the insulating layer 2 and the Si epitaxial layer 5, cracks may occur in the insulating layer 2 due to temperature changes, and the pressure-displacement characteristics of the diaphragm portion may change significantly due to thermal stress between each layer. occurs.
この発明はこのような事情のもとになされたもので、歩
留まりが良好で、かつ温度特性の優れた半導体形静電容
量式圧力センサの製造方法を提供することを目的とする
。The present invention was made under these circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor capacitive pressure sensor that has a good yield and excellent temperature characteristics.
その要点は、ダイアフラム部とともにキャパシタンスを
形成する電極部をＰ 低抵抗Ｓｉ層により形成すること
により、熱膨張係数の差による温度特性を改善するとと
もに、空洞形成時のアルカリ系異方性化学エツチングに
伴う発泡作用や製造過程の取り扱いによる電極部の破壊
を防いで歩留まりの向上を図るようにしたものである。The key point is that by forming the electrode part that forms capacitance together with the diaphragm part from a P low-resistance Si layer, the temperature characteristics due to the difference in thermal expansion coefficients are improved, and the alkaline anisotropic chemical etching during cavity formation is improved. This is intended to improve yield by preventing destruction of the electrode portion due to accompanying foaming action and handling during the manufacturing process.
第３図はこの発明の詳細な説明するためのセンサ断面図
である。同図において、１３はＰ 低抵抗Ｓｉ電極層、
１４は電極層、１５はＳｉ電極リードであり、その他は
第１図と同様である。FIG. 3 is a sectional view of a sensor for explaining the present invention in detail. In the same figure, 13 is a P low resistance Si electrode layer;
14 is an electrode layer, 15 is a Si electrode lead, and the other parts are the same as in FIG.
以下、同図を参照してこの発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to the same figure.
表面の結晶学的方向が（１００）面であるＮまたは１厘
の８１単結晶基板８に、良く知られ又いるイオン打ち込
み法や熱拡散法等によってＰ 層（１０２°Ｃｍ−”程
度）７をダイアフラムの厚さにした後、ＣＶＤ（Ｃｈｅ
ｍｉｃａｌ Ｖａｐｏｒ ＤｅｐｏｓＨ４ｏｎ ；化学
反応を利用した薄膜の形成方法）法等によってエピタキ
シャル層５をキャパシタンスの空隙に相肖スる厚さまで
成長させる。なお、この層は、低抵抗とはせずにアルカ
リ系異方性化学エツチングを受け易くしてお（ものとす
る。次に、Ｐ＋層７と導通を図るべく、低抵抗埋込み層
６を作る。こうして作られた集積体を挾むように、Ｓ
ｈＮ４． Ｓｉ ０２（酸化シリコン）等の絶縁層２，
９を０．５〜１μｍ程度形成する。Ｓｉ電極リード１５
を作るために絶縁層に所定の開口を形成した後、Ｐ＋低
抵抗Ｓｉ層（１０”ｃｍ−３８度）１３を数十μｍ形成
し、低抵抗Ｓｉ電極層１６と絶縁層２を貫通するよ５に
開口６をあける。この場合、Ｐ＋低抵抗Ｍ１６を数十μ
ｍの厚さにし得るのは、熱膨張係数が互いに殆んど同じ
だからである。なお、低抵抗Ｓｉ電極層１３の開口には
、ＨＦ−Ｈ，ＮＯａ系のエツチング液が用いられる。ま
た、このとき、ダイアフラム部を形成するために、絶縁
Ｎ９を残すように、エツチングが行なわれる。しかる後
、これをＫ ＯＨ系ヤエチレンジアミンとピ四カテコー
ル系の異方性エツチング液に浸すと、抵抗の高いＳｉ層
（ここでは、エピタキシャル層５と単結晶基板８）のみ
がエツチング除去される。つまり、この異方性エツチン
グ液は、Ｐ 層を殆んどエツチングしない性質があるた
め、充分な時間が経過すれば、第３図の如く、を層を残
してダイアフラムが形成される。その後、金線やアルミ
ニウム線をボンディングするための金属層１および１４
をスパッタリング等によって形成する一方、ダイアプラ
ム部１１には表面安定化層１０を形成して、一連の工程
を終了する。A P layer (approximately 102°Cm-'') 7 is formed on a N or 100cm 81 single crystal substrate 8 whose surface crystallographic direction is the (100) plane by well-known ion implantation, thermal diffusion, etc. After making the thickness of the diaphragm, CVD (Che
The epitaxial layer 5 is grown to a thickness compatible with the capacitance gap by a method such as a method of forming a thin film using a chemical reaction. Note that this layer is not made to have low resistance, but is made to be easily susceptible to alkaline anisotropic chemical etching.Next, a low resistance buried layer 6 is formed in order to establish electrical conduction with the P+ layer 7. .S sandwiching the aggregate made in this way.
hN4. Insulating layer 2 such as Si02 (silicon oxide),
9 with a thickness of about 0.5 to 1 μm. Si electrode lead 15
After forming a predetermined opening in the insulating layer in order to make a Open an opening 6 in 5. In this case, connect P + low resistance M16 to several tens of microns.
The reason why the thickness can be set to m is because the coefficients of thermal expansion are almost the same. Note that an HF-H, NOa-based etching solution is used for the opening of the low-resistance Si electrode layer 13. Further, at this time, etching is performed so as to leave the insulation N9 in order to form a diaphragm portion. Thereafter, when this is immersed in an anisotropic etching solution of KOH-based yaethylenediamine and pi-tetracatechol-based etching solution, only the high-resistance Si layer (in this case, epitaxial layer 5 and single crystal substrate 8) is etched away. In other words, since this anisotropic etching liquid has the property of hardly etching the P layer, if a sufficient amount of time passes, a diaphragm is formed leaving the P layer as shown in FIG. After that, metal layers 1 and 14 for bonding gold wires and aluminum wires.
is formed by sputtering or the like, and a surface stabilizing layer 10 is formed on the diaphragm portion 11 to complete the series of steps.
第４図はこの発明の他の実施例を説明するためのセンサ
断面図である。これは、第６図における金属層１と１４
のストレイ容量の特性改善を図るべく、上述の如き低抵
抗埋込み層を省略し、電極部４をＰ 層７に直接形成す
るようにしたもので、その他は第６図と同様である。FIG. 4 is a sectional view of a sensor for explaining another embodiment of the invention. This corresponds to metal layers 1 and 14 in FIG.
In order to improve the characteristics of stray capacitance, the low-resistance buried layer as described above is omitted, and the electrode portion 4 is formed directly on the P layer 7, but the other features are the same as in FIG.
第５図はこの発明のさらに別の実施例を説明するための
センサ断面図である。FIG. 5 is a sectional view of a sensor for explaining still another embodiment of the present invention.
すなわち、以上の実施例では、Ｐ＋層をイオン打ち込み
や熱拡散等の方法により形成するよ５にしたが、この実
施例は該Ｐ 層７をＳｉ単結晶基板８の全面にわたりＣ
ＶＤ法等によりエピタキシャル成長させた場合であり、
こうすることにより、ダイアフラムの厚さケ従来よりも
一層正確に制御することができるようにしたものである
。なお、その他の点は、第６，４図と同様である。That is, in the above embodiment, the P+ layer 7 was formed by a method such as ion implantation or thermal diffusion 5, but in this embodiment, the P+ layer 7 was formed by C over the entire surface of the Si single crystal substrate 8.
This is a case of epitaxial growth using VD method etc.
By doing this, the thickness of the diaphragm can be controlled more accurately than in the past. Note that other points are the same as in FIGS. 6 and 4.
以上の実施例では、電極間ギャップ（空洞１２）の形成
とダイアフラム部１１の形成とをアルカリ系異方性化学
エツチングにて同時に行なうよ５にしているが、Ｓｉ単
結晶基板８にＰ 層７を拡散またはエピタキシャル法に
よって形成し、他の異方性または等方性化学エツチング
にて所望形状のダイアフラム部を形成し、その後に、Ｓ
ｉエピタキシャル層５、絶縁層２の成長等を上述の如く
進めるよ５にし又も良いものである。なお、この場合、
Ｓｉ単結晶基板８上の絶縁層９と安定化膜１０は無くて
も差しつかえない。In the above embodiment, the formation of the interelectrode gap (cavity 12) and the formation of the diaphragm portion 11 are performed simultaneously by alkaline anisotropic chemical etching. is formed by a diffusion or epitaxial method, a diaphragm portion having a desired shape is formed by other anisotropic or isotropic chemical etching, and then S
It is also preferable to proceed with the growth of the epitaxial layer 5, the insulating layer 2, etc. as described above. In this case,
The insulating layer 9 and stabilizing film 10 on the Si single crystal substrate 8 may be omitted.
この発明によれば、金属電極層のかわりにＳｌのＰ＋低
抵抗層を所定厚さく数十μｍ）に形成するようにした瓦
め、従来のものに比べて電極部の強度が上がり、その結
果、前述の如き発泡現象に伴う破壊が防止され、歩留ま
りが向上するばかりでなく、その取り扱いが容易に１よ
るという効果がもたらされるものである。また、電極部
にＳｉの低抵抗層を用いているので、金属電極と比べて
熱膨張差によって生じる温度特性の劣化が防止される利
点を有するものである。According to this invention, a tile structure in which a P+ low resistance layer of Sl is formed to a predetermined thickness (several tens of μm) instead of a metal electrode layer, the strength of the electrode part is increased compared to the conventional one, and as a result, This not only prevents the destruction caused by the foaming phenomenon described above and improves the yield, but also makes it easier to handle. Furthermore, since a low resistance layer of Si is used for the electrode portion, it has the advantage that deterioration of temperature characteristics caused by differences in thermal expansion is prevented compared to metal electrodes.
第１図は半導体形静電容量式圧力センザの従来例を示す
構成図、第２図はダイアフラム部の形成方法を説明する
ための説明図、第６図はこの発明の詳細な説明するため
のセンサ断面図、第４図はこの発明の他の実施例を説明
するためのセンサ断面図、第５図はこの発明のさらに他
の実施例を説明するためのセンサ断面図である。
符号説明
１．１４・・・・・・金属層、２，９・・・・・・絶縁
層、６・・・・・・開口、４・・・・・・金属電極リー
ド、５・・・・・・Ｓｉエピタキシャル層、６・・・・
・・低抵抗埋込層、７・・・・・・Ｐ＋層、８・・・・
・・Ｓｉ単結晶基板、１０・・・・・・表面安定化膜、
１１・・・・・・タ゛イアフラム部、１２・・・・・・
空洞、１３・・・・・・Ｓｉ低抵抗電極層、１５・・・
・・・Ｓｉ電極リード代理人 弁理士 並 木 昭 夫
代理人 弁理士 松 崎 溝
築１図
第 ２ 図FIG. 1 is a configuration diagram showing a conventional example of a semiconductor capacitive pressure sensor, FIG. 2 is an explanatory diagram for explaining a method of forming a diaphragm part, and FIG. 6 is a diagram for explaining a detailed explanation of the present invention. FIG. 4 is a sectional view of the sensor for explaining another embodiment of the present invention, and FIG. 5 is a sectional view of the sensor for explaining still another embodiment of the present invention. Description of symbols 1.14...Metal layer, 2,9...Insulating layer, 6...Opening, 4...Metal electrode lead, 5... ...Si epitaxial layer, 6...
...Low resistance buried layer, 7...P+ layer, 8...
...Si single crystal substrate, 10...surface stabilization film,
11...Tire diaphragm section, 12...
Cavity, 13... Si low resistance electrode layer, 15...
...Si electrode lead representative Patent attorney Akio Namiki Patent attorney Mitsuzuki Matsuzaki Figure 1 Figure 2
Claims (1)
厚さの８１工ピタキシヤル層を形成し、該エピタキシャ
ル層の一部に前記Ｐ＋拡散層とつながる低抵抗埋込み層
を形成する一方、該エピタキシャル層上およびこれと反
対側のＳｉ基板面上にそれぞれ絶縁層を形成するととも
に、該エピタキシャル層上に形成された絶縁層上にはＰ
＋低抵抗Ｓｉ層および金属層を順次形成した後、該金属
／ｉｔ、Ｐ＋低抵抗Ｓｉ層および絶縁層を貫通する開口
とこれと対応するＳｉ基板の反対側に形成された絶縁層
の開口とを形成し、しかる後これらの開口を通してエツ
チングを行な５ことによりダイアプラム部を形成し、該
ダイアプラム部と前記Ｐ＋低抵抗Ｓｉ層との間に測定用
キャパシタンスを形成する半導体形静電容量式圧センサ
の製造方法。 ２、特許請求の範囲第１項に記載の方法におい又、前記
Ｐ＋拡散層をＰ＋エピタキシャル層とする半導体形静電
容量式圧力センサの製造方法。[Claims] 1) A P+ diffusion layer is formed on a St single crystal substrate, an 81-layer epitaxial layer is formed with a predetermined thickness, and a low resistance embedding is provided in a part of the epitaxial layer to connect to the P+ diffusion layer. While forming a layer, an insulating layer is formed on the epitaxial layer and on the opposite side of the Si substrate, and a P layer is formed on the insulating layer formed on the epitaxial layer.
+ After sequentially forming the low resistance Si layer and the metal layer, an opening penetrating the metal/it, P + the low resistance Si layer and the insulating layer, and a corresponding opening in the insulating layer formed on the opposite side of the Si substrate. and then etching through these openings 5 to form a diaphragm section, and form a semiconductor capacitive capacitance for forming a measurement capacitance between the diaphragm section and the P+ low resistance Si layer. How to manufacture the sensor. 2. A method for manufacturing a semiconductor capacitive pressure sensor according to claim 1, wherein the P+ diffusion layer is a P+ epitaxial layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24478383A JPS60138434A (en) | 1983-12-27 | 1983-12-27 | Manufacture of semiconductor electrostatic capacity type pressure sensor |
| DE19843445774 DE3445774A1 (en) | 1983-12-27 | 1984-12-12 | Method for fabricating a capacitive semiconductor pressure pick-up |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24478383A JPS60138434A (en) | 1983-12-27 | 1983-12-27 | Manufacture of semiconductor electrostatic capacity type pressure sensor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60138434A true JPS60138434A (en) | 1985-07-23 |
| JPH0380254B2 JPH0380254B2 (en) | 1991-12-24 |
Family
ID=17123853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24478383A Granted JPS60138434A (en) | 1983-12-27 | 1983-12-27 | Manufacture of semiconductor electrostatic capacity type pressure sensor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS60138434A (en) |
| DE (1) | DE3445774A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6263828A (en) * | 1985-09-06 | 1987-03-20 | Yokogawa Electric Corp | Vibration type transducer and its manufacture |
| JPS6430423U (en) * | 1987-08-17 | 1989-02-23 | ||
| US6941812B2 (en) | 2002-08-20 | 2005-09-13 | Nagano Keiki Co., Ltd. | Converter and method of manufacturing the same |
| WO2009001488A1 (en) * | 2007-06-22 | 2008-12-31 | Panasonic Corporation | Diaphragm structure and acoustic sensor |
| US8166827B2 (en) | 2008-09-10 | 2012-05-01 | Panasonic Corporation | MEMS device and method for manufacturing the same |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4872945A (en) * | 1986-06-25 | 1989-10-10 | Motorola Inc. | Post seal etching of transducer diaphragm |
| JPH0750789B2 (en) * | 1986-07-18 | 1995-05-31 | 日産自動車株式会社 | Method for manufacturing semiconductor pressure converter |
| DE4106933B4 (en) * | 1991-03-05 | 2004-12-16 | Robert Bosch Gmbh | patterning methods |
| DE59508560D1 (en) * | 1994-11-24 | 2000-08-17 | Siemens Ag | Capacitive pressure sensor |
| DE4441903C1 (en) * | 1994-11-24 | 1996-03-21 | Siemens Ag | Micromechanical capacitive pressure sensor |
| EP0758080B1 (en) * | 1995-08-09 | 1998-09-30 | Siemens Aktiengesellschaft | Micromechanical device with stress-free perforated diaphragm |
| US5888845A (en) * | 1996-05-02 | 1999-03-30 | National Semiconductor Corporation | Method of making high sensitivity micro-machined pressure sensors and acoustic transducers |
| EP0979992B1 (en) * | 1998-08-11 | 2003-10-08 | Infineon Technologies AG | Method of Manufacturing a Micromechanical Sensor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5516228A (en) * | 1978-07-21 | 1980-02-04 | Hitachi Ltd | Capacity type sensor |
| JPS5764978A (en) * | 1980-10-03 | 1982-04-20 | Ibm | Capacitive pressure transducer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2856708A1 (en) * | 1978-12-29 | 1980-07-10 | Siemens Ag | Pressure measurement transducer - has membrane carrying strain gauges used as parallel resistive paths with curved connecting end sections |
| US4261086A (en) * | 1979-09-04 | 1981-04-14 | Ford Motor Company | Method for manufacturing variable capacitance pressure transducers |
| DE2940955A1 (en) * | 1979-10-09 | 1981-04-23 | Gosudarstvennyj naučno-issledovatel'skij institut teploenergetičeskogo priborostroenija, Moskva | Semiconductor strain gauge with epitaxial p-silicon resistor - on sapphire monocrystal gives signal independent of ambient temp. |
-
1983
- 1983-12-27 JP JP24478383A patent/JPS60138434A/en active Granted
-
1984
- 1984-12-12 DE DE19843445774 patent/DE3445774A1/en not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5516228A (en) * | 1978-07-21 | 1980-02-04 | Hitachi Ltd | Capacity type sensor |
| JPS5764978A (en) * | 1980-10-03 | 1982-04-20 | Ibm | Capacitive pressure transducer |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6263828A (en) * | 1985-09-06 | 1987-03-20 | Yokogawa Electric Corp | Vibration type transducer and its manufacture |
| JPH0518050B2 (en) * | 1985-09-06 | 1993-03-10 | Yokogawa Electric Corp | |
| JPS6430423U (en) * | 1987-08-17 | 1989-02-23 | ||
| US6941812B2 (en) | 2002-08-20 | 2005-09-13 | Nagano Keiki Co., Ltd. | Converter and method of manufacturing the same |
| WO2009001488A1 (en) * | 2007-06-22 | 2008-12-31 | Panasonic Corporation | Diaphragm structure and acoustic sensor |
| JP2009033698A (en) * | 2007-06-22 | 2009-02-12 | Panasonic Corp | Diaphragm structure and acoustic sensor |
| US8146437B2 (en) | 2007-06-22 | 2012-04-03 | Panasonic Corporation | Diaphragm structure and MEMS device |
| US8166827B2 (en) | 2008-09-10 | 2012-05-01 | Panasonic Corporation | MEMS device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3445774A1 (en) | 1985-07-04 |
| JPH0380254B2 (en) | 1991-12-24 |
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