CN109216450B - Manufacturing method of trench type power semiconductor element - Google Patents

Manufacturing method of trench type power semiconductor element Download PDF

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CN109216450B
CN109216450B CN201710523935.1A CN201710523935A CN109216450B CN 109216450 B CN109216450 B CN 109216450B CN 201710523935 A CN201710523935 A CN 201710523935A CN 109216450 B CN109216450 B CN 109216450B
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layer
trench
forming
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power semiconductor
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CN109216450A (en
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许修文
叶俊莹
倪君伟
李元铭
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Super Group Semiconductor Co Ltd
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Super Group Semiconductor Co Ltd
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Abstract

A method for manufacturing a trench power semiconductor element is provided to form a trench power semiconductor element having a shielding electrode and a gate electrode in a trench. The manufacturing method of the groove type power semiconductor element at least comprises the step of forming a groove gate structure in a groove of the epitaxial layer. The trench gate structure has a shield electrode, a gate electrode over the shield electrode, and an inter-electrode dielectric layer between the shield electrode and the gate electrode, and the step of forming the trench gate structure at least includes: forming an insulating layer covering the inner wall surface of the groove; and forming an initial spacer layer before the step of forming the inter-electrode dielectric layer, wherein the initial spacer layer has a first sidewall portion and a second sidewall portion respectively covering the two inner sidewall surfaces of the insulating layer, the bottom end of the first sidewall portion and the bottom end of the second sidewall portion are separated from each other, and the first sidewall portion and the second sidewall portion both have an extension portion protruding from the epitaxial layer.

Description

Manufacturing method of trench type power semiconductor element
Technical Field
The present invention relates to a method for manufacturing a power transistor, and more particularly, to a method for manufacturing a trench power semiconductor device having a shielding electrode.
Background
The operating loss of the conventional trench Power MOSFET (Power Metal Oxide Semiconductor Field Transistor) can be divided into two categories, i.e., switching loss (switching loss) and conduction loss (conduction loss), wherein the capacitance (Cgd) of the gate/drain is an important parameter affecting the switching loss. Too high gate/drain capacitance results in increased switching losses, which limits the switching speed of the power mosfet and is not suitable for high frequency circuits.
The conventional trench power mosfet has a shielding electrode (shielding electrode) located at the lower half of the gate trench to reduce the gate/drain capacitance and increase the breakdown voltage without sacrificing on-resistance.
Disclosure of Invention
The invention provides a manufacturing method of a trench type power semiconductor element, which forms a protective layer and a spacing layer on the surface of an epitaxial layer and the side wall of a trench so as to protect the surface of the epitaxial layer and the side wall surface of the trench from being oxidized in the process of executing a thermal oxidation process.
One embodiment of the present invention provides a method for manufacturing a trench power semiconductor device, including: forming an epitaxial layer on a substrate; forming a protective layer on a surface of the epitaxial layer; and forming a trench gate structure in the trench, wherein the trench gate structure has a shielding electrode, a gate electrode over the shielding electrode, and an inter-electrode dielectric layer between the shielding electrode and the gate electrode, and the step of forming the trench gate structure at least includes: forming an insulating layer covering an inner wall surface of the trench; and before the step of forming the inter-electrode dielectric layer, forming an initial spacer layer, wherein the initial spacer layer has a first sidewall portion and a second sidewall portion respectively covering the two inner sidewall surfaces of the insulating layer, the bottom end of the first sidewall portion and the bottom end of the second sidewall extension portion are separated from each other, and the first sidewall portion and the second sidewall portion both have an extension portion protruding from the protective layer.
In summary, in the method for manufacturing a trench type power semiconductor device according to the embodiments of the present invention, before forming the inter-electrode dielectric layer by a thermal oxidation process, a protection layer is formed on the surface of the epitaxial layer and spacers are formed on the sidewalls of the trench to protect the surface of the epitaxial layer and the sidewalls of the trench from being oxidized.
In addition, the bottom end of the first side wall part of the spacing layer is separated from the bottom end of the second side wall extension part, when reverse bias is applied to the trench type power semiconductor element, because the trench gate structure is filled into the bottom of the trench and the material right below the shielding electrode is simple, the electric field distribution at the bottom of the trench can be relieved, and therefore the breakdown voltage of the element can be further improved under the condition of not sacrificing the on-resistance.
For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description of the invention and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.
Drawings
Fig. 1 is a flow chart of a trench power semiconductor device according to an embodiment of the invention.
Fig. 2A to 2O are schematic partial cross-sectional views of a trench power semiconductor device in each processing step according to an embodiment of the invention.
Fig. 3A to fig. 3C are schematic partial cross-sectional views of a trench power semiconductor device in accordance with another embodiment of the present invention at various processing steps.
[ notation ] to show
Trench type power semiconductor devices T1 and T2
Substrate 10
Epitaxial layer 11
Surface 11s
Base region 110
Source region 111
Liner oxide layer 12
Sacrificial oxide layer SAC
Protective layer 13
Groove 11h
Opening h1
Hard film layer 14
Insulating layer 15
Inner side wall surface 15a
Bottom surface 15b
Spacing dielectric layer 16 "
Initial spacer layer 16'
First side wall 161'
Second side wall part 162'
Extensions 161 'S, 162' S
Initial inner dielectric layer 17'
Inner dielectric layer 17
Heavily doped semiconductor material 18'
Shield electrode 18
Inter-electrode dielectric layer 19
Spacer layer 16
First spacer 161
Second spacer 162
Accommodating space H1
Trench gate structures G1, G2
Grid 20
Interlayer dielectric layer 21
Contact window 21h
Heavily doped contact region 112
Conductive post 22
Source metal layer 23
Process steps S100 to S500, S401 to S407
Detailed Description
Referring to fig. 1, a flowchart of a trench power semiconductor device according to an embodiment of the invention is shown. Fig. 2A to fig. 2O are schematic partial cross-sectional views of a trench power semiconductor device in each processing step according to an embodiment of the invention.
As shown in fig. 1, in step S100, an epitaxial layer is formed on a substrate, and in step S200, a protective layer is formed on a surface of the epitaxial layer. Please refer to fig. 2A-2B.
As shown in fig. 2A, an epitaxial layer 11 is formed on a substrate 10, wherein the epitaxial layer 11 has a surface 11s far away from the substrate 10.
The substrate 10 has a high concentration of the first type conductivity impurity as a drain region (drain) of the trench power semiconductor device. The first type conductivity impurity may be an N-type or P-type conductivity impurity. Assuming that the substrate 10 is a silicon substrate, the N-type conductivity impurity is a pentavalent ion, such as a phosphorous ion or an arsenic ion, and the P-type conductivity impurity is a trivalent ion, such as a boron ion, an aluminum ion, or a gallium ion.
The epitaxial layer 11(epitaxial layer) has the same conductivity type as the substrate 10, but the doping concentration of the epitaxial layer 11 is lower thanThe doping concentration of the substrate 10. In the case of an NMOS transistor, the substrate 10 has a high concentration of N-type dopant (N)+) And epitaxial layer 11 has a low concentration of N-type doping (N)-). For example, in the case of a PMOS transistor, the substrate 10 and the epitaxial layer 11 have a high concentration of P-type dopant (P)+doping) and low concentration of P-type doping (P)-doping)。
In addition, in the present embodiment, after the step of forming the epitaxial layer 11 on the substrate 10, a pad oxide layer 12(pad oxide) is further formed on the surface 11s of the epitaxial layer 11. The pad oxide layer 12 may serve as an etch stop layer in subsequent processes.
Next, as shown in fig. 2B, a protective layer 13 is formed on the pad oxide layer 12, wherein the material of the protective layer 13 is different from the material of the pad oxide layer 12. The material of the protective layer 13 may be a nitride, such as: the silicon nitride protects the surface 11s of the epitaxial layer 11 from being oxidized in the subsequent thermal oxidation process.
With reference to fig. 2C, after the step of forming the protection layer 13, the method for manufacturing the trench power semiconductor device of the present embodiment further includes: a hard film 14 is formed on the protection layer 13.
Referring to fig. 1, next, in step S300, a trench is formed in the epitaxial layer. As shown in fig. 2D, a trench 11h is formed in the epitaxial layer 11. In the step of forming the trench 11h in the epitaxial layer 11, an opening h1 communicating with the trench 11h is also formed in the hard film layer 14 and the protective layer 13.
The step of forming the trench 11h and the opening h1 may apply any known technical means. For example, a patterned photoresist (not shown) is formed on the hard film layer 14 to define the position of the opening h 1. Subsequently, an opening h1 is formed by patterning the photoresist, and a trench 11h is further formed in the epitaxial layer 11. Alternatively, the trenches 11h may be formed in the epitaxial layer 11 by an etching process, such as dry etching or wet etching.
Please continue to refer to fig. 2E. In this embodiment, after forming the trench 11h in the epitaxial layer 11, forming a sacrificial oxide layer SAC on an inner wall surface of the trench 11h is further included. The sacrificial oxide layer SAC may be formed on the inner wall surface of the trench 11h by a thermal oxidation process.
Since the inner wall surface of the trench 11h has lattice defects when the trench 11h is formed, the sacrificial oxide layer SAC is formed on the inner wall surface of the trench 11h, and then the sacrificial oxide layer SAC is removed, so that the inner wall surface of the trench 11h can be repaired, and the lattice defects on the inner wall surface can be reduced to prevent the leakage phenomenon of the device.
It should be noted that, since the surface of the epitaxial layer 11 has the protection layer 13 and the hard film layer 14 before the trench 11h is formed, the surface 11s of the epitaxial layer 11 can be protected from being oxidized continuously during the process of forming the sacrificial oxide layer SAC by the thermal oxidation process. Next, referring to fig. 2F, the sacrificial oxide layer SAC is removed again.
Please refer to fig. 1 again. In step S400, a trench gate structure is formed in the trench. In this embodiment, the step of forming the trench gate structure further includes steps S401 to S407.
In detail, in step S401, an insulating layer covering an inner wall surface of the trench is formed. As shown in fig. 2G, the insulating layer 15 covers the inner wall surface of the trench 11h and has a profile substantially conforming to the inner wall surface of the trench 11 h. As shown in fig. 2G, the insulating layer 15 has two inner sidewall surfaces 15a facing each other and a bottom surface 15b connected between the two inner sidewall surfaces 15 a. The insulating layer 15 may be an oxide layer formed by thermal oxidation, such as: silicon oxide.
Referring to fig. 1, in step S402, an initial spacer layer is formed. In detail, please refer to fig. 2H to fig. 2I.
As shown in fig. 2H, an interlayer dielectric layer 16 "is formed, and the interlayer dielectric layer 16" covers the surface of the hard film 14, the inner surface of the opening H1, the two inner sidewall surfaces 15a and the bottom surface 15b of the insulating layer 15 in a blanket manner. In addition, in the present embodiment, the material of the spacer dielectric layer 16 ″ and the material of the protection layer 13 may be the same, for example, both are nitride. However, the material of the spacer dielectric layer 16 "and the material of the insulating layer 15 are different. In the present embodiment, the thickness of the spacer dielectric layer 16 "remains substantially the same and does not decrease as the depth of the trench 11h increases.
Next, please refer to fig. 2I. The bottom surface 15b of the partially covered insulating layer 15 and the spacer dielectric layer 16 ″ covering the surface of the hard film layer 14 are removed to form an initial spacer layer 16'. In one embodiment, the bottom surface 15b of the insulating layer 15 and the spacer dielectric layer 16 ″ covering the surface of the hard film layer 14 are partially removed by a dry etching (dry etching) process, leaving the spacer dielectric layer (i.e., the initial spacer layer 16') on the two inner sidewall surfaces 15a of the insulating layer 15.
In other words, the preliminary spacer layer 16 ' has a first sidewall portion 161 ' and a second sidewall portion 162 ' covering the two inner sidewall surfaces 15a of the insulating layer 15, respectively. In addition, the bottom end of the first sidewall portion 161 'and the bottom end of the second sidewall portion 162' are separated from each other, thereby exposing the bottom surface 15b of the insulating layer 15. In addition, the first sidewall 161 'and the second sidewall 162' have an extension 161 'S, 162' S protruding from the protection layer 13, and the extension 161 'S, 162' S covers the inner surface of the opening h 1.
Please refer to fig. 1 again. Next, in step S403, an initial inter-dielectric layer is formed to cover the initial spacer layer, wherein the bottom of the initial inter-dielectric layer is directly connected to the bottom surface of the insulating layer 15.
Please refer to fig. 2J. An initial inter-dielectric layer 17' overlies the surface 11s of the epitaxial layer 11 and within the trenches 11 h. In addition, the bottom of the initial inner dielectric layer 17' is directly connected to the bottom surface 15b of the insulating layer 15. In this embodiment, the material constituting the initial internal dielectric layer 17 'is different from the material constituting the initial spacer layer 16', but the same as the material constituting the insulating layer 15. In one embodiment, the insulating layer 15 and the initial inter-dielectric layer 17 'are silicon oxide layers, and the initial spacer layer 16' is a silicon nitride layer.
Thus, the material filled into the bottom of the trench 11h is relatively simple, and the electric field distribution at the bottom of the trench can be relaxed, so that the breakdown voltage of the device can be further improved without sacrificing the on-resistance.
Referring to fig. 1, in step S404, a heavily doped semiconductor material is formed in the lower portion of the trench. In step S405, the initial ild layer on the upper half of the trench is removed to form an ild layer on the lower half of the trench. As shown in fig. 2K, heavily doped semiconductor material 18' fills the lower half of the trench 11 h.
In one embodiment, a heavily doped semiconductor layer is first blanket formed on the epitaxial layer 11 and filled into the trench 11 h. Then, an etch back is performed to remove the heavily doped semiconductor layer covered on the surface of the epitaxial layer 11, and leave the heavily doped semiconductor material 18' in the lower half of the trench 11 h. The heavily doped semiconductor material 18' is, for example, a polysilicon structure (doped poly-Si) containing conductive impurities.
After removing the initial inter-dielectric layer 17 'located at the upper half of the trench 11h, the top of the heavily doped semiconductor material 18' protrudes above the top surface of the inter-dielectric layer 17. In addition, after removing the preliminary inter-dielectric layer 17' positioned at the upper half portion of the trench 11h, the hard film layer 14 positioned on the protection layer 13 is also removed.
Referring to fig. 1 again, in step S406, a thermal oxidation process is performed to oxidize the top of the heavily doped semiconductor material, thereby forming the inter-electrode dielectric layer 19 and the shielding electrode 18.
As shown in fig. 2L, after a thermal oxidation process is performed, the top portion of the heavily doped semiconductor material 18 'is oxidized to form the inter-electrode dielectric layer 19, and the portion of the heavily doped semiconductor material 18' that is not oxidized forms the shielding electrode 18. It should be noted that the epitaxial layer 11 is not oxidized further when the thermal oxidation process is performed due to the protection of the initial spacer layer 16' and the protective layer 13.
Next, referring to fig. 1 again, in step S407, a gate is formed in the upper half of the trench and insulated from the shielding electrode by the inter-electrode dielectric layer.
Please refer to fig. 2M to fig. 2N. As shown in fig. 2M, in one embodiment of the present invention, before forming the gate 20, the extensions 161 ' S and 162 ' S and the initial spacer 16 ' located in the upper half of the trench 11h are removed to form a spacer 16. At this time, the protective layer 13 is also removed in this step. The spacer 16 is disposed under the gate 20 and includes a first spacer 161 and a second spacer 162 respectively disposed on two opposite sides of the shielding electrode 18.
In fig. 2M, the insulating layer 15, the interpoly dielectric layer 19 and the spacer 16 define a receiving space H1 in the upper half of the trench 11H. Then, referring to fig. 2N, the gate 20 is formed in the accommodating space H1 at the upper half of the trench 11H.
In the step of forming the gate 20, a heavily doped polysilicon material may be first blanket-filled into the epitaxial layer 11 and the accommodating space H1, and then the heavily doped polysilicon material on the epitaxial layer 11 is removed by etching back to form the gate 20. Through the steps S401 to S407, the trench gate structure G1 may be formed in the trench 11 h.
Referring to fig. 1 again, in step S500, a body region and a source region are formed in the epitaxial layer, and the source region is located above the body region. In the embodiment of the present invention, after forming the body region and the source region, the method further includes: and forming a circuit redistribution layer on the surface of the epitaxial layer. Referring to fig. 2O, a cross-sectional view of a trench power semiconductor device according to an embodiment of the invention is shown.
In detail, a body doping process is performed on the epitaxial layer 11 to form a lightly doped region in the epitaxial layer 11, wherein the lightly doped region has a conductivity type opposite to that of the epitaxial layer 11. Then, a source doping process is performed on the lightly doped region to form a heavily doped region in the upper half of the lightly doped region, wherein the conductivity type of the heavily doped region is opposite to that of the lightly doped region. Next, a drive-in process is performed to diffuse the impurities in the lightly doped region and the heavily doped region to form a body region 110 and a source region 111, wherein the source region 111 is located above the body region 110.
Subsequently, a circuit redistribution layer may be formed on the epitaxial layer 11, so that the source region 111, the gate electrode 20 and the shielding electrode 18 may be electrically connected to an external control circuit. The technical means for forming the line redistribution layer may be implemented by any known technical means.
Specifically, the interlayer dielectric layer 21 is formed on the epitaxial layer 11. Thereafter, a plurality of contact holes 21h are formed through the interlayer dielectric layer 21, and the contact holes 21h extend to the source regions 111.
Thereafter, a doping process is performed through the contact hole 21h to form a heavily doped contact region 112 below the contact hole 21 h. Thereafter, the conductive pillars 22 are formed in the contact windows 21h, and the source metal layer 23 connecting the conductive pillars 22 is formed on the interlayer dielectric layer 21. That is, the source metal layer 23 may be electrically connected to the source region 111 through the conductive pillar 22.
The trench gate structure G1 of the trench power semiconductor device T1 formed through the above process includes an insulating layer 15, a spacer layer 16, an inter-layer dielectric 17, a shielding electrode 18, an inter-layer dielectric 19, and a gate 20.
The material of the spacer layer 16 is different from the material of the insulating layer 15 and the material of the inter-dielectric layer 17. The spacer layer 16 includes a first spacer 161 and a second spacer 162. The bottom end of the first spacer 161 and the bottom end of the second spacer 162 are separated from each other by a predetermined distance, and the predetermined distance is greater than the width of the shielding electrode 18.
In the present embodiment, the first spacer 161 and the second spacer 162 are located in the lower half of the trench 11h and are sandwiched between the insulating layer 15, the inter-electrode dielectric layer 19, and the inter-layer dielectric layer 17. That is, the first spacers 161 and the second spacers 162 of the present embodiment do not serve as the gate insulating layer.
Referring to fig. 3A to fig. 3C, cross-sectional views of a trench power semiconductor device in various processing steps according to another embodiment of the invention are shown. The first spacers 161 and the second spacers 162 of the trench power semiconductor device T2 formed by the manufacturing method of the present embodiment are used as gate insulating layers in cooperation with the insulating layer 15.
In the method for manufacturing a trench power semiconductor device according to another embodiment of the present invention, the steps of fig. 3A to 3C are performed after the steps of fig. 2A to 2L are completed.
Referring to fig. 3A, unlike the embodiment of fig. 2M in which the extensions 161 ' S and 162 ' S are directly removed from the upper portion of the trench 11h, in fig. 3A, the gate 20 is first formed in the upper portion of the trench 11h without removing the extensions 161 ' S and 162 ' S, the protection layer 13, and the initial spacer 16 ' located in the upper portion of the trench 11 h.
Referring to fig. 3B, the protective layer 13 and the extension portions 161 'S and 162' S on the epitaxial layer 11 are removed to form the spacer layer 16. The protective layer 13 and the extension portions 161 'S and 162' S may be removed by chemical mechanical polishing or selective etching.
The trench gate structure G2 of the present embodiment is different from the trench gate structure G1 of fig. 2N in that the first spacer 161 and the second spacer 162 of the spacer 16 both extend from the upper half of the trench 11h to the lower half of the trench 11 h. In addition, the first spacers 161 and the second spacers 162 cooperate with the insulating layer 15 to serve as a gate insulating layer to adjust the work function between the body region 110 and the gate 20, thereby reducing the leakage current during operation.
Finally, the body region 110, the source region 111 and the line redistribution layer are formed to form the trench power semiconductor device T2 shown in fig. 3C.
In summary, in the method for manufacturing a trench power semiconductor device provided in the present invention, before forming the inter-electrode dielectric layer 19 by a thermal oxidation process, the protective layer 13 is formed on the surface 11s of the epitaxial layer 11 and the spacer layer 16 is formed on the sidewall of the trench 11h to protect the surface 11s of the epitaxial layer 11 and the sidewall of the trench 11h from being further oxidized.
In addition, the bottom end of the first spacer 161 of the spacer 16 is separated from the bottom end of the second spacer 162, so that when a reverse bias is applied to the trench power semiconductor device, the material filled into the bottom of the trench 11h and located right under the shielding electrode 18 is relatively simple, so as to relax the electric field distribution at the bottom of the trench 11h, thereby further improving the breakdown voltage of the device without sacrificing the on-resistance.
Under the condition of improving the breakdown voltage, the doping concentration of the epitaxial layer 11 can be further optimized, so that the on-resistance is reduced, and the voltage conversion efficiency of the operation of the trench type power semiconductor element is improved. Simulation tests prove that the electric field distribution of the groove type power semiconductor element in the embodiment of the invention at the bottom of the groove 11h is smoother, so that the breakdown voltage is improved. Therefore, the on-resistance of the trench power semiconductor device according to the embodiment of the invention can be reduced by 50%.
In addition, in one of the trench power semiconductor devices T2 provided in the present invention, the insulating layer 15 and the spacer layer 16 made of two different materials are used as the gate insulating layer, so that the work function between the gate 20 and the body region 110 can be adjusted, thereby reducing the leakage current (leakage current) when the trench power semiconductor device T2 is operated under reverse bias.
The manufacturing method of the trench power semiconductor device of the embodiment of the invention can be integrated in the existing semiconductor manufacturing process to provide the trench power semiconductor device provided by the invention.
The disclosure is only a preferred embodiment of the invention and should not be taken as limiting the scope of the invention, so that the invention is not limited by the disclosure of the invention.

Claims (12)

1. A manufacturing method of a trench type power semiconductor element is characterized by comprising the following steps:
forming an epitaxial layer on a substrate;
forming a protective layer on a surface of the epitaxial layer;
forming a trench in the epitaxial layer; and
forming a trench gate structure in the trench, wherein the trench gate structure has a shield electrode, a gate electrode over the shield electrode, and an inter-electrode dielectric layer between the shield electrode and the gate electrode, and the step of forming the trench gate structure at least comprises:
forming an insulating layer covering an inner wall surface of the trench;
forming an initial spacer layer;
forming an initial inner dielectric layer covering the initial spacer layer, wherein the bottom of the initial inner dielectric layer is directly connected with the bottom surface of the insulating layer;
forming a heavily doped semiconductor material on the lower half part of the groove;
removing the initial inner dielectric layer positioned on the upper half part of the groove to form an inner dielectric layer positioned on the lower half part of the groove, wherein the inner dielectric layer surrounds the heavily doped semiconductor material, and the top of the heavily doped semiconductor material protrudes out of the top surface of the inner dielectric layer;
applying a thermal oxidation process to oxidize the top of the heavily doped semiconductor material to form the inter-electrode dielectric layer and the shielding electrode, wherein, when the thermal oxidation process is applied, the initial spacer layer has a first sidewall portion and a second sidewall portion respectively covering two inner sidewall surfaces of the insulating layer, the bottom ends of the first sidewall portion and the second sidewall portion are separated from each other, and the first sidewall portion and the second sidewall portion both have an extension portion protruding from the protective layer; and
and forming the grid electrode on the upper half part of the groove.
2. The method of manufacturing a trench power semiconductor device according to claim 1, wherein the method of manufacturing a trench power semiconductor device further comprises:
and forming a hard film layer on the protective layer before the step of forming the groove.
3. The method of manufacturing a trench power semiconductor device according to claim 2, wherein the hard film layer on the surface of the epitaxial layer is removed after the step of forming the inter-dielectric layer.
4. The method for manufacturing a trench power semiconductor device according to claim 2, wherein in the step of forming the trench, an opening communicating with the trench is formed in the hard film layer and the protective layer.
5. The method of manufacturing a trench power semiconductor device of claim 4 wherein the step of forming the initial spacer layer further comprises:
forming a spacing dielectric layer, wherein the spacing dielectric layer covers the surface of the hard film layer, the inner surface of the opening, the two inner side wall surfaces and the bottom surface of the insulating layer, and the material of the spacing dielectric layer is the same as that of the protective layer; and
and removing a part of the interval dielectric layer covering the bottom surface and the surface of the hard film layer to form the initial interval layer, wherein the two extending parts of the first side wall part and the second side wall part cover the inner surface of the opening.
6. The method of claim 5 wherein said spacer dielectric layer and said protective layer are nitride layers and said insulating layer and said inter-dielectric layer are oxide layers.
7. The method of manufacturing a trench power semiconductor device of claim 1 wherein forming the trench gate structure further comprises: before the step of forming the gate on the upper half portion of the trench, the extension portion and the initial spacer layer on the upper half portion of the trench are removed to form a spacer layer, wherein the spacer layer is located below the gate and includes a first spacer portion and a second spacer portion respectively located on two opposite sides of the shielding electrode.
8. The method of claim 7 wherein said protective layer is removed during the step of removing said extension and said initial spacer layer in said upper portion of said trench.
9. The method of manufacturing a trench power semiconductor device of claim 1 wherein forming the trench gate structure further comprises: after the step of forming the gate on the upper half portion of the trench, the extension portion protruding from the surface of the epitaxial layer is removed to form a spacer layer, wherein the spacer layer includes a first spacer portion and a second spacer portion, and the first spacer portion and the second spacer portion are located outside the gate and serve as gate insulating layers.
10. The method of claim 9, wherein the step of removing the extension portions is performed by removing the protective layer together.
11. The method of manufacturing a trench power semiconductor device as claimed in claim 1, wherein the method of manufacturing a trench power semiconductor device further comprises: and forming a body region and a source region in the epitaxial layer.
12. The method of manufacturing a trench power semiconductor device as claimed in claim 11, wherein the method of manufacturing a trench power semiconductor device further comprises: and forming a circuit redistribution layer on the surface of the epitaxial layer, wherein the circuit redistribution layer comprises an interlayer dielectric layer positioned on the epitaxial layer, a source electrode conductive layer positioned on the interlayer dielectric layer and at least one conductive column penetrating through the interlayer dielectric layer, and the source electrode conductive layer is electrically connected with the source electrode region through the conductive column.
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