CN109215979A - A kind of patch type inductance and preparation method thereof - Google Patents
A kind of patch type inductance and preparation method thereof Download PDFInfo
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- CN109215979A CN109215979A CN201811209431.3A CN201811209431A CN109215979A CN 109215979 A CN109215979 A CN 109215979A CN 201811209431 A CN201811209431 A CN 201811209431A CN 109215979 A CN109215979 A CN 109215979A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 110
- 238000005516 engineering process Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 162
- 239000002356 single layer Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 28
- 241000237858 Gastropoda Species 0.000 claims description 27
- 238000010276 construction Methods 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000010329 laser etching Methods 0.000 claims description 4
- 241001061264 Astragalus Species 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000004804 winding Methods 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
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- 238000005859 coupling reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/29—Terminals; Tapping arrangements for signal inductances
- H01F27/292—Surface mounted devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/32—Insulating of coils, windings, or parts thereof
- H01F27/323—Insulation between winding turns, between winding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/041—Printed circuit coils
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/10—Connecting leads to windings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/12—Insulating of windings
- H01F41/122—Insulating between turns or between winding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/0073—Printed inductances with a special conductive pattern, e.g. flat spiral
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
- H01F2027/2809—Printed windings on stacked layers
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Abstract
The invention discloses a kind of patch type inductance and preparation method thereof, patch type inductance includes pin layer and is located at spaced insulating layer and metal layer on pin layer, and the patterned metal structures correspondence in each metal layer is electrically connected to form multilayer planar spiral wire coil structures；Two ends of multilayer planar spiral wire coil structures are electrically connected with the corresponding pin structure for being located at pin layer respectively.According to the technical solution of the present invention, be conducive to obtain larger inductance value in smaller size, while being advantageously implemented the miniaturization of patch type inductance, patch type inductance can be made using semiconductor technology, be conducive to the size for accurately controlling patch type inductance, improve the precision of patch type inductance, while being also beneficial to improve the conductivity of patch type inductance, the resistance value of patch type inductance is reduced, the Q value of patch type inductance is improved.
Description
Technical field
The present embodiments relate to electronic component technology fields more particularly to a kind of patch type inductance and preparation method thereof.
Background technique
As the integrated level of the raising that user requires miniaturization of electronic products, electronic product is gradually increased, this is just to electricity
More stringent requirements are proposed for the size of electronic component included in sub- product, and how electronic component takes into account miniaturization and electronics
The electric property of element itself becomes urgent problem to be solved.
Patch type inductance is commonly utilized in each electronic product, and the size and electric property of patch type inductance directly affect collection
At the size and performance of the electronic product for having patch type inductance, this is again such that patch type inductance takes into account miniaturization and patch type
The electric property of inductance itself becomes most important.
Summary of the invention
In view of this, the present invention provides a kind of patch type inductance and preparation method thereof, be conducive to obtain in smaller size
Larger inductance value is taken, that is, while being advantageously implemented the miniaturization of patch type inductance, patch type can be made using semiconductor technology
Inductance is conducive to the size for accurately controlling patch type inductance, improves the precision of patch type inductance, while being also beneficial to improve patch
The conductivity of formula inductance reduces the resistance value of patch type inductance, improves the Q value of patch type inductance.
In a first aspect, the embodiment of the invention provides a kind of patch type inductance, patch type inductance includes:
Pin layer and be located at the pin layer on spaced insulating layer and metal layer, be located at each metal layer in
Patterned metal structures correspondence be electrically connected to form multilayer planar spiral wire coil structures；
Two ends of the multilayer planar spiral wire coil structures respectively be located at the pin layer corresponding pin knot
Structure electrical connection.
Further, along the axial direction of the multilayer planar spiral wire coil structures, the multilayer planar spiral wire loop knot
Structure includes multiple single layer snail shape loop constructions, the dielectric knot between the two neighboring single layer snail loop construction
The thickness of structure is greater than the thickness of the single layer planar spiral winding.
Further, the material for constituting the dielectric structure includes PI.
Further, the plane where being axially perpendicular to the pin layer of the multilayer planar spiral wire coil structures, or
The plane where being axially parallel to the pin layer of multilayer planar spiral wire coil structures described in person.
Further, along the axial direction of the multilayer planar spiral wire coil structures, the multilayer planar spiral wire loop knot
Structure includes multiple single layer snail shape loop constructions, and the single layer snail shape loop construction forms an at least astragal loop knot
Structure.
Further, the pin configuration includes pad structure and the metal structure on the pad structure, institute
Two ends for stating spiral wire coil structures are electrically connected with corresponding metal structure respectively.
Second aspect, the embodiment of the invention also provides a kind of production methods of patch type inductance, for making first party
Patch type inductance described in face, the production method of chip inductor include:
Form substrate；
The first patterned metal structures are formed over the substrate；
The first insulating layer is formed on first patterned metal structures and in the setting position of first insulating layer
Upper formation through-hole structure；
The second patterned metal structures are formed on the first insulating layer, and second patterned metal structures pass through position
It is electrically connected in the through-hole structure of first insulating layer with first patterned metal structures；
It is alternatively formed insulating layer and patterned metal structures, until forming N insulating layer；Wherein, N is the integer greater than 1；
Form pin configuration.
Further, after forming pin configuration, further includes:
Remove the substrate or the grinding substrate.
Further, M1 patterned metal structures are formed using electroplating technology, sputtering technology or etching technics；Wherein,
M1 is positive integer.
Further, the material for constituting M2 insulating layer includes PI, utilizes dry etch process or laser etching process
Through-hole structure is formed on the setting position of M2 insulating layer；Wherein, M2 is positive integer.
The embodiment of the invention provides a kind of patch type inductance, patch type inductance is set and includes pin layer and is located at pin
Spaced insulating layer and metal layer on layer, the patterned metal structures correspondence in each metal layer are electrically connected to form multilayer
Snail shape loop construction, two ends of multilayer planar spiral wire coil structures are respectively at the corresponding pin for being located at pin layer
Structure electrical connection.In this way, being arranged at intervals with insulating layer and metal layer in patch type inductance, and the pattern metal knot in metal layer
Multilayer planar spiral wire coil structures are configured to, is being conducive to obtain larger inductance value in smaller size, that is, is being advantageously implemented
While patch type inductance minimizes, patch type inductance can be made using semiconductor technology, be conducive to accurately control patch type
The size of inductance, improves the precision of patch type inductance, while being also beneficial to improve the conductivity of patch type inductance, reduces patch type
The resistance value of inductance improves the Q value of patch type inductance.
Detailed description of the invention
By reading a detailed description of non-restrictive embodiments in the light of the attached drawings below, the application's is other
Feature, objects and advantages will become more apparent upon:
Fig. 1 is a kind of structural schematic diagram of patch type inductance provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another patch type inductance provided in an embodiment of the present invention；
Fig. 3 is a kind of flow diagram of the production method of patch type inductance provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.It is same or similar in this specification
Drawing reference numeral represent the same or similar structure, element or process.It should be noted that in the absence of conflict, this Shen
Please in embodiment and embodiment in feature can be combined with each other.
The embodiment of the invention provides a kind of patch type inductance, patch type inductance includes pin layer and is located on pin layer
Spaced insulating layer and metal layer, the patterned metal structures correspondence in each metal layer are electrically connected to form multilayer planar
Spiral wire coil structures, two ends of multilayer planar spiral wire coil structures respectively be located at pin layer corresponding pin structure
Electrical connection.
As the integrated level of the raising that user requires miniaturization of electronic products, electronic product is gradually increased, this is just to electricity
More stringent requirements are proposed for the size of electronic component included in sub- product, and how electronic component takes into account miniaturization and electronics
The electric property of element itself becomes urgent problem to be solved.Patch type inductance is commonly utilized in each electronic product, patch type
The size of inductance and electric property directly affect the size and performance for being integrated with the electronic product of patch type inductance, this again such that
The electric property that patch type inductance takes into account miniaturization and patch type inductance itself becomes most important.
Patch type inductance provided in an embodiment of the present invention include pin layer and be located at pin layer on spaced insulation
Layer and metal layer, the patterned metal structures correspondence in each metal layer are electrically connected to form multilayer planar spiral wire loop knot
Two ends of structure, multilayer planar spiral wire coil structures are electrically connected respectively at the corresponding pin structure for being located at pin layer.In this way,
Insulating layer and metal layer are arranged at intervals in patch type inductance, and the patterned metal structures in metal layer form multilayer planar spiral shell
Shape loop construction is revolved, is being conducive to obtain larger inductance value in smaller size, that is, is advantageously implemented the miniaturization of patch type inductance
While, patch type inductance can be made using semiconductor technology, be conducive to the size for accurately controlling patch type inductance, improve patch
The precision of chip inductor, while being also beneficial to improve the conductivity of patch type inductance, the resistance value of patch type inductance is reduced, is improved
The Q value of patch type inductance.
It is core of the invention thought above, following will be combined with the drawings in the embodiments of the present invention, to the embodiment of the present invention
In technical solution be clearly and completely described.Based on the embodiments of the present invention, those of ordinary skill in the art are not having
Under the premise of making creative work, every other embodiment obtained be shall fall within the protection scope of the present invention.
Fig. 1 is a kind of structural schematic diagram of patch type inductance provided in an embodiment of the present invention.As shown in Figure 1, patch type is electric
Sense is including pin layer 1 and is located at spaced insulating layer 2 and metal layer 3 on pin layer 1, the figure in each metal layer 3
Case metal structure 31, which corresponds to, is electrically connected to form multilayer planar spiral wire coil structures, and the two of multilayer planar spiral wire coil structures
A end 4 is electrically connected with the corresponding pin structure 10 for being located at pin layer 1 respectively, and Fig. 1 is illustratively provided with above pin layer 1
Five layers of metal layer 3, the embodiment of the present invention are not construed as limiting the particular number of 1 upper metal layer 3 of pin layer.
Along the direction perpendicular to pin layer 1, it is provided with insulating layer 2 between every adjacent two metal layers 3, to realize phase
Patterned metal structures 31 are not necessarily to the electrical isolation of electrical connections in adjacent metal layer 3, undermost metal layer 3 and pin layer 1 it
Between be also equipped with insulating layer 2, be electrically insulated between undermost metal layer 3 and pin layer 1 with realizing without electrical connections.Figure
1 illustrates only the through-hole structure 20 in each insulating layer 2, and two ends 4 of multilayer planar spiral wire coil structures pass through position
Through-hole structure 20 in corresponding insulating layer 2 is electrically connected with the realization of corresponding pin structure 10 for being located at pin layer 1.
Fig. 2 is the structural schematic diagram of another patch type inductance provided in an embodiment of the present invention.With the patch of structure shown in Fig. 1
Unlike chip inductor, the patch type inductance of structure shown in Fig. 1 is formed by the axial direction of multilayer planar spiral wire coil structures
YY ' is perpendicular to 1 place plane of pin layer, the multilayer planar spiral wire coil structures of the patch type inductance formation of structure shown in Fig. 2
Axial XX ' be parallel to 1 place plane of pin layer.Fig. 2 illustratively above pin layer 1 be provided with two metal layers 3, two layers
Insulating layer 2 is provided between metal layer 3, and to realize, patterned metal structures 31 are exhausted without the electricity of electrical connections in two metal layers 3
Edge, likewise, be also equipped with insulating layer 2 between undermost metal layer 3 and pin layer 1, with realize undermost metal layer 3 with
The electrical isolation of electrical connections is not necessarily between pin layer 1.Fig. 2 equally illustrates only the through-hole structure 20 in each insulating layer 2,
Two ends 4 of multilayer planar spiral wire coil structures are by being located at the through-hole structure 20 corresponded in insulating layer 2 and being located at pin
The corresponding pin structure 10 of layer 1 realizes electrical connection.
The patch type inductance generallyd use at present is that (Muiti-layer Ceramic Capacitiors, chip are more by MLCC
Layer ceramic capacitor), use ceramic material to constitute, conductivity is lower, and manufacture craft is rougher, so that patch type inductance
Q value is lower, is unable to accurately control the size of patch type inductance, and patch type inductance precision is lower, is difficult to realize patch type inductance
Miniaturization.Insulating layer 2 and metal layer 3 are arranged at intervals in patch type inductance provided in an embodiment of the present invention, and in metal layer 3
Patterned metal structures 31 form multilayer planar spiral wire coil structures, are being conducive to obtain larger inductance in smaller size
Value while being advantageously implemented the miniaturization of patch type inductance, can be made patch type inductance using semiconductor technology, be conducive to
The size of accurate control patch type inductance, improves the precision of patch type inductance, while being also beneficial to improve the electricity of patch type inductance
Conductance reduces the resistance value of patch type inductance, improves the Q value of patch type inductance.
Optionally, along the axial direction of multilayer planar spiral wire coil structures, multilayer planar spiral wire coil structures include multiple
The dielectric structure between two neighboring single layer snail shape loop construction 5 can be set in single layer snail shape loop construction 5
Thickness be greater than single layer snail shape loop construction 5 thickness.As shown in Figure 1, the single layer snail in patch type inductance
The axial direction of shape loop construction 5 is equally along the direction XX ', along the axial XX ' of patch type inductance, adjacent two single layers snail shape coil
The thickness of dielectric structure between structure 5 is equal to the thickness of insulating layer 2 between adjacent metal 3.As shown in Fig. 2, patch type is electric
The axial direction of single layer snail shape loop construction 5 in sense is equally along the direction YY ', adjacent two single layers snail shape loop construction
Dielectric structure between 5 is vertical the distance between two single layer snail shape loop constructions 5.
Specifically, either the axially vertical of the patch type inductance of multilayer planar spiral wire coil structures is also parallel to draw
1 place plane of foot layer, the thickness that the dielectric structure between two neighboring single layer snail shape loop construction 5 is arranged are greater than single layer
The thickness of snail shape loop construction 5 is arranged relative to the patch type inductance of same thickness along the axial single of patch type inductance
The thickness of layer plane spiral wire coil structures 5 is equal to the thickness of dielectric structure, increases adjacent monolayer snail shape coil knot
It is too small caused along patch type inductance to improve distance between adjacent monolayer snail shape loop construction 5 for the distance between structure 5
Axial direction, the coupling between adjacent single layer snail shape loop construction 5 is too strong, influences the resonance frequency of patch type inductance
The problem of rate, improves the resonance frequency of patch type inductance.Illustratively, the material for constituting dielectric structure can be PI, i.e., poly-
Acid imide, namely constituting the material of insulating layer 2 is PI.
Optionally, along the axial direction of multilayer planar spiral wire coil structures, multilayer planar spiral wire coil structures include multiple
Single layer snail shape loop construction 5 can be set single layer snail shape loop construction 5 and form an at least astragal coil structures,
The wire circle of the example single layer snail shape loop construction 5 in the top metal layer 3 as shown in figure 1 is greater than 1, in this way can be
The bigger inductance value of patch type inductance is obtained in identical size, is equally beneficial for realizing the miniaturization of patch type inductance.Shown in Fig. 2
It includes multi-turn coil that single layer snail shape loop construction 5, which equally can be set, in the patch type inductance of structure, equally can be in phase
With the bigger inductance value of patch type inductance is obtained in size, it is advantageously implemented the miniaturization of patch type inductance.It should be noted that
The single layer snail shape loop construction 5 that the patch type inductance of structure shown in Fig. 2 is arranged includes multi-turn coil relative to current Fig. 2
Shown in one-turn coil single layer snail shape loop construction 5, increase the processing procedure number of patch type inductance, be preferably provided with Fig. 1
The single layer snail shape loop construction 5 of the patch type inductance of shown structure includes multi-turn coil.
Optionally, referring to Figures 1 and 2, the pin configuration 10 of patch type inductance may include pad structure 101 and be located at
Metal structure 102 on pad structure 101, two ends 4 of multilayer planar spiral wire coil structures respectively with corresponding metal
Structure 102 is electrically connected.Illustratively, the material for constituting pad structure 101 can be scolding tin, convenient for patch type inductance in printing electricity
Welding on the plate of road can be set in composition pin configuration 10 and pattern in the material of metal structure 102 and each metal layer 3 of composition
The material of metal structure 31 is identical.It should be noted that the embodiment of the present invention is to the specific material for constituting patterned metal structures 31
Material is not construed as limiting, preferably conductivity high metal material or metal oxide materials, to improve patch type inductance to the full extent
Q value.
The embodiment of the invention also provides a kind of production methods of patch type inductance, for making described in above-described embodiment
Patch type inductance, Fig. 3 are a kind of flow diagram of the production method of patch type inductance provided in an embodiment of the present invention.Such as Fig. 3
Shown, the production method of patch type inductance includes:
S110, substrate is formed.
Specifically, substrate is formed, which can be the wafer of 8 cun of wafers, 12 cun of wafers or 500mmx500mm size
Etc. larger sized wafer, the shape of substrate can be circle, square, rectangle etc., and the material for constituting substrate can be silicon, glass
One or more of glass, quartz, ceramics or organic matter.
S120, the first patterned metal structures are formed on the substrate.
Specifically, referring to Fig.1, the first patterned metal structures 311 are formed on substrate (substrate is not shown in Fig. 1), it can
Using plating, sputtering or first to deposit one layer of metal layer 3 and the techniques such as etch again and form the first patterned metal structures 311.Reference
Fig. 2 forms the first patterned metal structures 311 on substrate (substrate is not shown in Fig. 2), equally can use electroplating technology,
Sputtering technology first deposits one layer of metal layer 3 and the techniques such as etches again and forms the first patterned metal structures 311, it is preferred to use plating
Technique forms the first patterned metal structures 311, and electroplating technology can form the biggish metallic diaphragm of thickness, is conducive to improve patch
The Q value of formula inductance.
S130, the first insulating layer and the shape on the setting position of the first insulating layer are formed on the first patterned metal structures
At through-hole structure.
Specifically, referring to Fig.1, the first insulating layer 21 is formed on the first patterned metal structures 311 and in the first insulation
Through-hole structure 20 is formed on the setting position of layer 21, Fig. 1 is not shown the first insulating layer 21, illustrates only positioned at the first insulating layer 21
Through-hole structure 20.Referring to Fig. 2, the first insulating layer 21 is formed on the first patterned metal structures 311 and in the first insulating layer
Through-hole structure 20 is formed on 21 setting position, likewise, the first insulating layer 21 is not shown in Fig. 2, is illustrated only positioned at first absolutely
The through-hole structure 20 of edge layer 21.
Illustratively, the material for constituting the first insulating layer 21 may include PI i.e. polyimides, can first deposit one layer absolutely
Edge layer 21, then through-hole structure is formed on the setting position of the first insulating layer 21 by dry etch process or laser etching process
20.For the patch type inductance of structure shown in Fig. 2, since 21 thickness of the first insulating layer is larger, in the first insulating layer 21
20 elongate form of through-hole structure, preferably laser etching process form through-hole structure 20 on the setting position of the first insulating layer 21.
S140, the second patterned metal structures are formed on the first insulating layer, the second patterned metal structures are by being located at
The through-hole structure of first insulating layer is electrically connected with the first patterned metal structures.
Specifically, referring to 1 and Fig. 2, the second patterned metal structures 312 are formed on the first insulating layer 21, constitute second
The material of patterned metal structures 312 fills the through-hole structure 20 on the first insulating layer 21, and the second patterned metal structures 311 are logical
It crosses positioned at the realization of through-hole structure 20 of the first insulating layer 21 and being electrically connected for the first patterned metal structures 311, it equally can benefit
With electroplating technology, sputtering technology or first deposits one layer of metal layer and the techniques such as etch again and form the second patterned metal structures 312.
S150, it is alternatively formed insulating layer and patterned metal structures, until forming N insulating layer；Wherein, N is greater than 1
Integer.
Specifically, referring to Fig.1, second insulating layer 22 and the subsequent patterned metal structures 31 being arranged alternately are continuously formed
With insulating layer 2, until formed the 5th insulating layer 25, the 5th insulating layer 25 be located at bottom metal layer 3 and pin configuration 10 it
Between with realize the metal layer 3 of bottom with pin configuration 10 being electrically insulated without electrically connecting position.Referring to Fig. 2, the is continuously formed
Two insulating layers 22, second insulating layer 22 are located at the metal that bottom is realized between the metal layer 3 and pin configuration 10 of bottom
Being electrically insulated without electrically connecting position with pin configuration 10 of layer 3.
S160, pin configuration is formed.
Specifically, referring to Figures 1 and 2, pin configuration 10 is including pad structure 101 and on pad structure 101
Metal structure 102, the metal structure 102 that can be initially formed on the insulating layer 2 of bottom in pin configuration 10, then in metal
Pad structure 101 is formed in structure 102, and metal structure 102 and 101 shape one of pad structure in pin configuration 10 can be set
It causes, the two realizes patterning to simplify manufacturing process simultaneously.
Optionally, after forming pin configuration 10, substrate or grinding substrate can be removed, i.e. removing is located at the first metal
The substrate of 31 top of layer or grinding are located at the substrate of 31 top of the first metal layer to form complete patch type inductance.It is served as a contrast in removal
After bottom or grinding substrate, the surface mounting component size that form standard can be cut to metal layer 3 and insulating layer 2, such as 0201,
01005 or smaller size of surface mounting component.
Illustratively, referring to Fig. 2, it can also be initially formed substrate, such as can be silicon wafer, using TSV (Through
Silicon Via, through silicon via) technique forms through-hole structure 20 on the setting position of substrate, that is, and six formed in Fig. 2 are elongated
Through-hole structure 20, then make the first patterned metal structures 311 and the second pattern metal knot respectively in the front and back sides of substrate
Structure 312, the front or back of substrate form corresponding insulating layer 2 and pin configuration 10, unlike the embodiments above, the party
The substrate that method is formed is enclosed in inside patch type inductance, substrate can also using the other materials such as dielectric material or glass and
Corresponding technique is made, and the embodiment of the present invention is not construed as limiting this.
Patch type inductance provided in an embodiment of the present invention include pin layer and be located at pin layer on spaced insulation
Layer and metal layer, the patterned metal structures correspondence in each metal layer are electrically connected to form multilayer planar spiral wire loop knot
Structure, two ends of multilayer planar spiral wire coil structures are electrically connected respectively at the corresponding pin structure for being located at pin layer, can be with
Patch type inductance is made using the semiconductor technology that above-described embodiment is related to, is conducive to the size for accurately controlling patch type inductance,
The precision of patch type inductance is improved, while being also beneficial to improve the conductivity of patch type inductance, reduces the resistance of patch type inductance
Value improves the Q value of patch type inductance.In addition, being arranged at intervals with insulating layer and metal layer, and metal in the patch type inductance formed
Patterned metal structures in layer form multilayer planar spiral wire coil structures, are conducive to obtain larger inductance in smaller size
Value is advantageously implemented the miniaturization of patch type inductance.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiments here, be able to carry out for a person skilled in the art it is various it is apparent variation, again
Adjustment and substitution are without departing from protection scope of the present invention.Therefore, although by above embodiments to the present invention carried out compared with
For detailed description, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, can be with
Including more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of patch type inductance characterized by comprising
Pin layer and be located at the pin layer on spaced insulating layer and metal layer, the figure in each metal layer
Case metal structure correspondence is electrically connected to form multilayer planar spiral wire coil structures；
Two ends of the multilayer planar spiral wire coil structures are electric with the corresponding pin structure positioned at the pin layer respectively
Connection.
2. patch type inductance according to claim 1, which is characterized in that along the multilayer planar spiral wire coil structures
Axial, the multilayer planar spiral wire coil structures include multiple single layer snail shape loop constructions, the two neighboring list
The thickness of dielectric structure between layer plane helical coil structure is greater than the thickness of the single layer planar spiral winding.
3. patch type inductance according to claim 2, which is characterized in that the material for constituting the dielectric structure includes PI.
4. patch type inductance according to claim 1, which is characterized in that the axis of the multilayer planar spiral wire coil structures
The pin is axially parallel to perpendicular to plane where the pin layer or the multilayer planar spiral wire coil structures
Plane where layer.
5. patch type inductance according to claim 1, which is characterized in that along the multilayer planar spiral wire coil structures
Axial, the multilayer planar spiral wire coil structures include multiple single layer snail shape loop constructions, the single layer plane spiral shell
It revolves shape loop construction and forms an at least astragal coil structures.
6. patch type inductance according to claim 1, which is characterized in that the pin configuration includes pad structure and position
Metal structure on the pad structure, two ends of the spiral wire coil structures are electric with corresponding metal structure respectively
Connection.
7. a kind of production method of patch type inductance, special for making patch type inductance described in any one of claims 1-6
Sign is that the production method includes:
Form substrate；
The first patterned metal structures are formed over the substrate；
The first insulating layer and the shape on the setting position of first insulating layer are formed on first patterned metal structures
At through-hole structure；
The second patterned metal structures are formed on the first insulating layer, and second patterned metal structures are by being located at institute
The through-hole structure for stating the first insulating layer is electrically connected with first patterned metal structures；
It is alternatively formed insulating layer and patterned metal structures, until forming N insulating layer；Wherein, N is the integer greater than 1；
Form pin configuration.
8. the production method of patch type inductance according to claim 7, which is characterized in that after forming pin configuration,
Further include:
Remove the substrate or the grinding substrate.
9. the production method of patch type inductance according to claim 7, which is characterized in that utilize electroplating technology, sputtering work
Skill or etching technics form M1 patterned metal structures；Wherein, M1 is positive integer.
10. the production method of patch type inductance according to claim 7, which is characterized in that constitute the material of M2 insulating layer
Material includes PI, forms through-hole on the setting position of M2 insulating layer using dry etch process or laser etching process
Structure；Wherein, M2 is positive integer.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811209431.3A CN109215979A (en) | 2018-10-17 | 2018-10-17 | A kind of patch type inductance and preparation method thereof |
| JP2020538547A JP2021510457A (en) | 2018-10-17 | 2019-02-22 | Chip inductor and its manufacturing method |
| US17/261,787 US12094631B2 (en) | 2018-10-17 | 2019-02-22 | Chip inductor and method for manufacturing same |
| PCT/CN2019/075804 WO2020077928A1 (en) | 2018-10-17 | 2019-02-22 | Chip inductor and method for manufacturing same |
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| CN201811209431.3A CN109215979A (en) | 2018-10-17 | 2018-10-17 | A kind of patch type inductance and preparation method thereof |
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