WO2024037547A1

WO2024037547A1 - Semiconductor structure and method for manufacturing same, and semiconductor device

Info

Publication number: WO2024037547A1
Application number: PCT/CN2023/113183
Authority: WO
Inventors: 韩智毅; 陈曦
Original assignee: 韩智毅; 陈曦
Priority date: 2022-08-15
Filing date: 2023-08-15
Publication date: 2024-02-22
Also published as: CN115331927A

Abstract

A semiconductor structure and a method for manufacturing same, and a semiconductor device. The semiconductor structure comprises: a substrate (110); a first oxide layer (120) formed on the substrate (110); a plurality of first conductive lines (130) formed on the first oxide layer (120) and arranged in a particular direction; a second oxide layer (140) formed on the first oxide layer (120) and the plurality of first conductive lines (130), wherein a plurality of through holes (11) are formed in the second oxide layer (140), such that either end of each first conductive line (130) is respectively connected to one through hole (11), and the through hole (11) is filled with a conductive material; and a plurality of second conductive lines (150) formed on the second oxide layer (140) and respectively connected to one or more through holes (11), such that the plurality of first conductive lines (130), the plurality of through holes (11), and the plurality of second conductive lines (150) jointly form a spirally connected conductive structure.

Description

Semiconductor structures and preparation methods, semiconductor devices

This disclosure claims priority to the Chinese patent application filed with the China Patent Office on August 15, 2022, with application number 202210974331. This disclosure is ongoing.

Technical field

Embodiments of the present disclosure relate to the field of electronic devices, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure, as well as a semiconductor device.

Background technique

Inductor coils are widely used in substrate-based semiconductors and related processes. For example, in wireless chip applications, metal wires in the semiconductor process can be used to design coils of different shapes to receive wireless signals. However, these current structures basically adopt a coil structure in which the axis OO' is perpendicular to the substrate surface as shown in Figure 1 .

However, the coil structure shown in Figure 1 whose axis is perpendicular to the substrate surface has low adaptability, cannot meet the requirements of flexible and diverse device design and application, and will increase the cost of the system. Therefore, a semiconductor structure with flexible spatial geometry and modulation parameters, a preparation method of the semiconductor structure, and a semiconductor device are needed to meet various corresponding needs for diversified device design and applications.

Contents of the invention

In order to solve the above technical problems, according to one aspect of the present disclosure, a semiconductor structure is provided, including: a substrate; a first oxide layer formed on the substrate; a plurality of first conductive lines formed on the first on the oxide layer and arranged along a specific direction; a second oxide layer formed on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer, The two ends of each first conductive line among the plurality of first conductive lines are respectively connected to a through hole, and the through hole is filled with conductive material; and a plurality of second conductive lines are formed on the The second oxide layer is respectively connected to one or more through holes, so that the plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines together form a spirally connected conductive structure.

According to some embodiments of the present disclosure, an axis direction of the spirally connected conductive structure is parallel to the substrate.

According to some embodiments of the present disclosure, the specific direction is a straight line direction parallel to the substrate.

According to some embodiments of the present disclosure, the plurality of first conductive lines are parallel to each other.

According to some embodiments of the present disclosure, the plurality of second conductive lines are parallel to each other.

According to some embodiments of the present disclosure, the specific direction is a ring-shaped, arc-shaped or sector-shaped direction parallel to the substrate.

According to some embodiments of the present disclosure, the second oxide layer includes a plurality of stacked oxide sub-layers, The plurality of sub-via holes in the plurality of oxide sub-layers respectively penetrate up and down, constituting at least a part of the plurality of through-holes in the second oxide layer.

According to some embodiments of the present disclosure, one end of a second conductive line is connected to a through hole connected to a first conductive line, and the other end is connected to a through hole connected to another first conductive line, such that the The plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines together form a spirally connected conductive structure.

According to some embodiments of the present disclosure, the plurality of first conductive lines, the plurality of through holes, and the plurality of second conductive lines together form a plurality of conductive structures that are spirally connected and nested with each other, and the There are no electrical connections between the plurality of conductive structures.

According to some embodiments of the present disclosure, the first conductive line is composed of polysilicon material.

According to some embodiments of the present disclosure, the semiconductor structure further includes: an insulating layer formed on the second oxide layer and/or a plurality of second conductive lines; and/or one or more third conductive lines , is electrically connected to the spirally connected conductive structure, so that the spirally connected conductive structure and the one or more third conductive lines constitute at least a part of the semiconductor device.

According to another aspect of the present disclosure, a method for preparing a semiconductor structure is provided, including: forming a first oxide layer on a substrate; and forming a plurality of first conductive lines arranged in a specific direction on the first oxide layer. ; Forming a second oxide layer on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer so that in the plurality of first conductive lines Both ends of each first conductive line are respectively connected to a through hole, and the through holes are filled with conductive material; and a plurality of first conductive lines are formed on the second oxide layer and are respectively connected to one or more through holes. second conductive lines, so that the plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines together form a spirally connected conductive structure.

According to some embodiments of the present disclosure, forming a second oxide layer on the first oxide layer and the plurality of first conductive lines includes: forming a second oxide layer on the first oxide layer and the plurality of first conductive lines. A plurality of stacked oxide sub-layers are respectively formed on the second oxide layer to form the second oxide layer. A plurality of sub-through holes are respectively formed in the plurality of oxide sub-layers. The plurality of sub-through holes respectively penetrate up and down to form the second oxide layer. At least a portion of the plurality of through holes in the oxide layer.

According to some embodiments of the present disclosure, the method further includes: forming an insulating layer on the second oxide layer and/or the plurality of second conductive lines; and/or forming a conductive structure electrically connected to the spiral. The connected one or more third conductive lines, the spirally connected conductive structure and the one or more third conductive lines constitute at least a part of the semiconductor device.

According to yet another aspect of the present disclosure, a semiconductor device is provided, including the semiconductor structure as described in any one of the above.

According to some embodiments of the present disclosure, the semiconductor device is at least one of an energy conversion device, an energy storage device, a current measurement device, a voltage conversion device, an isolation communication device, or any combination thereof.

According to some embodiments of the present disclosure, parameters of the spirally connected conductive structures constituting the semiconductor structure are determined according to the type and/or parameters of the semiconductor device.

According to some embodiments of the present disclosure, the parameters of the spirally connected conductive structure include at least one of the following: a coil size of the spirally connected conductive structure; an axial length and/or shape of the spirally connected conductive structure ; and the number of turns of the spirally connected conductive structure.

According to the semiconductor structure, the preparation method of the semiconductor structure, and the semiconductor device provided by the embodiments of the present disclosure, a coil structure whose axis is approximately parallel to the substrate surface can be provided to flexibly control the direction and distribution trend of the magnetic lines of force on the substrate. Obtain high magnetic flux semiconductor devices. According to the semiconductor structure, the preparation method of the semiconductor structure, and the semiconductor device according to the embodiments of the present disclosure, corresponding physical models can be generated through the multi-dimensional modulation parameters of the coil structure, and various types of devices can be flexibly and conveniently manufactured according to the needs of actual applications. Semiconductor devices with spatial geometric structures improve design efficiency and device performance and adapt to different application scenarios.

Description of drawings

In order to explain the technical solutions in the embodiments of the present disclosure more clearly, the drawings needed to be used in the description of the embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 shows a coil structure in which the axis OO' is perpendicular to the substrate surface used in the prior art;

Figure 2 shows a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

Figure 3 shows a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

Figure 4 shows an example of a double-layer conductive structure that is spirally connected and nested with each other according to one embodiment of the present disclosure;

Figure 5 shows an example of a three-layer conductive structure that is spirally connected and nested with each other according to one embodiment of the present disclosure;

Figure 6 shows the orientation of axis OO' of a spirally connected conductive structure according to one embodiment of the present disclosure. Various example pictures;

7 shows an example of various top views of an axis OO' of a spirally connected conductive structure according to one embodiment of the present disclosure;

8 illustrates another example of a spirally connected conductive structure according to one embodiment of the present disclosure;

9 illustrates a flow chart of a method of manufacturing a semiconductor structure according to one embodiment of the present disclosure;

10 shows a schematic diagram of forming a first oxide layer on a substrate and manufacturing a plurality of first conductive lines according to an embodiment of the present disclosure;

Figure 11 shows a schematic diagram of forming a second oxide layer on the first oxide layer and forming a through hole according to an embodiment of the present disclosure;

Figure 12 shows a schematic diagram of an energy conversion device according to one embodiment of the present disclosure;

Figure 13 shows a schematic diagram of an energy storage device according to one embodiment of the present disclosure;

Figure 14 shows a schematic diagram of a current measurement device according to one embodiment of the present disclosure;

Figure 15 shows a schematic diagram of a voltage conversion device according to one embodiment of the present disclosure;

Figure 16 shows a schematic diagram of an isolated communication device according to one embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the usual meaning understood by a person with ordinary skill in the art to which this disclosure belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprising" mean that the elements or things appearing before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to express relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some well-known functions and well-known components.

Flowcharts are used in this disclosure to illustrate the steps of methods according to embodiments of the disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the various steps can be processed in reverse order or simultaneously. At the same time, you can add other operations to these processes, or remove a step or steps from these processes.

In semiconductor-related processes, when a coil structure with the axis OO' perpendicular to the substrate surface is used, one or more of the following shortcomings will result:

(1) The coil structure is essentially a coil structure using a two-dimensional geometric space structure. The structural adaptability is low and cannot meet the requirements of flexible and diverse device design and application.

(2) This coil structure loses a lot of magnetic energy and makes device design difficult. Specifically, when a coil structure with an axis perpendicular to the substrate is used, its magnetic field lines will be perpendicular to the substrate, which will cause most of the magnetic field lines of the coil structure to be arranged outside the device, causing greater loss of magnetic energy and making it difficult to achieve The high magnetic flux coil structure also makes it difficult to flexibly adjust and improve the Q factor. In addition, the arrangement of magnetic lines of force in this coil structure is relatively complex, making it difficult to calculate and process magnetic signals for this structure.

(3) The number of turns of the coil in this coil structure is limited. In the substrate-based semiconductor process manufacturing process, the two-dimensional geometric space structure results in a relatively limited number of coil turns in the coil structure. It is difficult to design and manufacture coils of comparable size and with a large number of turns, and it is also difficult to meet the requirements of more complex requirements. The structural requirements of multi-coil structure and mutual induction coil structure.

Based on the above shortcomings, the application of the semiconductor device formed by the above-mentioned coil structure perpendicular to the substrate surface is limited, and the design and production cost of the semiconductor device are increased.

Therefore, it is hoped to provide a semiconductor structure with flexible spatial geometry and modulation parameters, a preparation method of the semiconductor structure, and a semiconductor device to meet various corresponding needs for diversified device design and applications.

FIG. 2 shows a schematic structural diagram of a semiconductor structure 100 according to an embodiment of the present disclosure.

As shown in FIG. 2 , the semiconductor structure 100 includes a substrate 110 , a first oxide layer 120 , a first conductive line 130 , a second oxide layer 140 and a second conductive line 150 . Wherein, a first oxide layer 120 is formed on the substrate 110; a plurality of first conductive lines 130 are formed on the first oxide layer 120 and arranged along a specific direction; a second oxide layer 140 is formed on the on the first oxide layer 120 and the plurality of first conductive lines 130 , wherein a plurality of through holes 11 are formed in the second oxide layer 140 such that each of the plurality of first conductive lines 130 Both ends of 130 are respectively connected to a through hole 11, which is filled with conductive material; a plurality of second conductive lines 150 are formed on the second oxide layer 140, and are respectively connected to one or more through holes. The holes 11 are connected so that the plurality of first conductive lines 130 , the plurality of through holes 11 and the plurality of second conductive lines 150 together form a spirally connected conductive structure. Optionally, the axis direction of the spirally connected conductive structure may be parallel or substantially parallel to the substrate.

In the spirally connected conductive structure shown in FIG. 2 , the substrate 110 may be a semiconductor substrate, for example, the substrate 110 may be a silicon substrate. The plurality of first conductive lines 130 formed on the first oxide layer 120 on the substrate 110 may be a plurality of metal lines obtained by etching the metal layer deposited on the first oxide layer 120 . Optionally, the plurality of first conductive lines 130 may be arranged along a specific direction. In one example, the specific direction may be a straight line direction parallel to the substrate 110 . That is to say, the plurality of first conductive lines 130 may be arranged one by one along a straight line direction parallel to the substrate 110 . Multiple metal threads for cloth. In another example, the specific direction may be a ring-shaped, arc-shaped or sector-shaped direction parallel to the substrate 110 . That is to say, the plurality of first conductive lines 130 may be a direction parallel to the substrate 110 . 110 multiple metal wires arranged one by one in a circular, arc or fan-shaped direction. In addition, optionally, the plurality of first conductive lines 130 may also be parallel to each other. For example, the plurality of first conductive lines 130 may be arranged in parallel one by one along a straight line direction parallel to the substrate 110 . of multiple metal wires. The above-mentioned arrangement directions and arrangements of the first conductive lines 130 are only examples. In practical applications, different arrangement directions and arrangements of the first conductive lines 130 can be designed according to the specific requirements of the spirally connected conductive structure. There are no restrictions here.

After the plurality of first conductive lines 130 are formed, a second oxide layer 140 may be formed on the first oxide layer 120 and the plurality of first conductive lines 130 , wherein the second oxide layer 140 may include a plurality of stacked oxide layers 140 . sub-layers (140-1, 140-2...), the plurality of via holes 11 formed in the second oxide layer 140 may be composed of multi-layer sub-via holes ( 11-1,11-2…). Wherein, the multi-layer sub-through holes (11-1, 11-2...) respectively penetrate up and down, and are combined to form at least a part of the plurality of through holes 11 in the second oxide layer 140. In addition, optionally, one or more metal connection layers (not shown in the figure) can also be formed between any adjacent oxide sub-layers in the plurality of oxide sub-layers (140-1, 140-2...) as needed. ), the one or more metal connection layers are formed by etching metal layers deposited between adjacent oxide sub-layers, enabling conductive connections to be formed between via holes stacked up and down in each oxide sub-layer. FIG. 3 shows a semiconductor structure according to an embodiment of the present disclosure, wherein, as shown in FIG. 3 , the second oxide layer 140 may include three stacked oxide sub-layers (140-1, 140-2, 140-3). The plurality of through holes 11 formed in the second oxide layer 140 may be composed of three layers of sub-through holes (11-1, 11-2, 11-) respectively formed in three oxide sub-layers (140-1, 140-2, 140-3) 3) combined. Of course, in another example, the plurality of vias 11 formed in the second oxide layer 140 may be composed of sub-vias 11-1, metal connection layer 1, sub-vias 11-2, metal connection layer 2, sub-vias It is composed of holes 11-3, and the arrangement and order of the sub-vias and metal connection layers are not limited here.

Returning to FIG. 2 , a plurality of second conductive lines 150 may be formed on the second oxide layer 140 and connected to one or more through holes 11 respectively. The plurality of second conductive lines 150 may be formed through the second oxide layer 140 . The multiple metal lines obtained by etching the metal layer deposited on 140 may be formed in the same or different manner as the aforementioned first conductive lines 130 . Optionally, the plurality of second conductive lines 150 may also be arranged along a specific direction in the second oxide layer 140 , and may be arranged in the same or different manner as the first conductive lines 130 . In one example, the specific direction may be a straight line direction parallel to the substrate 110 . That is to say, the plurality of second conductive lines 150 may be arranged one by one along a straight line direction parallel to the substrate 110 . Multiple metal threads for cloth. In another example, the specific direction may also be a ring-shaped, arc-shaped or sector-shaped direction parallel to the substrate 110. That is to say, the plurality of second conductive lines 150 may be in a direction parallel to the substrate 110. A plurality of metal lines are arranged one by one in the circular, arc or fan-shaped direction of the bottom 110 . In addition, optionally, the plurality of second conductive lines 150 may also be parallel to each other. For example, the plurality of second conductive lines 150 may be arranged in parallel one by one along a straight line direction parallel to the substrate 110 . of multiple metal wires. The above-mentioned arrangement directions and arrangements of the second conductive lines 150 are only examples. In practical applications, different arrangement directions and arrangements of the second conductive lines 150 can be designed according to the specific requirements of the spirally connected conductive structure. There are no restrictions here.

Optionally, as shown in FIG. 2 , one end of a second conductive line 150 may be connected to a through hole connected to a first conductive line, and the other end may be connected to another through hole connected to another first conductive line. holes, so that the plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines together form a spirally connected conductive structure.

In an example of the present disclosure, optionally, the plurality of first conductive lines, the plurality of through holes, and the plurality of second conductive lines together form a spirally connected conductive structure, which may include as shown in Figure 2 One spirally connected conductive structure, that is, a coil; it may also include multiple spirally connected and mutually nested conductive structures, that is, multiple coils, and there may be no electrical connection between the multiple conductive structures. Figure 4 shows the An example of a spirally connected and mutually nested double-layer conductive structure (ie, two coils nested within each other) of one embodiment is disclosed. As shown in FIG. 4 , the spirally connected and mutually nested double-layer conductive structure formed on the substrate 110 may include two coils, respectively C1 and C2, where the respective metal lines of C1 and C2 are arranged approximately parallel, and There is no electrical connection between C1 and C2. FIG. 5 shows an example of a three-layer conductive structure that is spirally connected and nested with each other (ie, three coils are nested with each other) according to one embodiment of the present disclosure. As shown in FIG. 5 , the spirally connected and mutually nested three-layer conductive structure formed on the substrate 110 may include three coils, namely C1, C2 and C3, where the respective metal lines of C1, C2 and C3 are arranged. are approximately parallel, and there is no electrical connection between C1, C2 and C3. The above design and arrangement of multiple conductive structures that are spirally connected and nested with each other are only examples. In actual applications, multiple separate or nested conductive structures can be designed according to various scene requirements. The method is not limited here.

Optionally, at least one of the first conductive line, the through hole and the second conductive line may be made of metal material; in addition, optionally, the first conductive line, the through hole and the second conductive line may be made of metal material. At least one of the second conductive lines may be composed of polysilicon material. For example, the first conductive line may be etched from a polysilicon layer formed on an oxide layer on the substrate. The above material selection methods for the first conductive line, the through hole and the second conductive line are only examples. In practical applications, the first conductive line, all the materials can be selected according to various different scene requirements. The through hole and the second conductive line may be made of different materials, which is not limited here.

According to an embodiment of the present disclosure, various electronic components (such as chips, etc.) may be first prepared within the substrate, and then a semiconductor structure as described in the present disclosure may be prepared on the substrate to interact with the substrate. The electronic components prepared in the bottom are electrically connected, and these electronic components are controlled through the semiconductor structure and the semiconductor devices it constitutes.

According to an embodiment of the present disclosure, the semiconductor structure may further include: an insulating layer formed on the second oxide layer and/or a plurality of second conductive lines; and/or one or more third conductive lines, and The spirally connected conductive structure is electrically connected, and the spirally connected conductive structure and the one or more third conductive lines constitute at least a part of the semiconductor device. In this embodiment, after the semiconductor back-end process is completed, the spirally connected conductive structure can be covered with an insulating layer to form a through hole and connect one or more third conductive lines obtained by subsequent etching of the metal layer deposited. The one or more third conductive lines are used to connect the remaining components of the semiconductor device to prepare different semiconductor devices according to actual needs using the spirally connected conductive structures.

The above discloses an example of a basic structure of a spirally connected conductive structure composed of a plurality of first conductive lines, a plurality of through holes, and a plurality of second conductive lines according to an embodiment of the present disclosure. In practical applications, various improvements or deformations can be made to the spirally connected conductive structure, and these improvements and deformations are also within the scope of the present disclosure. In practical applications, various designs can be made for the axis direction of the spirally connected conductive structure according to the application scenario. Figure 6 shows various examples of the direction of the axis OO' of the spirally connected conductive structure according to one embodiment of the present disclosure. picture. As shown in FIG. 6 , the axis OO′ of the spirally connected conductive structure does not have to be strictly parallel to the substrate 110 , but may be at a certain angle relative to the substrate, or extend approximately parallel to the substrate 110 in a curved manner. Yes, there is no restriction here. In addition, FIG. 7 shows various views of the axis OO′ of the spirally connected conductive structure facing the substrate according to one embodiment of the present disclosure. Example of view. As shown in Figure 7, the axis OO' of the spirally connected conductive structure can also be a fully closed or semi-closed structure, such as a closed or semi-closed arc, circle, square, triangle, ellipse, pentagon Or various irregular patterns, etc., so that the spirally connected conductive structure correspondingly forms a surrounding or semi-circling coil, so that the magnetic field lines can form a closed or semi-closed loop in the direction parallel to the substrate according to the design to adapt to different application scenarios needs.

In addition, in practical applications, various designs can be made for the conductive lines and through holes of the spirally connected conductive structure according to the application scenario. Figure 8 shows another example of the spirally connected conductive structure according to one embodiment of the present disclosure. . As shown in FIG. 8 , the conductive lines and through holes that make up the spirally connected conductive structure may not be strictly parallel or perpendicular to the substrate 110 , nor may they be strictly straight lines, but may be designed in various ways according to the needs of the actual scenario, and Flexibly arrange the extension direction and arrangement order of each first conductive line, second conductive line, through hole (sub-via hole, metal connection layer), etc., as long as it can form a connected and conductive spiral structure, there is no limit here .

The above shows a semiconductor structure according to an embodiment of the present disclosure. This semiconductor structure can provide a coil structure with an axis approximately parallel to the substrate surface to flexibly control the direction and distribution trend of magnetic lines of force on the substrate to obtain a high magnetic flux semiconductor. device. According to the semiconductor structure of the embodiment of the present disclosure, a corresponding physical model can be generated through the multi-dimensional modulation parameters of the coil structure, and semiconductor devices with various spatial geometric structures can be flexibly and conveniently manufactured according to the needs of practical applications, thereby improving design efficiency and device performance to adapt to different application scenarios.

FIG. 9 shows a flow chart of a method 900 for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

As shown in Figure 9, the preparation method of the semiconductor structure includes:

Step S901: Form a first oxide layer on the substrate;

Step S902: Form a plurality of first conductive lines arranged along a specific direction on the first oxide layer;

Step S903: Form a second oxide layer on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer so that the plurality of first conductive lines Two ends of each first conductive line in the line are respectively connected to a through hole, and the through hole is filled with conductive material;

Step S904: Form a plurality of second conductive lines respectively connected to one or more through holes on the second oxide layer, so that the plurality of first conductive lines, the plurality of through holes and the plurality of through holes are formed. The two second conductive lines together form a spirally connected conductive structure.

As shown in FIG. 2 , the prepared semiconductor structure 100 may include a substrate 110 , a first oxide layer 120 , a first conductive line 130 , a second oxide layer 140 and a second conductive line 150 . Wherein, a first oxide layer 120 is formed on the substrate 110; a plurality of first conductive lines 130 are formed on the first oxide layer 120 and arranged along a specific direction; a second oxide layer 140 is formed on the on the first oxide layer 120 and the plurality of first conductive lines 130 , wherein a plurality of through holes 11 are formed in the second oxide layer 140 such that each of the plurality of first conductive lines 130 Both ends of 130 are respectively connected to a through hole 11, which is filled with conductive material; a plurality of second conductive lines 150 are formed on the second oxide layer 140, and are respectively connected to one or more through holes. The holes 11 are connected so that the plurality of first conductive lines 130 , the plurality of through holes 11 and the plurality of second conductive lines 150 together form a spirally connected conductive structure. Optionally, the axis OO' direction of the spirally connected conductive structure may be parallel or substantially parallel to the substrate.

According to an embodiment of the present disclosure, in step S901, a first oxide layer is formed on the substrate.

In the spirally connected conductive structure shown in FIG. 2 , the substrate 110 may be a semiconductor substrate, for example, the substrate 110 may be a silicon substrate.

In step S902, a plurality of first conductive lines arranged in a specific direction are formed on the first oxide layer.

In the spirally connected conductive structure shown in FIG. 2 , the plurality of first conductive lines 130 formed on the first oxide layer 120 on the substrate 110 may be formed by etching the metal layer deposited on the first oxide layer 120 . Multiple metal lines obtained by etching. Optionally, the plurality of first conductive lines 130 may be arranged along a specific direction. In one example, the specific direction may be a straight line direction parallel to the substrate 110 . That is to say, the plurality of first conductive lines 130 may be arranged one by one along a straight line direction parallel to the substrate 110 . Multiple metal threads for cloth. In another example, the specific direction may be a ring-shaped, arc-shaped or sector-shaped direction parallel to the substrate 110 . That is to say, the plurality of first conductive lines 130 may be a direction parallel to the substrate 110 . 110 multiple metal wires arranged one by one in a circular, arc or fan-shaped direction. In addition, optionally, the plurality of first conductive lines 130 may also be parallel to each other. For example, the plurality of first conductive lines 130 may be arranged in parallel one by one along a straight line direction parallel to the substrate 110 . of multiple metal wires. The above-mentioned arrangement directions and arrangements of the first conductive lines 130 are only examples. In practical applications, different arrangement directions and arrangements of the first conductive lines 130 can be designed according to the specific requirements of the spirally connected conductive structure. There are no restrictions here.

FIG. 10 shows a schematic diagram of forming a first oxide layer 120 on a substrate 110 and manufacturing a plurality of first conductive lines 130 according to an embodiment of the present disclosure. As shown in FIG. 10 , after forming the first oxide layer 120 on the substrate 110 , a metal layer can be deposited on the first oxide layer 120 , and a plurality of first conductive lines 130 can be formed by etching. Alternatively, the plurality of first conductive lines 130 may be a plurality of metal lines arranged one by one along a straight line direction parallel to the substrate 110 , and the plurality of first conductive lines 130 may also be parallel to each other.

In step S903, a second oxide layer is formed on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer such that the plurality of first conductive lines are Two ends of each first conductive line in a conductive line are respectively connected to a through hole, and the through hole is filled with conductive material. FIG. 11 shows a schematic diagram of forming a second oxide layer on the first oxide layer and a plurality of first conductive lines and forming through holes according to an embodiment of the present disclosure. As shown in FIG. 11 , after forming a plurality of first conductive lines 130 , a second oxide layer 140 may be formed on the first oxide layer 120 and the plurality of first conductive lines 130 , and a plurality of first conductive lines 130 may be manufactured on the second oxide layer 140 . The through holes 11 are filled with conductive material, so that the through holes 11 can be electrically connected to the first conductive lines 130 respectively.

Optionally, forming a second oxide layer on the first oxide layer may include: respectively forming a plurality of stacked oxide sub-layers on the first oxide layer and a plurality of first conductive lines to form the second oxide layer. In the oxide layer, a plurality of sub-through holes are respectively formed in the plurality of oxide sub-layers, and the plurality of sub-through holes respectively penetrate up and down to form at least a part of the plurality of through holes in the second oxide layer. Specifically, referring to FIG. 3 , the second oxide layer 140 may include a plurality of stacked oxide sub-layers (140-1, 140-2...), and the plurality of through holes 11 formed in the second oxide layer 140 may be formed by It is composed of multi-layer sub-vias (11-1, 11-2...) formed in oxide sub-layers (140-1, 140-2...). Wherein, the multi-layer sub-through holes (11-1, 11-2...) respectively penetrate up and down, and are combined to form at least a part of the plurality of through holes 11 in the second oxide layer 140. In addition, optionally, between any adjacent oxide sub-layers in the plurality of oxide sub-layers (140-1, 140-2...), If necessary, one or more metal connection layers (not shown in the figure) are formed. The one or more metal connection layers are formed by etching the metal layer deposited between adjacent oxide sublayers. A conductive connection is formed between the via holes stacked one above another in each oxide sub-layer. In FIG. 3 , the second oxide layer 140 may include three stacked oxide sub-layers (140-1, 140-2, 140-3), and the plurality of through holes 11 formed in the second oxide layer 140 may be formed from three stacked oxide sub-layers. It is composed of three layers of sub-vias (11-1, 11-2, 11-3) respectively formed in the oxide sub-layers (140-1, 140-2, 140-3). Of course, in another example, the plurality of vias 11 formed in the second oxide layer 140 may be composed of sub-vias 11-1, metal connection layer 1, sub-vias 11-2, metal connection layer 2, sub-vias It is composed of holes 11-3, and the arrangement and order of the sub-vias and metal connection layers are not limited here.

In step S904, a plurality of second conductive lines respectively connected to one or more through holes are formed on the second oxide layer, so that the plurality of first conductive lines, the plurality of through holes and the The plurality of second conductive lines together form a spirally connected conductive structure.

Referring to FIG. 2 , a plurality of second conductive lines 150 may be formed on the second oxide layer 140 and connected to one or more through holes 11 respectively. The plurality of second conductive lines 150 may pass through the second oxide layer 140 . The multiple metal lines obtained by etching the metal layer deposited on 140 may be formed in the same or different manner as the aforementioned first conductive lines 130 . Optionally, the plurality of second conductive lines 150 may also be arranged along a specific direction in the second oxide layer 140 , and may be arranged in the same or different manner as the first conductive lines 130 . In one example, the specific direction may be a straight line direction parallel to the substrate 110 . That is to say, the plurality of second conductive lines 150 may be arranged one by one along a straight line direction parallel to the substrate 110 . Multiple metal threads for cloth. In another example, the specific direction may also be a ring-shaped, arc-shaped or sector-shaped direction parallel to the substrate 110. That is to say, the plurality of second conductive lines 150 may be in a direction parallel to the substrate 110. A plurality of metal lines are arranged one by one in the circular, arc or fan-shaped direction of the bottom 110 . In addition, optionally, the plurality of second conductive lines 150 may also be parallel to each other. For example, the plurality of second conductive lines 150 may be arranged in parallel one by one along a straight line direction parallel to the substrate 110 . of multiple metal wires. The above-mentioned arrangement directions and arrangements of the second conductive lines 150 are only examples. In practical applications, different arrangement directions and arrangements of the second conductive lines 150 can be designed according to the specific requirements of the spirally connected conductive structure. There are no restrictions here.

In an example of the present disclosure, optionally, the plurality of first conductive lines, the plurality of through holes, and the plurality of second conductive lines together form a spirally connected conductive structure, which may include as shown in Figure 2 One spirally connected conductive structure, that is, a coil; it may also include multiple spirally connected and mutually nested conductive structures, that is, multiple coils, and there may be no electrical connection between the multiple conductive structures. 4 shows an example of a double-layer conductive structure that is spirally connected and nested in each other (ie, two coils are nested in each other) according to one embodiment of the present disclosure. As shown in FIG. 4 , the spirally connected and mutually nested double-layer conductive structure formed on the substrate 110 may include two coils, respectively C1 and C2, where the respective metal lines of C1 and C2 are arranged approximately parallel, and There is no electrical connection between C1 and C2. FIG. 5 shows an example of a three-layer conductive structure that is spirally connected and nested with each other (ie, three coils are nested with each other) according to one embodiment of the present disclosure. As shown in Figure 5, in the lining The spirally connected and mutually nested three-layer conductive structure formed on the bottom 110 may include three coils, namely C1, C2 and C3, wherein the respective metal wire arrangements of C1, C2 and C3 are all approximately parallel, and C1, C2 There is no electrical connection to C3. The above design and arrangement of multiple conductive structures that are spirally connected and nested with each other are only examples. In actual applications, multiple separate or nested conductive structures can be designed according to various scene requirements. The method is not limited here.

According to an embodiment of the present disclosure, the method may further include: forming an insulating layer on the second oxide layer and/or the plurality of second conductive lines; and/or forming an insulating layer electrically connected to the spirally connected conductive structure. One or more third conductive lines, the spirally connected conductive structure and the one or more third conductive lines constitute at least a part of the semiconductor device. In this embodiment, after the semiconductor back-end process is completed, the spirally connected conductive structure can be covered with an insulating layer to form a through hole and connect one or more third conductive lines obtained by subsequent etching of the metal layer deposited. The one or more third conductive lines are used to connect the remaining components of the semiconductor device to prepare different semiconductor devices according to actual needs using the spirally connected conductive structures.

The above discloses an example of a method for preparing a spirally connected conductive structure composed of a plurality of first conductive lines, a plurality of through holes, and a plurality of second conductive lines according to an embodiment of the present disclosure. In practical applications, various improvements or deformations can be made to the spirally connected conductive structure, and these improvements and deformations are also within the scope of the present disclosure. In practical applications, various designs can be made for the axis direction of the spirally connected conductive structure according to the application scenario. Figure 6 shows various examples of the direction of the axis OO' of the spirally connected conductive structure according to one embodiment of the present disclosure. picture. As shown in FIG. 6 , the axis OO′ of the spirally connected conductive structure does not have to be strictly parallel to the substrate 110 , but may be at a certain angle relative to the substrate, or extend approximately parallel to the substrate 110 in a curved manner. Yes, there is no restriction here. Furthermore, FIG. 7 shows examples of various top views of the axis OO' of the spirally connected conductive structure according to one embodiment of the present disclosure. As shown in Figure 7, the axis OO' of the spirally connected conductive structure can also be a fully closed or semi-closed structure, such as a closed or semi-closed arc, circle, square, triangle, ellipse, pentagon Or various irregular patterns, etc., so that the spirally connected conductive structure correspondingly forms a surrounding or semi-circling coil, so that the magnetic field lines can form a closed or semi-closed loop in the direction parallel to the substrate according to the design to adapt to different application scenarios needs.

In addition, in practical applications, the conductive lines and through-holes of the spirally connected conductive structure can also be designed according to the Various designs are applied to the application scenarios, and FIG. 8 shows another example of a spirally connected conductive structure according to an embodiment of the present disclosure. As shown in FIG. 8 , the conductive lines and through holes that make up the spirally connected conductive structure may not be strictly parallel or perpendicular to the substrate 110 , nor may they be strictly straight lines, but may be designed in various ways according to the needs of the actual scenario, and Flexibly arrange the extension direction and arrangement order of each first conductive line, second conductive line, through hole (sub-via hole, metal connection layer), etc., as long as it can form a connected and conductive spiral structure, there is no limit here .

The above shows a method for preparing a semiconductor structure according to an embodiment of the present disclosure. This method can provide a coil structure whose axis is approximately parallel to the surface of the substrate, so as to flexibly control the direction and distribution trend of the magnetic lines of force on the substrate, and obtain high magnetic flux. semiconductor devices. According to the preparation method of a semiconductor structure according to the embodiment of the present disclosure, a corresponding physical model can be generated through the modulation parameters of multiple dimensions of the coil structure, and semiconductor devices with various spatial geometric structures can be flexibly and conveniently manufactured according to the needs of practical applications. , improve design efficiency and device performance, and adapt to different application scenarios.

The above provides a semiconductor structure and a preparation method of the semiconductor structure according to embodiments of the present disclosure. After the above-mentioned semiconductor structure is prepared, the prepared semiconductor structure can also be used to manufacture semiconductor devices with various specific uses. According to an embodiment of the present disclosure, a semiconductor device is also provided, including the semiconductor structure described in any of the above examples. Alternatively, the semiconductor device according to the embodiment of the present disclosure may be at least one of an energy conversion device, an energy storage device, a current measurement device, a voltage conversion device, an isolation communication device, or any combination thereof.

Optionally, various parameters of the spirally connected conductive structures constituting the semiconductor structure may be determined according to the type and/or parameters of the semiconductor device. For example, the parameters of the spirally connected conductive structure, that is, the coil parameters, may include at least one of the following: the coil size of the spirally connected conductive structure; the axial length and/or shape of the spirally connected conductive structure; and the number of turns of the helically connected conductive structure.

Different from the two-dimensional coil structure prepared on the substrate surface in the prior art, the semiconductor structure according to the embodiment of the present disclosure is a three-dimensional coil structure. Therefore, in the embodiments of the present disclosure, not only the size and number of turns of the coil can be adjusted, but also the length and/or the topology of the shape in the axial direction can be adjusted to adapt to the needs of semiconductor devices of different application types.

Alternatively, the semiconductor structure according to the embodiment of the present disclosure can form a physical structure with quasi-four-dimensional parameters represented by MODEL Inductance (Lx, Ly, Ts, n), where "MODEL" represents "model" and "Inductance" represents " Coil model type", Lx and Ly respectively represent the width and height of a single turn coil in a spirally connected conductive structure (as shown in Figure 2), Ts represents the topology of the axial structure of the coil (as shown in Figure 7), n Represents the number of turns in the coil.

In actual applications, the above parameters can be arbitrarily set according to the needs of the application scenario. Optionally, according to the actual product requirements of semiconductor integrated circuits, the value range of the above parameters can be: Lx = 0.1 ~ 10mm (can be consistent with the size of the chip and integrated inside the chip), Ly = 10 ^-8 ~ 10 ^-7 m, Ts can be topological structure description parameters (for example, it can be expressed as Ts = (A 0.5mm), where A represents the topology (shape) of the axial structure of the coil, which is a circle, and 0.5mm represents the axial direction of the coil. The radius of the circle formed by the structure is 0.5mm), and n can range from 1 to 1000.

The values of the above parameters are only examples. In actual applications, any relevant parameters can also be used to represent various properties of the semiconductor structure. For example, when the shape of the single-turn coil of the semiconductor structure is not square or rectangular, but approximately arc-shaped, circular or elliptical, the parameters Lx and Ly can be used to represent the width and height of the single-turn coil instead of using a circle. The shape radius R and radian θ, or the major and minor axes a and b of the ellipse are used to represent the parameters of the semiconductor structure, which are not limited here. During the manufacturing process of semiconductor devices, various flexibly selectable and adjusted parameters of the above-mentioned semiconductor structures can be made.

This semiconductor structure can be used to produce semiconductor devices for various purposes. For example, the semiconductor structure can be used as an energy conversion and storage device and applied in semiconductor devices. When the number of turns of the semiconductor structure coil is n and the AC or DC current passing through the coil is I, the magnetic field B in the coil can be expressed as: B = μnI, where μ is the magnetic permeability of the magnetic material in the coil. Therefore, the energy E stored in the coil can be expressed as: where V is the volume inside the coil.

According to the above principle, the coil of the semiconductor structure can be used as an energy conversion device or an energy storage device to achieve various corresponding functions.

Figure 12 shows a schematic diagram of an energy conversion device according to one embodiment of the present disclosure. As shown in Figure 12, on-chip DC-DC conversion can be achieved. Among them, Vsupply is the input voltage, and Vout is the output voltage. According to the circuit shown in Figure 12, the required output voltage Vout (for example, constant Vout) can be obtained. The basic working principle of the circuit shown in Figure 12 is to feed back the output voltage Vout to the control circuit, so that the control circuit achieves a stable Vout output by controlling the switches of the two MOS tubes on both sides of the coil of the semiconductor structure. Specifically, at time t1, the control circuit can control the MOS transistor switch M1 to turn on and the MOS transistor switch M2 to turn off. At this time, the input voltage Vsupply charges the coil of the semiconductor structure in the present disclosure. After charging to a certain level, time t2 is reached. At this time, the control circuit controls the switch M1 to close and the switch M2 to open. The coil of the semiconductor structure charges the capacitor C to form the output voltage Vout. The control circuit can perform voltage detection on the output voltage Vout. Subsequently, when the control circuit detects that the output voltage Vout reaches a certain set value, the switch M2 can be controlled to close again and the switch M1 can be opened to charge the coil of the semiconductor structure. At this time, the capacitor C can be responsible for providing the output voltage Vout to the outside.

In the process of the capacitor C providing the output voltage Vout, when the control circuit detects that Vout is lower than Vout-dV (dV here can be set according to the application requirements and circuit functions of the device to be provided), the control circuit will The switch M1 is closed again, and the switch M2 is opened to control the stable output of the output voltage Vout. This circuit can enter a stable working state through the above control circuit control and cycle process to achieve a stable Vout output.

Figure 13 shows a schematic diagram of an energy storage device according to one embodiment of the present disclosure. As shown in Figure 13, when the electromagnetic field passes through the coil of the semiconductor structure in the circuit, a current will be generated in the coil. The generated current can obtain the Vout voltage through the circuit shown in Figure 13. The obtained Vout voltage can be used for Other electrical equipment provides electrical energy.

Specifically, under the action of the electromagnetic field in the direction shown in Figure 13, the electromagnetic field can charge the coil of the semiconductor structure, thereby forming a forward voltage in the coil. In the circuit shown in Figure 13, the semiconductor structure The coil can simultaneously charge the capacitor C through the diode D to obtain the output voltage Vout. In addition, after the electromagnetic field in the direction shown in Figure 13 is reversed, under the action of the reverse electromagnetic field, a reverse voltage opposite to the previous forward voltage is formed in the coil, then the diode D is turned off, and the output voltage Vout will remains consistent as forward voltage. As mentioned above, under the action of the spatially alternating electromagnetic field, the capacitor C will be charged half of the time. Considering that the capacitor C has the ability to store electrical energy, it can be ensured that the circuit shown in Figure 13 can provide a more stable positive voltage. output to voltage Vout.

In another example, the coil of the semiconductor structure can also be applied to a current measuring device. Figure 14 shows a schematic diagram of a current measurement device according to one embodiment of the present disclosure. As shown in Figure 14, when an energized wire with current flowing through it is placed near the coil of the semiconductor structure, when the wire passes the current I, due to electromagnetic induction, an electric current will be generated in the coil of the semiconductor structure along the axis of the coil. Magnetic field B in the direction OO'. The change in the intensity of the magnetic field B will act on the coil, causing a corresponding induced current I _C to be generated in the coil. Thus, by measuring the induced current I _C in the coil, the change in the intensity of the magnetic field B can be reflected, and the current I through the wire can be measured accordingly. The placement of the wires shown in FIG. 14 is only an example. For example, the wires can be located on the upper part of the coil as shown in FIG. 14 or on the lower part of the coil (or substrate). Examples of current measurement devices according to the present disclosure can perform current measurements without introducing additional components into the circuit under test.

In yet another example, the coil of the semiconductor structure can also be applied to a voltage conversion device. Figure 15 shows a schematic diagram of a voltage conversion device according to one embodiment of the present disclosure. In the voltage conversion device shown in FIG. 15, a structure in which two coils (an input coil and an output coil) in a semiconductor structure are nested in each other is used. As shown in Figure 15, Vin(f) on both sides of one input coil is used as the input AC voltage, and Vout(f) on both sides of the other output coil is used as the output AC voltage. If the number of turns of the input coil is n and the number of turns of the output coil is m, the output voltage can be expressed as; Voltage conversion is achieved with a structure nested through multiple coils. The structure of the voltage conversion device shown in Figure 15 above is only an example. In actual applications, different coil nesting methods and different coil nesting numbers can also be used to achieve flexible voltage conversion effects.

In yet another example, the coil of the semiconductor structure can also be applied to isolated communication devices. In many applications, signals need to be measured and collected in a relatively high-voltage environment, and then transmitted to relatively low-voltage circuits for processing. Traditional electrical connections may affect the reliability of low-voltage circuits and greatly increase system costs. In the embodiment of the present disclosure, the coupling coil can be formed by a structure in which two coils are nested in each other in the above semiconductor structure, so that the signal can be transmitted between the high-voltage circuit and the low-voltage circuit while the two coils are electrically isolated. Free transmission between devices to achieve high and low voltage isolation on a single chip and reduce system costs. In addition, it can also provide better system reliability and stability than optical isolation and capacitive isolation. Figure 16 shows a schematic diagram of an isolated communication device according to one embodiment of the present disclosure. In the isolated communication device shown in Figure 16, Vin is the input signal. Vout can be obtained through the coupling coil formed by two coils nested in each other. Then, Vin can be restored at the output end through the recovery circuit "Recover Circuit" to achieve Signal communication under electrical isolation.

In this example, the communication signal may be an alternating signal. Specifically, the alternating input signal Vin can be generated by a coupling coil formed by two coils nested in each other to generate the alternating output signal Vout. Here, the waveform of Vout may be different from Vin. Therefore, in this case, it is necessary to restore the The waveform of Vout returns to Vin. In the case of different Vin waveforms, the specific recovery process can be;

1. If Vin is a sinusoidal waveform, Vout can also be a sinusoidal waveform, but may have different amplitude changes. At this time, the recovery circuit can provide a simple amplification current to restore Vout to the required amplitude value.

2. If Vin is a square wave waveform, Vout will become a pulse waveform, and its pulses appear at the rising and falling edges of the square wave waveform. At this time, the recovery circuit will restore the pulse waveform to a square waveform.

3. If Vin is another form of waveform, it can be transformed into a combination of sinusoidal waveform and square waveform through waveform transformation (such as Fourier transform, etc.), and can be restored through the corresponding combination of the above two waveform recovery methods 1 and 2. The waveform of Vout returns to the waveform of Vin, and at the same time returns to the required amplitude value.

The application of the semiconductor structure and the specific structure of the device in Figures 12 to 16 above are examples. In actual applications, the semiconductor structure can also be applied to various semiconductor devices and chip structures according to specific scene requirements. There are no restrictions here.

Various changes, substitutions and alterations to the technology herein may be made without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of the present disclosure is not limited to the specific aspects of the process, machine, manufacture, composition of events, means, methods and acts described above. A currently existing or later developed process, machine, manufacture, composition of events, means, method, or act may be utilized that performs substantially the same function or achieves substantially the same results as in its respective aspects herein. Accordingly, the appended claims include within their scope such processes, machines, manufacture, compositions of events, means, methods or acts.

The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for the purposes of illustration and description. Furthermore, this description is not intended to limit the disclosed embodiments to the form disclosed herein. Although various example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Industrial applicability

The present disclosure provides a semiconductor structure, a preparation method of the semiconductor structure, and a semiconductor device, which can provide a coil structure with an axis approximately parallel to the substrate surface, so as to flexibly control the direction and distribution trend of magnetic lines of force on the substrate, and obtain high magnetic flux semiconductors. device to improve design efficiency and device performance, and has strong industrial practicality.

Claims

A semiconductor structure including:

substrate;

A first oxide layer is formed on the substrate;

A plurality of first conductive lines are formed on the first oxide layer and arranged along a specific direction;

A second oxide layer is formed on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer so that the plurality of first conductive lines are Both ends of each first conductive line are respectively connected to a through hole, and the through hole is filled with conductive material; and

A plurality of second conductive lines are formed on the second oxide layer and are respectively connected to one or more through holes, so that the plurality of first conductive lines, the plurality of through holes and the plurality of third The two conductive lines together form a spirally connected conductive structure.
The semiconductor structure of claim 1, wherein an axis direction of the spirally connected conductive structure is parallel to the substrate.
The semiconductor structure of claim 1, wherein the specific direction is a straight line, annular, arc or sector direction parallel to the substrate.
The semiconductor structure of claim 1, wherein the second oxide layer includes a plurality of stacked oxide sub-layers, and a plurality of sub-vias in the plurality of oxide sub-layers respectively penetrate up and down to form the second oxide layer. At least a portion of the plurality of vias in the layer.
The semiconductor structure of claim 1, wherein

The plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines together form a plurality of conductive structures that are spirally connected and nested with each other, and there is no electrical connection between the plurality of conductive structures. .
The semiconductor structure of claim 1, wherein

The first conductive line is made of polysilicon material.
The semiconductor structure of claim 1, wherein

The semiconductor structure further includes: an insulating layer formed on the second oxide layer and/or a plurality of second conductive lines; and/or

One or more third conductive lines are electrically connected to the spirally connected conductive structure, so that the spirally connected conductive structure and the one or more third conductive lines form at least a part of the semiconductor device.
A method for preparing a semiconductor structure, including:

forming a first oxide layer on the substrate;

forming a plurality of first conductive lines arranged along a specific direction on the first oxide layer;

A second oxide layer is formed on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer such that a plurality of first conductive lines are Both ends of each first conductive line are respectively connected to a through hole, and the through hole is filled with conductive material; and

A plurality of second conductive lines respectively connected to one or more through holes are formed on the second oxide layer, so that the plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines are formed on the second oxide layer. The conductive threads together form a spirally connected conductive structure.
A semiconductor device comprising the semiconductor structure according to any one of claims 1-7.
The semiconductor device according to claim 9, wherein the semiconductor device is:

At least one of energy conversion devices, energy storage devices, current measurement devices, voltage conversion devices, isolation communication devices or any combination thereof.