CN115331927A - Semiconductor structure, preparation method and semiconductor device - Google Patents
Semiconductor structure, preparation method and semiconductor device Download PDFInfo
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- CN115331927A CN115331927A CN202210974331.XA CN202210974331A CN115331927A CN 115331927 A CN115331927 A CN 115331927A CN 202210974331 A CN202210974331 A CN 202210974331A CN 115331927 A CN115331927 A CN 115331927A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/29—Terminals; Tapping arrangements for signal inductances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
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Abstract
The embodiment of the disclosure provides a semiconductor structure, a preparation method of the semiconductor structure and a semiconductor device. The semiconductor structure according to an embodiment of the present disclosure includes: a substrate; a first oxide layer formed on the substrate; a plurality of first conductive lines formed on the first oxide layer and arranged along a specific direction; a second oxide layer formed on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer, so that two ends of each of the plurality of first conductive lines are respectively connected with one through hole, and the through holes are filled with conductive materials; and a plurality of second conductive lines formed on the second oxide layer and respectively connected with one or more through holes, so that the plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines jointly form a spiral-connected conductive structure.
Description
Technical Field
Embodiments of the present disclosure relate to the field of electronic devices, and in particular, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a semiconductor device.
Background
In substrate-based semiconductors and related processes, inductive coils have been widely used, for example, in wireless chip applications, different shapes of coils can be designed using metal wires in semiconductor processes for receiving wireless signals. However, these structures currently use a coil structure with an axis OO' perpendicular to the substrate surface as shown in fig. 1.
However, the coil structure shown in fig. 1, in which the axis is perpendicular to the substrate surface, has low adaptability, cannot meet the requirements of flexible device design and application, and increases the cost of the system. Therefore, there is a need for a semiconductor structure and a method of fabricating a semiconductor structure, and a semiconductor device, with flexible spatial geometry and modulation parameters to meet various corresponding requirements for diverse device designs and applications.
Disclosure of Invention
To solve the above technical problem, according to an aspect of the present disclosure, there is provided a semiconductor structure including: a substrate; a first oxide layer formed on the substrate; a plurality of first conductive lines formed on the first oxide layer and arranged in a specific direction; a second oxide layer formed on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer, so that two ends of each of the plurality of first conductive lines are respectively connected with one through hole, and the through holes are filled with conductive materials; and a plurality of second conductive lines formed on the second oxide layer and respectively connected with one or more through holes, so that the plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines together form a spirally connected conductive structure.
According to some embodiments of the disclosure, an axial direction of the spiral connected conductive structure is parallel to the substrate.
According to some embodiments of the present disclosure, wherein the specific direction is a linear direction parallel to the substrate.
According to some embodiments of the present disclosure, wherein the plurality of first conductive lines are parallel to each other.
According to some embodiments of the present disclosure, wherein the plurality of second conductive lines are parallel to each other.
According to some embodiments of the present disclosure, wherein the specific direction is a circular, arc or fan direction parallel to the substrate.
According to some embodiments of the present disclosure, the second oxide layer includes a plurality of oxide sub-layers stacked, and a plurality of sub-vias of the plurality of oxide sub-layers respectively pass through up and down to constitute at least a portion of the plurality of vias of the second oxide layer.
According to some embodiments of the present disclosure, one end of one second conductive line is connected to the via connected to one first conductive line, and the other end is connected to the via connected to another first conductive line, so that the plurality of first conductive lines, the plurality of vias, and the plurality of second conductive lines collectively constitute a spiral-connected conductive structure.
According to some embodiments of the present disclosure, the plurality of first conductive lines, the plurality of vias and the plurality of second conductive lines together form a plurality of conductive structures that are spirally connected and nested with each other, and the plurality of conductive structures do not have electrical connection therebetween.
According to some embodiments of the present disclosure, wherein the first conductive line is comprised of a polysilicon material.
According to some embodiments of the present disclosure, wherein the semiconductor structure further comprises: an insulating layer formed on the second oxide layer and/or the plurality of second conductive lines; and/or one or more third conductive lines electrically connected to the spiral-connected conductive structure such that the spiral-connected conductive structure and the one or more third conductive lines constitute at least a portion of a semiconductor device.
According to another aspect of the present disclosure, there is provided a method of fabricating a semiconductor structure, including: forming a first oxide layer on a substrate; forming a plurality of first conductive lines arranged along a specific direction on the first oxide layer; forming a second oxide layer on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer, so that two ends of each of the plurality of first conductive lines are respectively connected with one through hole, and the through holes are filled with conductive materials; and forming a plurality of second conductive lines respectively connected with one or more through holes on the second oxide layer, so that the plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines jointly form a spiral-connected conductive structure.
According to some embodiments of the present disclosure, wherein an axial direction of the spiral connected conductive structure is parallel to the substrate.
According to some embodiments of the present disclosure, wherein the specific direction is a linear direction parallel to the substrate.
According to some embodiments of the present disclosure, wherein the plurality of first conductive lines are parallel to each other.
According to some embodiments of the present disclosure, wherein the plurality of second conductive lines are parallel to each other.
According to some embodiments of the present disclosure, wherein the specific direction is a circular, arc or fan direction parallel to the substrate.
According to some embodiments of the present disclosure, wherein forming a second oxide layer on the first oxide layer and the plurality of first conductive lines comprises: and forming a plurality of stacked oxide sub-layers on the first oxide layer and the plurality of first conductive lines respectively to form the second oxide layer, forming a plurality of sub-through holes in the plurality of oxide sub-layers respectively, wherein the plurality of sub-through holes are communicated up and down respectively to form at least one part of the plurality of through holes in the second oxide layer.
According to some embodiments of the present disclosure, one end of one second conductive line is connected to the via connected to one first conductive line, and the other end is connected to the via connected to another first conductive line, so that the plurality of first conductive lines, the plurality of vias, and the plurality of second conductive lines collectively constitute a spiral-connected conductive structure.
According to some embodiments of the present disclosure, the plurality of first conductive lines, the plurality of vias and the plurality of second conductive lines together form a plurality of conductive structures that are spirally connected and nested with each other, and the plurality of conductive structures do not have electrical connection therebetween.
According to some embodiments of the present disclosure, wherein the first conductive line is comprised of a polysilicon material.
According to some embodiments of the disclosure, wherein the method further comprises: forming an insulating layer on the second oxide layer and/or the plurality of second conductive lines; and/or forming one or more third conductive lines electrically connected to the spiral-connected conductive structure, the spiral-connected conductive structure and the one or more third conductive lines constituting at least a portion of a semiconductor device.
According to yet another aspect of the present disclosure, there is provided a semiconductor device comprising the semiconductor structure as defined in any one of the above.
According to some embodiments of the present disclosure, wherein the semiconductor device is: at least one of an energy conversion device, an energy storage device, a current measurement device, a voltage conversion device, an isolated communication device, or any combination thereof.
According to some embodiments of the present disclosure, wherein a parameter of a conductive structure of the spiral connection constituting the semiconductor structure is determined according to a type and/or a parameter of the semiconductor device.
According to some embodiments of the disclosure, the parameters of the spiral connected conductive structure comprise at least one of: the coil size of the spiral connected conductive structure; the axial length and/or shape of the helically connected conductive structure; and the number of turns of the spirally connected conductive structure.
According to the semiconductor structure, the preparation method of the semiconductor structure and the semiconductor device, which are provided by the embodiment of the disclosure, the coil structure with the axis approximately parallel to the surface of the substrate can be provided, so that the trend and the distribution trend of the magnetic force lines on the substrate can be flexibly controlled, and the semiconductor device with high magnetic flux can be obtained. According to the semiconductor structure, the preparation method of the semiconductor structure and the semiconductor device, the corresponding physical model can be generated through the modulation parameters of multiple dimensions of the coil structure, the semiconductor device with various different space geometric structures can be flexibly and conveniently manufactured according to the requirements of practical application, the design efficiency and the device performance are improved, and different application scenes are adapted.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments of the present disclosure will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 illustrates a prior art coil structure with axis OO' perpendicular to the substrate surface;
FIG. 2 illustrates a schematic structural diagram of a semiconductor structure, according to one embodiment of the present disclosure;
FIG. 3 illustrates a schematic structural diagram of a semiconductor structure, according to one embodiment of the present disclosure;
FIG. 4 illustrates an example of a spiral connected and nested double layer conductive structure according to one embodiment of the present disclosure;
FIG. 5 illustrates an example of a spiral connected and nested three-layer conductive structure according to one embodiment of the present disclosure;
FIG. 6 illustrates various exemplary views of the orientation of the axis OO' of the spiral connected conductive structure according to one embodiment of the present disclosure;
FIG. 7 illustrates examples of various top views of the axis OO' of the spiral connected conductive structure according to one embodiment of the present disclosure;
FIG. 8 illustrates another example of a spiral connected conductive structure according to one embodiment of the present disclosure;
FIG. 9 shows a flow chart of a method of fabricating a semiconductor structure according to one embodiment of the present disclosure;
FIG. 10 shows a schematic diagram of forming a first oxide layer on a substrate and fabricating a plurality of first conductive lines, according to one embodiment of the present disclosure;
fig. 11 illustrates a schematic diagram of forming a second oxide layer on a first oxide layer and forming a via according to one embodiment of the present disclosure;
FIG. 12 shows a schematic diagram of an energy conversion device according to an embodiment of the present disclosure;
FIG. 13 shows a schematic diagram of an energy storage device according to an embodiment of the present disclosure;
FIG. 14 shows a schematic diagram of a current measurement device according to one embodiment of the present disclosure;
FIG. 15 shows a schematic diagram of a voltage conversion device according to one embodiment of the present disclosure;
fig. 16 shows a schematic diagram of an isolated communication device according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly. To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components have been omitted from the present disclosure.
Flow charts are used in this disclosure to illustrate steps of methods according to embodiments of the disclosure. It should be understood that the preceding or subsequent steps need not be performed in the exact order shown. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to the processes, or a certain step or steps may be removed from the processes.
In semiconductor related processes, when a coil structure with an axis OO' perpendicular to the substrate surface is used, one or more of the following disadvantages may result:
(1) The coil structure is essentially a coil structure adopting a two-dimensional geometric space structure, has low structural adaptability and cannot meet the requirements of flexible and various device designs and applications.
(2) The coil structure has more magnetic energy loss and difficult device design. Specifically, when a coil structure with an axis perpendicular to the substrate is adopted, the magnetic lines of force of the coil structure are perpendicular to the substrate, and most of the magnetic lines of force of the coil structure are distributed outside the device, so that more magnetic energy loss occurs, the coil structure with high magnetic flux is difficult to realize, and the Q factor is difficult to flexibly adjust and promote. In addition, the magnetic lines of force of this coil structure are arranged the mode comparatively complicated, lead to the magnetic signal to this structure to calculate, handle the difficulty.
(3) The number of turns of the coil structure is limited. In the manufacturing process of a semiconductor process based on a substrate, the two-dimensional geometrical space structure causes that the number of turns of a coil in the coil structure is limited, the coil with the same size and more turns is difficult to design and manufacture, and the requirements of a multi-coil structure and a mutual inductor structure with a more complex structure are difficult to meet.
Based on the above disadvantages, the application of the semiconductor device formed of the coil structure perpendicular to the substrate surface is limited, and the design and manufacturing costs of the semiconductor device are increased.
Accordingly, it is desirable to provide a semiconductor structure and a method of fabricating a semiconductor structure, and a semiconductor device, with flexible spatial geometry and modulation parameters to meet various corresponding requirements for diverse device designs and applications.
Fig. 2 shows a schematic structural diagram of a semiconductor structure 100 according to an embodiment of the present disclosure.
As shown in fig. 2, the semiconductor structure 100 includes a substrate 110, a first oxide layer 120, a first conductive line 130, a second oxide layer 140, and a second conductive line 150. Wherein a first oxide layer 120 is formed on the substrate 110; a plurality of first conductive lines 130 formed on the first oxide layer 120 and arranged in a specific direction; a second oxide layer 140 formed on the first oxide layer 120 and the plurality of first conductive lines 130, wherein a plurality of through holes 11 are formed in the second oxide layer 140, such that two ends of each first conductive line 130 of the plurality of first conductive lines 130 are respectively connected to one through hole 11, and the through holes 11 are filled with a conductive material; the second conductive lines 150 are formed on the second oxide layer 140 and are respectively connected to one or more through holes 11, such that the first conductive lines 130, the through holes 11, and the second conductive lines 150 together form a spiral-connected conductive structure. Alternatively, the axial direction of the spiral-connected conductive structure may be parallel or substantially parallel to the substrate.
In the conductive structure of the spiral connection shown in fig. 2, the substrate 110 may be a semiconductor substrate, for example, the substrate 110 may be a silicon substrate. The plurality of first conductive lines 130 formed on the first oxide layer 120 on the substrate 110 may be a plurality of metal lines etched from a metal layer deposited on the first oxide layer 120. Alternatively, the plurality of first conductive lines 130 may be arranged in a specific direction. In one example, the specific direction may be a linear direction parallel to the substrate 110, that is, the plurality of first conductive lines 130 may be a plurality of metal lines arranged one by one in the linear direction parallel to the substrate 110. In another example, the specific direction may be a circular, arc, or fan-shaped direction parallel to the substrate 110, that is, the plurality of first conductive lines 130 may be a plurality of metal lines arranged one by one in the circular, arc, or fan-shaped direction parallel to the substrate 110. In addition, optionally, the plurality of first conductive lines 130 may also be parallel to each other, for example, the plurality of first conductive lines 130 may be a plurality of metal lines arranged in parallel one by one along a straight line direction parallel to the substrate 110. The arrangement direction and the arrangement manner of the first conductive lines 130 are only examples, and in practical applications, the arrangement direction and the arrangement manner of the first conductive lines 130 can be designed differently according to specific requirements of the spiral-connected conductive structure, which is not limited herein.
After the formation of the plurality of first conductive lines 130, a second oxide layer 140 may be formed on the first oxide layer 120 and the plurality of first conductive lines 130, wherein the second oxide layer 140 may include a stacked plurality of oxide sublayers (140-1, 140-2 \8230; and the plurality of via holes 11 formed in the second oxide layer 140 may be combined by a plurality of sub-via holes (11-1, 11-2 \8230; and) formed in the plurality of oxide sublayers (140-1, 140-2 \8230). Wherein, the multi-layer sub-through holes (11-1, 11-2 \8230;) are respectively penetrated up and down to combine into at least one part of the plurality of through holes 11 in the second oxide layer 140. In addition, optionally, between any adjacent oxide sublayers in the plurality of oxide sublayers (140-1, 140-2 \8230;), one or more metal connecting layers (not shown in the figure) can be formed according to needs, and the one or more metal connecting layers are formed by etching the metal layer deposited between the adjacent oxide sublayers, so that the conductive connection can be formed between the through holes stacked up and down in each oxide sublayer. Fig. 3 illustrates a semiconductor structure according to an embodiment of the present disclosure, wherein, as shown in fig. 3, the second oxide layer 140 may include three oxide sublayers (140-1, 140-2, 140-3) stacked, and the plurality of vias 11 formed in the second oxide layer 140 may be combined by three sub-vias (11-1, 11-2, 11-3) respectively formed in the three oxide sublayers (140-1, 140-2, 140-3). Of course, in another example, the plurality of through holes 11 formed in the second oxide layer 140 may be composed of sub-through holes 11-1, metal connection layers 1,11-2, metal connection layers 2, and 11-3, and the arrangement and sequence of the sub-through holes and the metal connection layers are not limited herein.
Referring back to fig. 2, a plurality of second conductive lines 150 may be formed on the second oxide layer 140 and respectively connected to the one or more through holes 11, and the plurality of second conductive lines 150 may be a plurality of metal lines formed by etching a metal layer deposited on the second oxide layer 140, and may be formed in the same manner as or different from the first conductive lines 130. Alternatively, the plurality of second conductive lines 150 may also be arranged in a specific direction in the second oxide layer 140, and may adopt the same or different arrangement manner as the first conductive lines 130. In one example, the specific direction may be a linear direction parallel to the substrate 110, that is, the plurality of second conductive lines 150 may be a plurality of metal lines arranged one by one in the linear direction parallel to the substrate 110. In another example, the specific direction may also be a circular, arc or fan-shaped direction parallel to the substrate 110, that is, the second conductive lines 150 may be metal lines arranged one by one along the circular, arc or fan-shaped direction parallel to the substrate 110. In addition, optionally, the plurality of second conductive lines 150 may also be parallel to each other, for example, the plurality of second conductive lines 150 may be a plurality of metal lines arranged in parallel one by one along a linear direction parallel to the substrate 110. The arrangement direction and the arrangement manner of the second conductive lines 150 are only examples, and in practical applications, the arrangement direction and the arrangement manner of the second conductive lines 150 may be designed differently according to specific requirements of the spiral-connected conductive structure, which is not limited herein.
Alternatively, as shown in fig. 2, one end of one second conductive line 150 may be connected to one via hole connected to one first conductive line, and the other end may be connected to another via hole connected to another first conductive line, so that the plurality of first conductive lines, the plurality of via holes, and the plurality of second conductive lines collectively constitute a spiral-connected conductive structure.
In one example of the present disclosure, optionally, the conductive structures in which the plurality of first conductive lines, the plurality of vias, and the plurality of second conductive lines collectively form a spiral connection may include one spiral-connected conductive structure, i.e., one coil, as shown in fig. 2; a plurality of conductive structures, i.e. a plurality of coils, which are spirally connected and nested within each other may also be included, and there may be no electrical connection between the plurality of conductive structures. Figure 4 illustrates an example of a spiral connected and nested double layer conductive structure (i.e., two coils nested within each other) according to one embodiment of the present disclosure. As shown in fig. 4, the spirally connected and nested double-layer conductive structure formed on the substrate 110 may include two coils, respectively C1 and C2, in which the respective metal line rows of C1 and C2 are approximately parallel and there is no electrical connection between C1 and C2. Figure 5 illustrates an example of a spiral connected and nested three-layer conductive structure (i.e., three coils nested within each other) according to one embodiment of the present disclosure. As shown in fig. 5, the spiral-connected and nested three-layer conductive structure formed on the substrate 110 may include three coils, respectively C1, C2 and C3, wherein the metal lines of C1, C2 and C3 are arranged approximately in parallel, and there is no electrical connection between C1, C2 and C3. The above design and arrangement manner of the plurality of conductive structures that are spirally connected and nested with each other is only an example, and in practical application, various manners of separating or nesting the plurality of different conductive structures may be designed according to various different scene requirements, which is not limited herein.
Optionally, at least one of the first conductive line, the via, and the second conductive line may be composed of a metal material; further optionally, at least one of the first conductive line, the via, and the second conductive line may be comprised of a polysilicon material. For example, the first conductive line may be etched from a polysilicon layer formed on an oxide layer on the substrate. The above selection manner of the materials of the first conductive line, the through hole, and the second conductive line is only an example, and in practical applications, different preparation materials may be selected for the first conductive line, the through hole, and the second conductive line according to various different scene requirements, which is not limited herein.
According to one embodiment of the present disclosure, various electronic components (e.g., chips, etc.) may be first fabricated within the substrate, and then the semiconductor structure as described in the present disclosure may be fabricated on the substrate to be electrically connected with the electronic components fabricated within the substrate and controlled by the semiconductor structure and the semiconductor devices formed thereby, etc.
According to an embodiment of the present disclosure, the semiconductor structure may further include: an insulating layer formed on the second oxide layer and/or the plurality of second conductive lines; and/or one or more third conductive lines electrically connected to the spirally connected conductive structure, the spirally connected conductive structure and the one or more third conductive lines constituting at least a portion of a semiconductor device. In this embodiment, after the semiconductor back-end process is completed, an insulating layer may be covered on the conductive structure of the spiral connection, a through hole is formed and connected to one or more third conductive lines obtained by etching a metal layer deposited subsequently, and the remaining parts of the semiconductor device are connected through the one or more third conductive lines, so as to prepare different semiconductor devices by using the conductive structure of the spiral connection according to actual needs.
An example of a basic structure of a spiral-connected conductive structure constituted by a plurality of first conductive lines, a plurality of vias, and a plurality of second conductive lines in common according to an embodiment of the present disclosure is disclosed above. In practical applications, various modifications or variations can be made to the conductive structure of the spiral connection, and these modifications and variations are also within the scope of the present disclosure. In practical applications, various designs can be made for the axial direction of the spiral-connected conductive structure according to application scenarios, and fig. 6 shows various exemplary diagrams of the direction of the axis OO' of the spiral-connected conductive structure according to one embodiment of the present disclosure. As shown in fig. 6, the axis OO' of the spiral-connected conductive structure may not run exactly parallel to the substrate 110, but may run at an angle relative to the substrate, or may run approximately parallel to the substrate 110 in a curved manner, which is not limited herein. Further, fig. 7 shows examples of various top views of the axis OO' of the spiral-connected conductive structure facing the substrate according to one embodiment of the present disclosure. As shown in fig. 7, the axis OO' of the spirally connected conductive structure may also be a fully or semi-closed structure, such as a closed or semi-closed arc, a circle, a square, a triangle, an ellipse, a pentagon or various irregular figures, so that the spirally connected conductive structure correspondingly forms a surrounding or semi-surrounding coil, so that the magnetic lines of force may form a closed or semi-closed loop line in a direction parallel to the substrate according to a design, so as to meet the requirements of different application scenarios.
In addition, in practical applications, various designs may be made for the conductive lines and the through holes of the spiral-connected conductive structure according to application scenarios, and fig. 8 shows another example of the spiral-connected conductive structure according to an embodiment of the present disclosure. As shown in fig. 8, each conductive line and each through hole constituting the conductive structure of the spiral connection may not be strictly parallel or perpendicular to the substrate 110, or may not be strictly straight, and various designs may be performed according to the requirements of the actual scene, and the extending directions and the arrangement order of each first conductive line, each second conductive line, each through hole (sub-through hole, metal connection layer), and the like are flexibly arranged, as long as the spiral structure of the connected conductive structure can be formed, which is not limited herein.
The semiconductor structure according to the embodiment of the present disclosure is shown above, and the semiconductor structure can provide a coil structure with an axis approximately parallel to the surface of the substrate, so as to flexibly control the trend and distribution of magnetic lines of force on the substrate, and obtain a semiconductor device with high magnetic flux. According to the semiconductor structure disclosed by the embodiment of the disclosure, the corresponding physical model can be generated through the modulation parameters of multiple dimensions of the coil structure, semiconductor devices with various different space geometric structures can be flexibly and conveniently manufactured according to the requirements of practical application, the design efficiency and the device performance are improved, and the semiconductor structure is suitable for different application scenes.
Fig. 9 illustrates a flow chart of a method 900 of fabricating a semiconductor structure in accordance with an embodiment of the present disclosure.
As shown in fig. 9, the method for fabricating the semiconductor structure includes:
step S901: forming a first oxide layer on a substrate;
step S902: forming a plurality of first conductive lines arranged along a specific direction on the first oxide layer;
step S903: forming a second oxide layer on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer, so that two ends of each first conductive line in the plurality of first conductive lines are respectively connected with one through hole, and conductive materials are filled in the through holes;
step S904: and forming a plurality of second conductive lines respectively connected with one or more through holes on the second oxide layer, so that the plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines jointly form a spiral-connected conductive structure.
As shown in fig. 2, the prepared semiconductor structure 100 may include a substrate 110, a first oxide layer 120, a first conductive line 130, a second oxide layer 140, and a second conductive line 150. Wherein a first oxide layer 120 is formed on the substrate 110; a plurality of first conductive lines 130 formed on the first oxide layer 120 and arranged in a specific direction; a second oxide layer 140 formed on the first oxide layer 120 and the plurality of first conductive lines 130, wherein a plurality of through holes 11 are formed in the second oxide layer 140, such that two ends of each first conductive line 130 of the plurality of first conductive lines 130 are respectively connected to one through hole 11, and the through holes 11 are filled with a conductive material; a plurality of second conductive lines 150 are formed on the second oxide layer 140 and are respectively connected to one or more through holes 11, such that the plurality of first conductive lines 130, the plurality of through holes 11, and the plurality of second conductive lines 150 collectively constitute a spiral-connected conductive structure. Alternatively, the axis OO' of the spiral-connected conductive structure may be oriented parallel or substantially parallel to the substrate.
According to the embodiment of the present disclosure, in step S901, a first oxide layer is formed on a substrate.
In the conductive structure of the spiral connection shown in fig. 2, the substrate 110 may be a semiconductor substrate, for example, the substrate 110 may be a silicon substrate.
In step S902, a plurality of first conductive lines arranged in a specific direction are formed on the first oxide layer.
In the conductive structure of the spiral connection shown in fig. 2, the plurality of first conductive lines 130 formed on the first oxide layer 120 on the substrate 110 may be a plurality of metal lines etched from a metal layer deposited on the first oxide layer 120. Alternatively, the plurality of first conductive lines 130 may be arranged in a specific direction. In one example, the specific direction may be a linear direction parallel to the substrate 110, that is, the plurality of first conductive lines 130 may be a plurality of metal lines arranged one by one in the linear direction parallel to the substrate 110. In another example, the specific direction may be a circular, arc, or fan-shaped direction parallel to the substrate 110, that is, the plurality of first conductive lines 130 may be a plurality of metal lines arranged one by one in the circular, arc, or fan-shaped direction parallel to the substrate 110. In addition, optionally, the plurality of first conductive lines 130 may also be parallel to each other, for example, the plurality of first conductive lines 130 may be a plurality of metal lines arranged in parallel one by one along a straight line direction parallel to the substrate 110. The arrangement direction and the arrangement manner of the first conductive lines 130 are only examples, and in practical applications, the arrangement direction and the arrangement manner of the first conductive lines 130 may be designed differently according to specific requirements of the spiral-connected conductive structure, which is not limited herein.
Fig. 10 illustrates a schematic diagram of forming a first oxide layer 120 on a substrate 110 and fabricating a plurality of first conductive lines 130 according to one embodiment of the present disclosure. As shown in fig. 10, after forming a first oxide layer 120 on a substrate 110, a metal layer may be deposited on the first oxide layer 120, and a plurality of first conductive lines 130 may be formed by etching. Alternatively, the plurality of first conductive lines 130 may be a plurality of metal lines arranged one by one in a linear direction parallel to the substrate 110, and the plurality of first conductive lines 130 may also be parallel to each other.
In step S903, a second oxide layer is formed on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer, such that two ends of each of the plurality of first conductive lines are respectively connected to one through hole, and the through holes are filled with a conductive material. Fig. 11 illustrates a schematic diagram of forming a second oxide layer on the first oxide layer and the plurality of first conductive lines and forming a via hole according to one embodiment of the present disclosure. As shown in fig. 11, after forming the plurality of first conductive lines 130, a second oxide layer 140 may be formed on the first oxide layer 120 and the plurality of first conductive lines 130, and a plurality of via holes 11 are fabricated on the second oxide layer 140 and filled with a conductive material so that the via holes 11 can be electrically connected to the first conductive lines 130, respectively.
Alternatively, forming a second oxide layer on the first oxide layer may include: and forming a plurality of stacked oxide sub-layers on the first oxide layer and the plurality of first conductive lines respectively to form the second oxide layer, forming a plurality of sub-through holes in the plurality of oxide sub-layers respectively, wherein the plurality of sub-through holes are communicated up and down respectively to form at least one part of the plurality of through holes in the second oxide layer. Specifically, referring to FIG. 3, the second oxide layer 140 may include a stacked plurality of oxide sublayers (140-1, 140-2 \8230; and the plurality of via holes 11 formed in the second oxide layer 140 may be combined by a plurality of sub-via holes (11-1, 11-2 \8230; and 11-1, 140-2 \8230) formed in the plurality of oxide sublayers (140-1, 140-2 \8230; and the like). Wherein, the multi-layer sub-through holes (11-1, 11-2 \8230;) are respectively penetrated up and down to combine into at least one part of the plurality of through holes 11 in the second oxide layer 140. In addition, optionally, between any adjacent oxide sublayers in the plurality of oxide sublayers (140-1, 140-2 \8230;), one or more metal connecting layers (not shown in the figure) can be formed according to needs, and the one or more metal connecting layers are formed by etching the metal layer deposited between the adjacent oxide sublayers, so that the conductive connection can be formed between the through holes stacked up and down in each oxide sublayer. In fig. 3, the second oxide layer 140 may include three oxide sublayers (140-1, 140-2, 140-3) stacked, and the plurality of through holes 11 formed in the second oxide layer 140 may be combined by three sub-through holes (11-1, 11-2, 11-3) respectively formed in the three oxide sublayers (140-1, 140-2, 140-3). Of course, in another example, the plurality of through holes 11 formed in the second oxide layer 140 may be composed of sub-through holes 11-1, metal connection layers 1,11-2, metal connection layers 2, and 11-3, and the arrangement and sequence of the sub-through holes and the metal connection layers are not limited herein.
In step S904, a plurality of second conductive lines respectively connected to one or more vias are formed on the second oxide layer, such that the plurality of first conductive lines, the plurality of vias, and the plurality of second conductive lines collectively form a spiral-connected conductive structure.
Referring to fig. 2, the plurality of second conductive lines 150 may be formed on the second oxide layer 140 and respectively connected to the one or more through holes 11, and the plurality of second conductive lines 150 may be a plurality of metal lines formed by etching a metal layer deposited on the second oxide layer 140, and may be formed in the same manner as or different from the first conductive lines 130. Alternatively, the plurality of second conductive lines 150 may also be arranged in a specific direction in the second oxide layer 140, and may adopt the same or different arrangement manner as the first conductive lines 130. In one example, the specific direction may be a linear direction parallel to the substrate 110, that is, the plurality of second conductive lines 150 may be a plurality of metal lines arranged one by one in the linear direction parallel to the substrate 110. In another example, the specific direction may also be a circular, arc or fan-shaped direction parallel to the substrate 110, that is, the second conductive lines 150 may be metal lines arranged one by one along the circular, arc or fan-shaped direction parallel to the substrate 110. In addition, optionally, the plurality of second conductive lines 150 may also be parallel to each other, for example, the plurality of second conductive lines 150 may be a plurality of metal lines arranged in parallel one by one along a linear direction parallel to the substrate 110. The arrangement direction and the arrangement manner of the second conductive lines 150 are only examples, and in practical applications, the arrangement direction and the arrangement manner of the second conductive lines 150 may be designed differently according to specific requirements of the spiral-connected conductive structure, which is not limited herein.
Alternatively, as shown in fig. 2, one end of one second conductive line 150 may be connected to one via hole connected to one first conductive line, and the other end may be connected to another via hole connected to another first conductive line, so that the plurality of first conductive lines, the plurality of via holes, and the plurality of second conductive lines collectively constitute a spiral-connected conductive structure.
In one example of the present disclosure, optionally, the conductive structures in which the plurality of first conductive lines, the plurality of vias, and the plurality of second conductive lines collectively form a spiral connection may include one spiral-connected conductive structure, i.e., one coil, as shown in fig. 2; a plurality of conductive structures, i.e. a plurality of coils, which are spirally connected and nested with each other, may also be included, and there may be no electrical connection between the plurality of conductive structures. Figure 4 illustrates an example of a spiral connected and nested double layer conductive structure (i.e., two coils nested within each other) according to one embodiment of the present disclosure. As shown in fig. 4, the spirally connected and nested double-layer conductive structure formed on the substrate 110 may include two coils, respectively C1 and C2, in which the respective metal line rows of C1 and C2 are approximately parallel and there is no electrical connection between C1 and C2. Figure 5 illustrates an example of a spiral connected and nested three-layer conductive structure (i.e., three coils nested within each other) according to one embodiment of the present disclosure. As shown in fig. 5, the spiral-connected and nested three-layer conductive structure formed on the substrate 110 may include three coils, respectively C1, C2 and C3, wherein the metal lines of C1, C2 and C3 are arranged approximately in parallel, and there is no electrical connection between C1, C2 and C3. The above design and arrangement manner of the plurality of conductive structures that are spirally connected and nested with each other is only an example, and in practical applications, various manners of separating or nesting the plurality of conductive structures may be designed according to various different scene requirements, which is not limited herein.
Optionally, at least one of the first conductive line, the via, and the second conductive line may be composed of a metal material; further optionally, at least one of the first conductive line, the via, and the second conductive line may be comprised of a polysilicon material. For example, the first conductive line may be etched from a polysilicon layer formed on an oxide layer on the substrate. The above selection manner of the materials of the first conductive line, the through hole, and the second conductive line is only an example, and in practical applications, different preparation materials may be selected for the first conductive line, the through hole, and the second conductive line according to various different scene requirements, which is not limited herein.
According to one embodiment of the present disclosure, various electronic components (e.g., chips, etc.) may be first fabricated within the substrate, and then the semiconductor structure as described in the present disclosure may be fabricated on the substrate to be electrically connected with the electronic components fabricated within the substrate and controlled by the semiconductor structure and the semiconductor devices formed thereby, etc.
According to an embodiment of the present disclosure, the method may further include: forming an insulating layer on the second oxide layer and/or the plurality of second conductive lines; and/or forming one or more third conductive lines electrically connected to the spiral-connected conductive structure, the spiral-connected conductive structure and the one or more third conductive lines constituting at least a portion of a semiconductor device. In this embodiment, after the semiconductor back-end process is completed, an insulating layer may be covered on the spirally connected conductive structure, a via hole is formed and connected to one or more third conductive lines obtained by etching the deposited metal layer, and the remaining parts of the semiconductor device are connected through the one or more third conductive lines, so as to manufacture different semiconductor devices by using the spirally connected conductive structure according to actual needs.
Examples of methods of making a spiral-connected conductive structure collectively comprised of a plurality of first conductive lines, a plurality of vias, and a plurality of second conductive lines according to embodiments of the present disclosure are disclosed above. In practical applications, various modifications or variations can be made to the conductive structure of the spiral connection, and these modifications and variations are also within the scope of the present disclosure. In practical applications, various designs can be made for the axial direction of the conductive structure of the spiral connection according to application scenarios, and fig. 6 shows various exemplary diagrams of the direction of the axial line OO' of the conductive structure of the spiral connection according to one embodiment of the present disclosure. As shown in fig. 6, the axis OO' of the spiral-connected conductive structure may not run exactly parallel to the substrate 110, but may run at an angle relative to the substrate, or may run approximately parallel to the substrate 110 in a curved manner, which is not limited herein. Further, fig. 7 illustrates examples of various top views of the axis OO' of the helically connected conductive structures according to one embodiment of the present disclosure. As shown in fig. 7, the axis OO' of the spirally connected conductive structure may also be a fully or semi-closed structure, such as a closed or semi-closed arc, a circle, a square, a triangle, an ellipse, a pentagon or various irregular figures, so that the spirally connected conductive structure correspondingly forms a surrounding or semi-surrounding coil, so that the magnetic lines of force may form a closed or semi-closed loop line in a direction parallel to the substrate according to a design, so as to meet the requirements of different application scenarios.
In addition, in practical applications, various designs may be made for the conductive lines and the through holes of the spiral-connected conductive structure according to application scenarios, and fig. 8 shows another example of the spiral-connected conductive structure according to an embodiment of the present disclosure. As shown in fig. 8, each conductive line and each through hole constituting the spiral-connected conductive structure may not be strictly parallel or perpendicular to the substrate 110, or may not be strictly linear, and may be variously designed according to the requirements of an actual scene, and the extending directions and the arrangement order of each first conductive line, each second conductive line, each through hole (sub-through hole, metal connection layer), and the like are flexibly arranged, as long as the spiral structure for communicating conduction can be formed, which is not limited herein.
The above shows the preparation method of the semiconductor structure according to the embodiment of the present disclosure, which can provide a coil structure with an axis approximately parallel to the substrate surface, so as to flexibly control the trend and distribution trend of the magnetic force lines on the substrate, and obtain a semiconductor device with high magnetic flux. According to the preparation method of the semiconductor structure, the corresponding physical model can be generated through the modulation parameters of multiple dimensions of the coil structure, semiconductor devices with various different space geometric structures can be flexibly and conveniently manufactured according to the requirements of practical application, the design efficiency and the device performance are improved, and the preparation method is suitable for different application scenes.
The above provides a semiconductor structure and a method of fabricating the semiconductor structure according to embodiments of the present disclosure. After the semiconductor structure described above is prepared, semiconductor devices having various specific uses can also be manufactured using the prepared semiconductor structure. According to an embodiment of the present disclosure, there is also provided a semiconductor device including the semiconductor structure as described in any of the above examples. Alternatively, the semiconductor device according to the embodiment of the present disclosure may be at least one of an energy conversion device, an energy storage device, a current measurement device, a voltage conversion device, an isolation communication device, or any combination thereof.
Alternatively, various parameters of the conductive structure of the spiral connection constituting the semiconductor structure may be determined according to the type and/or parameters of the semiconductor device. For example, the parameters of the conductive structure of the spiral connection, i.e. the coil parameters, may comprise at least one of the following: the coil size of the spiral connected conductive structure; the axial length and/or shape of the helically connected conductive structure; and the number of turns of the spirally connected conductive structure.
Unlike the two-dimensional coil structure prepared on the surface of the substrate in the prior art, the semiconductor structure according to the embodiment of the present disclosure is a coil structure of a three-dimensional space. Therefore, in the embodiment of the present disclosure, the requirements of semiconductor devices of different application types can be adapted by adjusting not only the size and the number of turns of the coil but also the topological structure of the length and/or the shape in the axial direction.
Alternatively, the semiconductor structure according to the embodiment of the present disclosure may form a quasi-four-dimensional parametric physical structure represented by a MODEL of MODEL, where "MODEL" represents "MODEL", "index" represents "coil MODEL type", lx and Ly represent the width and height (as shown in fig. 2) of a single-turn coil in the spirally-connected conductive structure, respectively, ts represents the topology of the axial structure of the coil (as shown in fig. 7), and n represents the number of turns of the coil.
In practical application, the above parameters can be arbitrarily valued according to the requirements of an application scene. Optionally, according to actual product requirements of the semiconductor integrated circuit, the value ranges of the above parameters may be: lx =0.1 to 10mm (may be integrated in the chip in accordance with the size of the chip), ly =10 -8 ～10 -7 m, ts may be a topology description parameter (for example, it may be expressed as Ts = (a 0.5 mm), where a denotes that the topology (shape) of the axial structure of the coil is a circle, 0.5mm denotes that the radius of the circle formed by the axial structure of the coil is 0.5 mm), and n may be 1 to 1000.
The values of the above parameters are merely examples, and in practical applications, any relevant parameter may be used to represent each property of the semiconductor structure. For example, when the shape of the single-turn coil of the semiconductor structure is not a square or rectangle, but an approximate arc, circle or ellipse, the parameters Lx and Ly may not be used to represent the width and height of the single-turn coil, but the radius R and the radian θ of the circle or the major and minor axes a and b of the ellipse may be used to represent the parameters of the semiconductor structure, without limitation. In the manufacturing process of the semiconductor device, various flexible selections and adjustments can be made on the parameters of the semiconductor structure.
The semiconductor structure can be used for manufacturing semiconductor devices with various purposes. For example, the semiconductor structure can be utilized as an energy conversion and storage device for application in semiconductor devices. When the number of turns of the semiconductor structure coil is n, and the alternating current or direct current passing through the coil is I, the magnetic field B in the coil can be expressed as: b = μ nI, where μ is the permeability of the magnetic material in the coil. Thus, the energy E stored in the coil can be expressed as:
where V is the volume within the coil.
According to the principle, the coil of the semiconductor structure can be used as an energy conversion device or an energy storage device to realize various corresponding functions.
Fig. 12 shows a schematic diagram of an energy conversion device according to an embodiment of the present disclosure. As shown in fig. 12, on-chip (on-chip) DC-DC conversion may be implemented. Where Vsupply is the input voltage and Vout is the output voltage, the circuit shown in fig. 12 can obtain a desired output voltage Vout (e.g., constant Vout). The basic operation principle of the circuit shown in fig. 12 is to feed back the output voltage Vout to the control circuit, so that the control circuit controls the switches of the two MOS transistors on both sides of the coil of the semiconductor structure to realize stable Vout output. Specifically, at time t1, the control circuit may control the MOS transistor switch M1 to be turned on, and the MOS transistor switch M2 to be turned off, where the input voltage Vsupply charges the coil of the semiconductor structure in the present disclosure. After the charging reaches a certain degree, and at the time point t2, the control circuit controls the switch M1 to be closed, the switch M2 to be opened, and the coil of the semiconductor structure charges the capacitor C, so as to form the output voltage Vout. The control circuit may perform voltage detection on the output voltage Vout. Subsequently, when the control circuit detects that the output voltage Vout reaches a certain set value, the switch M2 may be controlled to be turned off again, and the switch M1 may be turned on to charge the coil of the semiconductor structure. At this time, the capacitor C may be responsible for providing the output voltage Vout outwards.
When the control circuit detects that Vout is lower than Vout-dV during the process of providing the output voltage Vout by the capacitor C (where dV can be set according to the application requirements and circuit functions of the device to be provided), the control circuit will turn off the switch M1 again and turn on the switch M2 to control the stable output of the output voltage Vout. The circuit can enter a stable operating state through the above control circuit control and cycling process to achieve a stable Vout output.
Fig. 13 shows a schematic diagram of an energy storage device according to an embodiment of the present disclosure. As shown in fig. 13, when an electromagnetic field passes through a coil of a semiconductor structure in a circuit, a current is generated in the coil, and the generated current can obtain a Vout voltage through the circuit shown in fig. 13, and the obtained Vout voltage can be used for supplying electric energy to other electric devices.
Specifically, under the action of the electromagnetic field in the direction shown in fig. 13, the electromagnetic field may charge the coil of the semiconductor structure, thereby forming a forward voltage in the coil. In the circuit shown in fig. 13, the coil of the semiconductor structure may simultaneously charge the capacitor C through the diode D to obtain the output voltage Vout. After the electromagnetic field in the direction shown in fig. 13 is reversed, a reverse voltage opposite to the previous forward voltage is formed in the coil by the reverse electromagnetic field, the diode D is turned off, and the output voltage Vout is uniformly maintained as the forward voltage. As described above, under the action of the spatially alternating electromagnetic field, the capacitor C will be charged half of the time, so that the circuit shown in fig. 13 can be ensured to provide a relatively stable output of the forward voltage Vout, considering the capacity of the capacitor C to store electric energy.
In another example, the coil of the semiconductor structure may also be applied to a current measuring device. FIG. 14 shows a schematic diagram of a current measurement device according to one embodiment of the present disclosure. As shown in fig. 14, when a current-carrying wire through which a current flows is placed in the vicinity of the coil of the semiconductor structure, when a current I flows through the wire, a magnetic field B in the direction of the coil axis line OO' is generated in the coil of the semiconductor structure due to electromagnetic induction. The change of the intensity of the magnetic field B acts on the coil, so that a corresponding induction current I is generated in the coil C . Thereby, by measuring the induced current I in the coil C The change in the strength of the magnetic field B can be reflected and the current I through the wire can be measured accordingly. The placement of the wires shown in fig. 14 is merely an example, and the wires may be located on the upper portion of the coil as shown in fig. 14, or may be located on the lower portion of the coil (or substrate), for example. Examples of current measurement devices according to the present disclosure may make current measurements without introducing additional elements in the circuit-under-test.
In yet another example, the coil of the semiconductor structure may also be applied to a voltage conversion device. FIG. 15 shows a schematic diagram of a voltage conversion device according to one embodiment of the present disclosure. In the voltage conversion device shown in fig. 15, a structure in which two coils (an input coil and an output coil) are nested with each other in a semiconductor structure is used. As shown in fig. 15, one of whichVin (f) on both sides of the input coil is used as input alternating voltage, and Vout (f) on both sides of the other output coil is used as output alternating voltage. If the number of turns of the input coil is n and the number of turns of the output coil is m, the output voltage can be expressed as;
to achieve voltage conversion through a multiple coil nested configuration. The structure of the voltage conversion device shown in fig. 15 is merely an example, and in practical applications, flexible voltage conversion effects can be achieved by using different coil nesting manners and different numbers of coil nesting.
In yet another example, the coil of the semiconductor structure may also be applied to an isolated communication device. In many applications, it is desirable to measure and collect signals in a relatively high voltage environment and then pass the signals to a relatively low voltage circuit for processing. Conventional electrical connections may affect the reliability of the low voltage circuit, greatly increasing system cost. In the embodiment of the present disclosure, the coupling coil may be formed by a structure in which two coils are nested in each other in the above semiconductor structure, so that a signal can be freely transmitted between the high-voltage circuit and the low-voltage circuit under the condition of electrical isolation between the two coils, thereby realizing high-voltage and low-voltage isolation of a single chip and reducing system cost. In addition, the system reliability and stability are better than those of optical isolation and capacitive isolation. Fig. 16 shows a schematic diagram of an isolated communication device according to one embodiment of the present disclosure. In the isolated communication device shown in fig. 16, vin is an input signal, vout can be obtained through a coupling coil formed by nesting two coils, and then Vin can be restored through a restoring Circuit "Recover Circuit" at an output terminal, thereby realizing signal communication in an electrically isolated state.
In this example, the communication signal may be an alternating signal. Specifically, the alternating input signal Vin may be generated by illustrating a coupled coil formed by two coils nested within one another to produce the alternating output signal Vout. Here, the waveform of Vout may be different from Vin. Therefore, in this case, the waveform of Vout needs to be restored to Vin by the restoration circuit shown in fig. 16. In the case of different Vin waveforms, the specific recovery process may be;
1. if Vin is a sinusoidal waveform, vout may also be a sinusoidal waveform, but may have different amplitude variations. At this point, the recovery circuit may provide a simple amplified current to recover Vout to the desired amplitude value.
2. If Vin is a square waveform, vout will become a pulse waveform, with the pulses appearing at the rising and falling edges of the square waveform. At this time, the recovery circuit recovers the pulse waveform to a square waveform.
3. If Vin is a waveform of other form, it can be changed into a combination of a sine waveform and a square waveform by waveform transformation (such as fourier transform, etc.), so as to restore the waveform of Vout to the waveform of Vin and simultaneously restore to the required amplitude value by corresponding combination of the above two waveform restoration manners 1 and 2.
The application and the device specific structure of the semiconductor structure in fig. 12 to fig. 16 are all examples, and in practical application, the semiconductor structure may be applied to various different semiconductor devices and chip structures according to specific scene requirements, which is not limited herein.
Various changes, substitutions and alterations to the techniques herein may be made without departing from the techniques of the teachings as defined by the appended claims. Moreover, the scope of the claims of the present disclosure is not limited to the particular aspects of the process, machine, manufacture, composition of matter, means, methods and acts described above. Processes, machines, manufacture, compositions of matter, means, methods, or acts, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or acts.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the disclosure to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (10)
1. A semiconductor structure, comprising:
a substrate;
a first oxide layer formed on the substrate;
a plurality of first conductive lines formed on the first oxide layer and arranged in a specific direction;
a second oxide layer formed on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer, so that two ends of each of the plurality of first conductive lines are respectively connected with one through hole, and the through holes are filled with conductive materials; and
and a plurality of second conductive lines formed on the second oxide layer and respectively connected to one or more through holes, such that the plurality of first conductive lines, the plurality of through holes, and the plurality of second conductive lines collectively form a spiral-connected conductive structure.
2. The semiconductor structure of claim 1, wherein an axial direction of the spiral-connected conductive structure is parallel to the substrate.
3. The semiconductor structure of claim 1, wherein the particular direction is a linear, circular, arcuate, or scalloped direction parallel to the substrate.
4. The semiconductor structure of claim 1, wherein the second oxide layer comprises a plurality of stacked oxide sub-layers, and a plurality of sub-vias of the plurality of oxide sub-layers respectively pass through up and down to form at least a portion of the plurality of vias in the second oxide layer.
5. The semiconductor structure of claim 1, wherein,
the first conductive lines, the through holes and the second conductive lines form a plurality of conductive structures which are spirally connected and are mutually nested together, and the conductive structures are not electrically connected.
6. The semiconductor structure of claim 1, wherein,
the first conductive line is comprised of a polysilicon material.
7. The semiconductor structure of claim 1, wherein,
the semiconductor structure further includes: an insulating layer formed on the second oxide layer and/or the plurality of second conductive lines; and/or
One or more third conductive lines electrically connected with the spiral-connected conductive structure such that the spiral-connected conductive structure and the one or more third conductive lines constitute at least a portion of a semiconductor device.
8. A method of fabricating a semiconductor structure, comprising:
forming a first oxide layer on a substrate;
forming a plurality of first conductive lines arranged along a specific direction on the first oxide layer;
forming a second oxide layer on the first oxide layer and the plurality of first conductive lines, wherein a plurality of through holes are formed in the second oxide layer, so that two ends of each first conductive line in the plurality of first conductive lines are respectively connected with one through hole, and conductive materials are filled in the through holes; and
and forming a plurality of second conductive lines respectively connected with one or more through holes on the second oxide layer, so that the plurality of first conductive lines, the plurality of through holes and the plurality of second conductive lines jointly form a spiral-connected conductive structure.
9. A semiconductor device comprising the semiconductor structure of any one of claims 1-7.
10. The semiconductor device of claim 9, wherein the semiconductor device is:
at least one of an energy conversion device, an energy storage device, a current measurement device, a voltage conversion device, an isolated communication device, or any combination thereof.
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| CN109215979A (en) * | 2018-10-17 | 2019-01-15 | 安徽安努奇科技有限公司 | A kind of patch type inductance and preparation method thereof |
| US11450595B2 (en) * | 2019-12-27 | 2022-09-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package device with integrated inductor and manufacturing method thereof |
| CN114582586A (en) * | 2022-01-24 | 2022-06-03 | 南京中感微电子有限公司 | Integrated inductor and manufacturing method thereof, and direct current-direct current converter |
| CN114883083A (en) * | 2022-05-05 | 2022-08-09 | 北京航空航天大学 | Progressive MEMS double-layer solenoid inductance coil and integrated preparation method thereof |
| CN115331927A (en) * | 2022-08-15 | 2022-11-11 | 韩智毅 | Semiconductor structure, preparation method and semiconductor device |
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