CN109150276B - Hardware platform realized by general adaptive beam forming technology - Google Patents
Hardware platform realized by general adaptive beam forming technology Download PDFInfo
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- CN109150276B CN109150276B CN201811316464.8A CN201811316464A CN109150276B CN 109150276 B CN109150276 B CN 109150276B CN 201811316464 A CN201811316464 A CN 201811316464A CN 109150276 B CN109150276 B CN 109150276B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
- H04B7/0617—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal for beam forming
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/0408—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas using two or more beams, i.e. beam diversity
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
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Abstract
The invention provides a hardware platform realized by a general adaptive beam forming technology, which comprises: the AD daughter card acquires a multi-channel intermediate frequency analog signal through a multi-channel AD chip and performs analog-to-digital conversion to obtain a digital signal, and then serially processes the digital signal through high-speed LVDS in the FMC plug-in unit and outputs high-speed serial LVDS data to the general signal preprocessing board; the general signal preprocessing board is used for carrying out digital beam forming and accessory function programming processing on the high-speed serial LVDS data to obtain a beam forming result; the main control interface board is used for receiving the beam forming result through the high-speed LVDS, forwarding the received data stream, and calculating the self-adaptive channel coefficient to complete the time sequence forwarding and/or generating function; and the back plate is interconnected with the AD daughter card, the general signal preprocessing plate and the main control interface plate through a VPX plug-in unit so as to realize data interaction.
Description
Technical Field
The invention relates to a radar signal receiving beam forming system, in particular to a hardware platform realized by adopting a general adaptive beam forming technology of radar signals with phased array system, multiple sub-arrays, multiple digital receiving channels and high data rate.
Background
With the development of radar technology, high-speed digital devices and spatial filtering theory, modern radars have achieved digitization in the baseband, intermediate frequency and even partial radio frequency fields. Compared with a wave beam control method in an analog mode, the self-adaptive digital wave beam forming method which has the advantages of flexibility, accuracy and strong anti-jamming capability has obvious advantages. However, the adaptive beamforming algorithm also puts higher requirements on the hardware platform: high digital bandwidth, platform versatility and expandability, reliability, data processing real-time performance and the like.
At present, the development of a self-adaptive beam forming hardware platform is realized by analyzing resources required by a system according to specific functions of a specific model, designing hardware and finally programming. This design method has several major disadvantages:
1. the universality is poor, and a large amount of manpower and material resources are consumed by redesigning hardware every time, so that the development cost is increased, and the development period is prolonged;
2. the expansibility is poor, and on one hand, the expansibility comprises related expansibility of hardware, such as adding a receiving channel and the like; if the conventional design of the receiving channel is added, hardware redesign is needed to be carried out on the board; on the other hand, the method includes software-related expansibility, such as adding other digital algorithms (simultaneous multi-beam, angle super-resolution, etc.), and the conventional design requires overall software scheme change when adding other algorithms, and also has higher requirements on data interface bandwidth and digital logic resources of the system.
3. The reliability is poor, due to non-universal design, the reliability is not high, when the hardware platform is partially failed, the whole system can not work normally, and the redundant design can not be realized;
4. the data transmission speed is slow, the data transmission is carried out on the previous data flow signals through parallel data lines and address lines, the speed is slow, the reliability is not high, and the data flow signals are not suitable for long-distance transmission. The high-speed transmission bus also requires data packaging, so that the system processing has intermittence and pause, and the system delay is unstable.
At present, no explanation or report of the similar technology of the invention is found, and similar data at home and abroad are not collected.
Disclosure of Invention
The invention aims to provide a hardware platform realized by a general adaptive beam forming technology, which is used for solving the problems of poor universality, poor expansibility and poor reliability of the conventional adaptive beam forming hardware platform.
In order to achieve the above object, the present invention provides a hardware platform implemented by a general adaptive beamforming technology, including:
the AD daughter card acquires a multi-channel intermediate frequency analog signal through a multi-channel AD chip and performs analog-to-digital conversion to obtain a digital signal, and then serially processes the digital signal through high-speed LVDS in the FMC plug-in unit and outputs high-speed serial LVDS data to the general signal preprocessing board;
the general signal preprocessing board is used for carrying out digital beam forming and accessory function programming processing on the high-speed serial LVDS data to obtain a beam forming result;
the main control interface board is used for receiving the beam forming result through the high-speed LVDS, forwarding the received data stream, and calculating the self-adaptive channel coefficient to complete the time sequence forwarding and/or generating function;
and the back plate is interconnected with the AD daughter card, the general signal preprocessing plate and the main control interface plate through a VPX plug-in unit so as to realize data interaction.
Preferably, the AD daughter card can be reconfigured according to the requirement, is provided with 8 or 16 sampling channels, and is connected with the universal signal preprocessing board through an FMC plug-in.
Preferably, the general signal preprocessing board comprises four large-capacity FPGAs, and any two of the FPGAs are interconnected through a data line for configuring a differential and single-ended mode.
Preferably, the number of the universal signal preprocessing boards is 1 or more, and the universal signal preprocessing boards are connected with the backplane through the VPX plug-in, are provided with programmable board bit numbers, and can be loaded with programs running the same.
Preferably, the main control interface board comprises an FPGA chip and a DSP chip, the FPGA chip forwards the received data stream to the signal processing system through the optical fiber module, receives the beam forming system scheduling command through the CAN bus, and generates a system timing sequence, and the DSP chip completes weight calculation for adaptive beam forming and algorithm implementation of related expansion functions.
Preferably, the FPGA chip and the DSP chip realize data interaction through a Raipidii IO high-speed serial interface.
Preferably, the back board is provided with a VPX socket, adopts an equivalent full interconnection structure, and is used for providing full interconnection high-speed LVDS interconnection resources between any two VPX plug-ins, providing a programmable board number of each VPX plug-in, and simultaneously providing GPIO interconnection resources and broadcast-type parallel port resources.
Compared with the prior art, the invention has the following beneficial effects:
the configuration is flexible, the universality is strong, a user can increase or reduce the number of the universal preprocessing boards according to the needs, the AD chip model, the FPGA chip model and the DSP chip model can be customized according to the needs, the system structure is not influenced, and the redundant interface design is carried out according to the board position number, so that all the universal signal preprocessing boards can be loaded with the same logic software, and the number of backup parts is greatly reduced; the expansibility is strong, the number of data channels of the access platform and the software functions which can be realized by the platform can be customized, and the full interconnection structure of the platform back plate simultaneously supports the simultaneous formation of 4 digital beams under the condition of not increasing hardware links; the system has the advantages that the reliability is high, the preprocessing boards are interconnected through the serial LVDS high-speed structure, the data stream transmission mode ensures that the system processing delay is stable compared with the data packet transmission mode, and the LVDS transmission supported by the high-speed serial transceiver ensures the anti-interference capability of data transmission, so that the data transmission is reliable and effective.
Drawings
FIG. 1 is a diagram illustrating a hardware platform architecture for implementing adaptive beamforming in accordance with a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a basic architecture of a general signal preprocessing board according to a preferred embodiment of the present invention;
fig. 3 is a schematic diagram of a main control interface board architecture according to a preferred embodiment of the present invention.
Detailed Description
While the embodiments of the present invention will be described and illustrated in detail with reference to the accompanying drawings, it is to be understood that the invention is not limited to the specific embodiments disclosed, but is intended to cover various modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.
For the convenience of understanding the embodiments of the present invention, the following description will be further explained by taking specific embodiments as examples with reference to the drawings, and the embodiments are not to be construed as limiting the embodiments of the present invention.
Referring to fig. 1, a hardware platform implemented by the general adaptive beamforming technology provided in this embodiment includes:
the AD daughter card acquires a multi-channel intermediate frequency analog signal through a multi-channel AD chip and performs analog-to-digital conversion to obtain a digital signal, and then serially processes the digital signal through high-speed LVDS in the FMC plug-in unit and outputs high-speed serial LVDS data to the general signal preprocessing board;
the general signal preprocessing board is used for carrying out digital beam forming and accessory function programming processing on the high-speed serial LVDS data to obtain a beam forming result;
the main control interface board is used for receiving the beam forming result through the high-speed LVDS, forwarding the received data stream, and calculating the self-adaptive channel coefficient to complete the time sequence forwarding and/or generating function;
and the back plate is interconnected with the AD daughter card, the general signal preprocessing plate and the main control interface plate through the VPX plug-in unit so as to realize data interaction.
The AD daughter card mainly completes data acquisition, can configure multi-channel digital acquisition, serves as a platform signal access source, can be reconfigured according to needs, is provided with a plurality of (generally 8 or 16) sampling channels, and is connected with the general signal preprocessing board through the FMC plug-in.
The general signal preprocessing board mainly comprises four high-capacity FPGAs (field programmable gate arrays) for completing digital beam forming and other programmable auxiliary functions, coefficients used by the digital beam forming are calculated by the main control board and are updated through a high-speed serial LVDS communication link, and meanwhile, abundant logic resources on the board can complete system function expansion, such as a pulse compression module, a data channel correction module, a channel equalization module and the like. Any two FPGAs are interconnected through a data line for configuring a differential single-ended mode. The universal signal preprocessing board can be 1 or more as required and is connected with the backboard through the VPX plug-in, and the universal signal preprocessing board is provided with a programmable board bit number and can be loaded and run the same program.
The main control interface board comprises an FPGA chip and two DSP chips, wherein the FPGA chip is mainly responsible for receiving a beam forming result received through the high-speed LVDS, transmitting the received data stream to the signal processing system through the optical fiber module, receiving a beam forming system scheduling command through the CAN bus and generating a system time sequence. And the DSP chip completes weight calculation of self-adaptive beam forming and algorithm realization of related expansion functions. The FPGA chip and the DSP chip realize data interaction through a Raipid IO high-speed serial interface.
The back board mainly realizes the data interaction function, and is provided with a VPX socket which is interconnected with each board card through a VPX plug-in. The platform back plate adopts an equivalent full-interconnection structure and is used for providing full-interconnection high-speed LVDS interconnection resources between any two VPX plug-ins, providing a programmable plate number of each VPX plug-in, simultaneously providing GPIO interconnection resources and broadcast parallel port resources, and providing interface support for realizing the expansion of other digital beam algorithms such as simultaneous multi-beam and the like.
The invention mainly collects the intermediate frequency receiver signal through the AD daughter card, the general signal preprocessing board completes the channel weighting to form the digital wave beam, the digital wave beam is transmitted to the main control interface board through the data interface, the main control interface board transmits the signal to the signal processing through the optical fiber, meanwhile, the main control interface board receives the sampling signal of the general signal preprocessing board, calculates the self-adaptive coefficient through the self-adaptive algorithm, and feeds back the self-adaptive coefficient to the general signal preprocessing board.
The following examples are provided for further illustration, but the present invention is not limited to the composition and function of the present invention.
Application example:
the platform samples the intermediate frequency analog signals of the receiver through the AD daughter card, and the acquired multi-channel data are transmitted to the general signal preprocessing board through the high-speed LVDS. In the application example, the AD daughter card adopts two AD9653 chips of ADI company to realize 8-channel 40Mhz intermediate frequency sampling, and each motherboard can carry two AD daughter cards, so that the combination of one general signal preprocessing board and the AD daughter card can finish the sampling of 16 intermediate frequency receiving channels;
the general signal preprocessing board mainly completes digital beam forming and other programmable accessory functions, referring to fig. 2, in the application example, four stratxiv series EP4SE530H40I4 chips of Altera company are selected as main chips to complete the realization of main logic modules, the FPGA chip is interconnected with other general signal preprocessing boards and a main control interface board through a high-speed serial LVDS communication link to transmit digital beam information and channel coefficient data, meanwhile, system function expansion is also completed by utilizing abundant logic resources on the board, for example, a pulse compression module, a data channel correction module, a channel equalization module and the like are added, 4 general preprocessing boards are selected in the application example, and the number of channels accessed to a hardware platform is 64;
the main control interface board completes the functions of self-adaptive beam forming weight calculation, digital beam data forwarding, sequential control, scheduling information forwarding and the like. Referring to fig. 3, in this example, the stratxiv series EP4SE230H40I4 from Altera corporation is selected as the FPGA chip, and the TI6678 multi-core chip is selected as the high-speed DSP chip; the FPGA chip is mainly responsible for receiving a beam forming result received through the high-speed LVDS, transmitting data stream to a signal processing system through an optical fiber module, receiving a beam forming system scheduling command through a CAN bus, generating a system time sequence, finishing weight calculation of self-adaptive beam forming and algorithm realization of related expansion functions by the DSP chip, and realizing data interaction between the FPGA chip and the DSP chip through a Raipid IO high-speed serial interface;
the back plate mainly realizes a data interaction function, is interconnected with each board card through the VPX plug-in, adopts an equivalent full-interconnection structure, provides programmable board numbers for all the general signal preprocessing boards, and can flexibly configure data interfaces.
The application example completes the function of the radar self-adaptive beam forming system with 64 sub-array channels through the hardware architecture. The problem that the development universality, expansibility, reliability and data real-time performance of a conventional radar beam forming system are poor is solved.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be able to make modifications or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (7)
1. A hardware platform implemented by a generic adaptive beamforming technique, comprising:
the AD daughter card acquires a multi-channel intermediate frequency analog signal through a multi-channel AD chip and performs analog-to-digital conversion to obtain a digital signal, and then serially processes the digital signal through high-speed LVDS in the FMC plug-in unit and outputs high-speed serial LVDS data to the general signal preprocessing board;
the general signal preprocessing board is used for carrying out digital beam forming and accessory function programming processing on the high-speed serial LVDS data to obtain a beam forming result;
the main control interface board is used for receiving the beam forming result through the high-speed LVDS, forwarding the received data stream, and calculating the self-adaptive channel coefficient to complete the time sequence forwarding and/or generating function;
the back board is interconnected with the AD daughter card, the general signal preprocessing board and the main control interface board through a VPX plug-in unit so as to realize data interaction;
and the coefficient used by the digital beam forming on the general signal preprocessing board is calculated by the main control interface board and is updated through the high-speed LVDS communication link.
2. The hardware platform implemented by the general adaptive beamforming technology according to claim 1, wherein the AD daughter card is reconfigurable as required, has 8 or 16 sampling channels, and is connected to the general signal preprocessing board through FMC plug-in.
3. The hardware platform implemented by the general adaptive beamforming technology of claim 1, wherein the general signal preprocessing board comprises four large-capacity FPGAs, and any two pieces of the general signal preprocessing board are interconnected through a data line for configuring a differential and single-ended mode.
4. The hardware platform implemented by the general adaptive beamforming technology of claim 1 or 3, wherein the number of the general signal preprocessing boards is 1 or more, and the general signal preprocessing boards are connected to the backplane through a VPX plug-in, are provided with programmable board bit numbers, and can be loaded with programs running the same.
5. The hardware platform implemented by the general adaptive beamforming technology according to claim 1, wherein the main control interface board comprises an FPGA chip and a DSP chip, the FPGA chip forwards the received data stream to the signal processing system through the optical fiber module, receives the beamforming system scheduling command through the CAN bus, and generates a system timing sequence, and the DSP chip performs weight calculation for adaptive beamforming and algorithm implementation of related expansion functions.
6. The hardware platform implemented by the general adaptive beamforming technology of claim 5, wherein the FPGA chip and the DSP chip implement data interaction through a Raipidii IO high-speed serial interface.
7. The hardware platform implemented by the general adaptive beamforming technology of claim 1, wherein the backplane is provided with a VPX socket, and an equivalent full interconnect structure is adopted to provide full interconnect high-speed LVDS interconnect resources between any two VPX cards, and provide a programmable board number of each VPX card, and is provided with GPIO interconnect resources and broadcast-type parallel port resources.
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