CN214591471U - Low-cost miniaturized full-airspace full-frequency-band signal interception device - Google Patents

Abstract

The utility model relates to a wireless countermeasure technical field specifically discloses a full frequency channel signal of low-cost miniaturized full airspace intercepts and captures device, including antenna array, connector, FPGA that the order is connected, and the order is connected the connector with ware is divided to merit between the FPGA, and is connected the connector with direction finding wave detector between the FPGA. The utility model discloses be equipped with the antenna array, the connector, FPGA, the merit is divided the ware, the direction finding wave detector etc, circuit main part (connector, FPGA, the merit is divided the ware, the direction finding wave detector) can be integrated on the integrated board of a 3U specification because of the structure is little, the miniaturization has been realized, low cost, wherein the receiver, the merit is divided the ware, the frequency measurement circuit that FPGA constitutes can realize full frequency channel frequency measurement, the receiver, the direction finding circuit that direction finding wave detector and FPGA constitute can realize full airspace direction finding, whole full airspace full frequency channel signal to RF signal has been realized and has been intercepted.

Description

Low-cost miniaturized full-airspace full-frequency-band signal interception device

Technical Field

The utility model relates to a wireless confrontation technical field especially relates to a full frequency channel signal of low-cost miniaturized airspace intercepts and captures device.

Background

As shown in fig. 1, the conventional full-airspace full-band signal detection device needs 4 modules of 3U specifications, including a down-conversion module, a digital receiving module, a single-bit module, and a computer module, to realize detection of full-airspace and full-band signals. After a radio frequency input signal is subjected to front-end amplification, filtering and shunting, 1 path of the radio frequency input signal enters a single-bit module to complete 1 GHz-18 GHz broadband instantaneous coverage, and the other 4 paths of the radio frequency input signal enter a down-conversion module which is divided into 4 sections according to the instantaneous bandwidth 1GHz and is completely converted into 1.3G-2.3 GHz intermediate frequency, and then the radio frequency input signal enters a digital receiving module to complete pulse monitoring, parameter extraction, interferometer direction finding and radiation source positioning, so that the interferometer direction finding of the instantaneous bandwidth 1GHz is realized. The frequency source component is controlled by the computer module to realize the switching of working frequency bands, and the final result is completely transmitted to the preprocessing and sorting module, and the obtained result is displayed on the computer module.

As shown in fig. 2, the digital receiver module adopts a VPX architecture, and the radio frequency adopts a back outgoing line mode; and the backup optical fiber interface adopts a rear outlet mode. The module is provided with 4 paths of ADCs, and is connected with 2 pieces of FPGAs in back, and is used for digital receiving processing of 4 1GHz bandwidths in a frequency range of 1 GHz-18 GHz. When a hardware circuit is designed, equal-length design needs to be carried out on sampling clocks among multiple paths of ADCs and routing among the ADCs and the FPGA, and the receiving synchronization of the JESD204B needs to be adjusted, so that the phase consistency of sampling of the multiple paths of ADCs is guaranteed. Multiple sets of memory in the module are used to store raw data and PDW data. Two groups of DDR3 memories are hung on the FPGA1 and used for storing original data. QDR-II on FPGA2 is used to store PDW parameters. The optical transceiver module is a backup option, and when the original data needs to be stored continuously for a long time, the original data is transmitted by using the optical fiber and is stored in an external large-capacity data recorder for a long time.

The digital receiver module receives 4 paths of 1.3G-2.3 GHz intermediate frequency signals, respectively finishes acquisition and quantization, sends the signals into the FPGA for digital signal processing, forms PDW parameters, caches the PDW parameters and 1 path of original data, and reports the PDW parameters and the 1 path of original data to the computer module for subsequent processing. Which path of original data is cached can be manually selected by the upper computer. The FPGA is used as a core of signal processing, a main processing FPGA1 is selected to complete the processing of 4 paths of intermediate frequency signals, and an FPGA2 is used as a coprocessor and is controlled by an external interface. And after the signal processing is finished, packaging and reporting the PDW parameters and the original data. DDR3 in the module selects 4Gbit capacity (256M 16bit), each group has 2 chips, group A and group B together constitute 256M 32bit ping-pong memory, which is used to store 1 path of original data with maximum 2.5Gsps sampling rate of 12 bit. The continuous storage time of the raw data can reach more than 220ms for the sampling rate of 2.5 Gsps. The QDR-II is 144-Mbit QDR-II + SRAM, can store PDW parameters for a long time, and is convenient for the FPGA and the computer to access bidirectionally.

As shown in fig. 3, the single-bit frequency measurement is implemented by using a single-bit receiving system, after a radio frequency signal enters a module, the radio frequency signal enters a high-speed single-bit quantization direct sampling after being filtered, amplified by frequency conversion, and then is subjected to real-time pipeline processing after being quantized, so as to obtain a frequency code and a bandwidth, and the frequency code and the bandwidth are output to an amplitude measurement module. Inputting a path of 1 GHz-18 GHz signals, dividing the signals into two sections according to 1 GHz-6 GHz and 6G-18 GHz, wherein the 1 GHz-6 GHz is directly amplified and filtered and then sent to a single-bit ADC for quantization, and the other path of signals is subjected to frequency conversion from 6 GHz-18 GHz to 0.5 GHz-6.5 GHz and then sent to the single-bit ADC for quantization. And after the two paths of single-bit ADCs are processed, the output frequency code and the width-preserving signal are obtained after the results are fused.

Although the existing full-airspace full-band signal detection device can realize full-airspace full-band signal detection, 4 3U modules are adopted, and the device relates to a plurality of circuits, and is high in cost and large in size.

SUMMERY OF THE UTILITY MODEL

The utility model provides a low-cost miniaturized full airspace full-band signal interception device, the technical problem of solution lies in: how to realize full-space-domain full-frequency-band signal interception with smaller volume and lower cost.

In order to solve the technical problem, the utility model provides a low-cost miniaturized full airspace full-band signal capture device, which comprises an antenna array, a connector, a FPGA, a power divider and a direction detector, wherein the antenna array, the connector, the FPGA and the power divider are sequentially connected, the power divider is sequentially connected between the connector and the FPGA, and the direction detector is connected between the connector and the FPGA;

the antenna array receives full airspace signals to obtain M paths of RF signals, and the M paths of RF signals are sent to the connector, wherein M is more than or equal to 4; the connector outputs one of the M paths of RF signals to the power divider and outputs the M paths of RF signals to the direction finding detector; the power divider divides an input RF signal into N RF sub-signals which are input to the FPGA through a GTX high-speed serial interface of the FPGA, wherein N is more than or equal to 2; the direction detector carries out video envelope detection and ADC sampling on the input multi-channel RF signals in sequence and then inputs the signals to the FPGA;

and the FPGA carries out frequency measurement on the input N paths of RF sub-signals and carries out direction measurement on the input M paths of RF signals.

Preferably, the antenna array adopts M paths of antennas to realize the full-space-domain signal receiving at even interval distribution.

Preferably, the power divider is a 4-power divider, that is, N is 4.

Preferably, the single-channel frequency measurement bandwidth of the GTX high-speed serial interface is 4-6 GHz, and the full coverage of the bandwidth of 2-18 GHz of 4 paths of RF radio frequency sub-signals is realized.

Preferably, the utility model provides a pair of low-cost miniaturized full airspace full frequency channel signal interception device still including connecting FPGA's treater, the treater is right the pulse description word that FPGA generated carries out the analysis, and discerns the pulse radiation source.

Preferably, the utility model provides a pair of low-cost miniaturized full airspace full frequency channel signal capture device still including connecting the network interface of treater, the treater passes through the network interface transmits the identification result of pulse radiation source to control system.

Preferably, the control system sends the generated countermeasure to the processor through the network interface to generate a corresponding interference signal, and transmits the interference signal to the pulsed radiation source through the FPGA, the connector, and the antenna array, so as to implement interference on the pulsed radiation source in a predetermined orientation and at a predetermined frequency and in a predetermined interference pattern.

Preferably, the connector is a digital-analog hybrid connector.

Preferably, the utility model provides a pair of low-cost miniaturized full airspace full frequency channel signal interception device still including connecting FPGA's first memory with connect the second memory of treater.

Preferably, the utility model provides a pair of low-cost miniaturized full airspace full frequency channel signal interception device, M way antenna all adopts feedback formula compression type double-ridge rectangle horn antenna.

The utility model provides a pair of low-cost miniaturized full airspace full frequency channel signal interception device, be equipped with the antenna array, the connector, FPGA, the ware is divided to the merit, the direction finding wave detector etc, circuit main part (connector, FPGA, the merit is divided the ware, the direction finding wave detector) can be integrated on the integrated board of a 3U specification because of the structure is little, the miniaturization has been realized, low cost, wherein the receiver, the merit is divided the ware, the full frequency channel frequency measurement can be realized to the frequency measurement circuit that FPGA constitutes, the receiver, the direction finding circuit that direction finding wave detector and FPGA constitute can realize full airspace direction finding, whole full airspace full frequency channel signal interception to RF signal has been realized.

Drawings

Fig. 1 is a circuit structure diagram of a conventional full-airspace full-band signal interception apparatus provided in the background art of the present invention;

fig. 2 is a circuit structure diagram of the digital receiving module in fig. 1 according to the background art of the present invention;

fig. 3 is a circuit structure diagram of a single-bit module in fig. 1 according to the background of the present invention;

fig. 4 is a first circuit structure diagram of a low-cost miniaturized full-airspace full-band signal capture device provided by the embodiment of the present invention;

fig. 5 is a block diagram of the connector of fig. 4 according to an embodiment of the present invention;

fig. 6 is a structural diagram of a single antenna in fig. 4 according to an embodiment of the present invention;

fig. 7 is a second circuit structure diagram of a miniaturized full airspace full-band signal capture device according to an embodiment of the present invention.

Detailed Description

The following embodiments of the present invention will be described in detail with reference to the accompanying drawings, which are given for illustrative purposes only and are not to be construed as limiting the invention, including the drawings, which are only used for reference and illustration, and do not constitute a limitation to the scope of the invention, since many changes may be made thereto without departing from the spirit and scope of the invention.

The embodiment of the utility model provides a pair of low-cost miniaturized full airspace full frequency channel signal capture device, as shown in figure 4, including antenna array, connector, FPGA that the order is connected to and the merit of connecting between connector and FPGA divides the ware, and connects the direction finding wave detector between connector and FPGA in order.

The antenna array receives full airspace signals to obtain M paths of RF signals, and the M paths of RF signals are sent to the connector, wherein M is more than or equal to 4; the connector outputs one of the M paths of RF signals to the power divider and outputs the M paths of RF signals to the direction-finding detector; the power divider divides an input RF signal into N RF sub-signals which are input to the FPGA through a GTX high-speed serial interface of the FPGA, wherein N is more than or equal to 2; the direction-finding detector carries out video envelope detection and ADC sampling on the input multi-channel RF signals in sequence and then inputs the signals to the FPGA.

The FPGA carries out frequency measurement on the input N paths of RF sub-signals and carries out direction measurement on the input M paths of RF signals. In fact, the apparatus further comprises a first memory connected to the FPGA for storing the related information. And a filter is arranged between the antenna array and the connector to increase the signal-to-noise ratio and release the signal power. And the power supply circuit is used for supplying power to each circuit module.

Specifically, the antenna array adopts M paths of antennas to realize the full-space-domain signal receiving at even interval distribution. When M is 4, adopting 4 amplitude comparison direction finding; when M is 6, 4-amplitude azimuth or 6-amplitude azimuth can be adopted; when M is 8, 4, 6, or 8 yaw may be used. Wherein the accuracy of 8 log direction is higher than 6 log direction and higher than 4 log direction. The general case of 4-way direction finding accuracy is 10 degrees R.M.S, and 8-way direction finding accuracy is 6 degrees R.M.S.

In this embodiment, for example, 8 antennas and 4 power dividers (a single-channel frequency measurement bandwidth is 4-6 GHz), the received 8 RF signals are input to a direction detector, and are subjected to video detection and low-speed ADC sampling, and then enter a large-scale FPGA to realize full-airspace amplitude-versus-direction measurement. The power-divided 4-path RF radio frequency sub-signals directly enter the FPGA through a GTX high-speed interface of the FPGA to carry out full-band direction finding, and the GTX is a high-speed serial interface and is equivalent to a 1-bit ADC and a 4-path 1-bit ADC. Specifically, the acquisition rate of the GTX in this embodiment is 9GHz, so that each path of signal can cover the frequency measurement with a 4GHz bandwidth, and the 4 paths of signals can simultaneously realize the frequency measurement coverage of a full frequency band (2 to 18 GHz).

Preferably, the connector is a new generation 7-row MultiGig RT2 connector developed by Tyco. The MultiGig RT2 connector has excellent performance, controllable characteristic impedance, low insertion loss, and crosstalk less than 3% at transmission rates up to 6.25 Gbps. The VPX standard still uses the euroca 3U in structure. As shown in FIG. 5, 1 8-column 7-row RT2 connector P0 and 2 16-column 7-row RT2 connectors P1-P2 are defined on the 3U VPX board. Wherein, P0 is a public connecting end and provides a maintenance management bus, a test bus and a power supply signal; p1 provides 32 pairs of differential pair signals and 8 single-ended signals; p2 is user-defined and can be defined as either a differential signal or a single-ended signal.

The utility model discloses be equipped with the antenna array, a connector, FPGA, the merit is divided the ware, the direction finding wave detector etc, circuit main part (connector, FPGA, the merit is divided the ware, the direction finding wave detector) can be integrated on the integrated board (the 3U integrated board shown in figure 5) of a 3U specification because of the structure is little, the miniaturization has been realized, low cost, wherein the receiver, the merit is divided the ware, the frequency measurement circuit that FPGA constitutes can realize full frequency channel frequency measurement, the receiver, the direction finding circuit that direction finding wave detector and FPGA constitute can realize full airspace direction finding, whole full airspace full frequency channel signal to RF signal has been realized and has been intercepted.

In order to improve the measurement effect and the control volume of the interception device, the antenna array of this embodiment is based on a feedback type compression type double-ridge rectangular horn antenna, and the structure of the antenna array is shown in fig. 6, which has the advantages that:

1. the cost of the antenna can be controlled so as to meet the requirement of reducing the cost of the whole machine;

2. the gain of the antenna is high enough in the scanning range, and the requirement of system power can be met;

3. the antenna beam width is wide enough to meet the beam coverage requirements.

The ridge waveguide horn antenna has the advantages of small volume, light weight, compact structure, high strength, convenient installation, high aperture utilization rate, strong wind resistance, large power capacity, flexible aperture amplitude control and the like. In consideration of practical application, the ridge waveguide is adopted to increase the bandwidth of the antenna, reduce the caliber width of the H surface and further increase the beam width of the H surface, and meanwhile, for the practical processing simplicity, the logarithmically-graded ridge is changed into the linearly-graded ridge, and the influence is within an acceptable range.

As shown in fig. 7, the signal interception apparatus of this embodiment further includes a network interface connected to the processor, and a second memory (for storing related information) connected to the processor, wherein the processor transmits the identification result of the pulsed radiation source to the control system through the network interface. The processor can realize the sorting of signals, control the FPGA, the direction detector, the antenna array and the like. The input finished by the control system is a pulse description word (frequency, arrival time, pulse width, direction and repetition frequency) sent by a network interface, and the identification of the radiation source is finished by analyzing five parameters of the pulse description word. The control system can also generate a countermeasure strategy according to the identification result, send the countermeasure strategy to the processor through the network interface to generate a corresponding interference signal, and transmit the interference signal to the pulse radiation source through the FPGA, the connector and the antenna array, so that the pulse radiation source is interfered in a given direction and a given frequency by adopting a given interference pattern, and the device can complete a battle task in an hostile environment.

The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be equivalent replacement modes, and all are included in the scope of the present invention.

Claims (10)

1. A low-cost miniaturized full-airspace full-band signal interception device is characterized by comprising an antenna array, a connector, an FPGA, a power divider and a direction detector, wherein the antenna array, the connector and the FPGA are sequentially connected, the power divider is sequentially connected between the connector and the FPGA, and the direction detector is connected between the connector and the FPGA;

the antenna array receives full airspace signals to obtain M paths of RF signals, and the M paths of RF signals are sent to the connector, wherein M is more than or equal to 4; the connector outputs one of the M paths of RF signals to the power divider and outputs the M paths of RF signals to the direction finding detector; the power divider divides an input RF signal into N RF sub-signals which are input to the FPGA through a GTX high-speed serial interface of the FPGA, wherein N is more than or equal to 2; the direction detector carries out video envelope detection and ADC sampling on the input multi-channel RF signals in sequence and then inputs the signals to the FPGA;

and the FPGA carries out frequency measurement on the input N paths of RF sub-signals and carries out direction measurement on the input M paths of RF signals.

2. A low-cost miniaturized full-airspace full-band signal acquisition device as claimed in claim 1, wherein: the antenna array adopts M paths of antennas to realize the full-airspace signal receiving at even interval distribution.

3. A low-cost miniaturized full-airspace full-band signal acquisition device as claimed in claim 2, wherein: the power divider is a 4-power divider, namely N is 4.

4. A low-cost miniaturized full-airspace full-band signal acquisition device as claimed in claim 3, wherein: the single-channel frequency measurement bandwidth of the GTX high-speed serial interface is 4-6 GHz, and the full coverage of the bandwidth of 2-18 GHz of 4-channel RF sub-signals is realized.

5. A low-cost miniaturized full-airspace full-band signal acquisition device as claimed in claim 1, wherein: the system also comprises a processor connected with the FPGA, and the processor analyzes the pulse description words generated by the FPGA and identifies a pulse radiation source.

6. A low-cost miniaturized full-airspace full-band signal acquisition device as claimed in claim 5, wherein: the system also comprises a network interface connected with the processor, and the processor transmits the identification result of the pulse radiation source to the control system through the network interface.

7. A low-cost miniaturized full-airspace full-band signal acquisition device as claimed in claim 6, wherein: the control system sends the generated countermeasure strategy to the processor through the network interface so as to generate a corresponding interference signal, and transmits the interference signal to the pulse radiation source through the FPGA, the connector and the antenna array, so that the pulse radiation source is interfered by a set interference pattern at a set direction and a set frequency.

8. A low-cost miniaturized full-airspace full-band signal acquisition device as claimed in claim 7, wherein: the connector is a digital-analog hybrid connector.

9. A low-cost miniaturized full-airspace full-band signal acquisition device as claimed in claim 6, wherein: the FPGA-based touch screen display device further comprises a first memory connected with the FPGA and a second memory connected with the processor.

10. A low-cost miniaturized full-airspace full-band signal acquisition device as claimed in claim 2, wherein: and the M-path antenna adopts a feedback type compression type double-ridge rectangular horn antenna.

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