CN213423461U - High-efficiency broadband digital beam former for hierarchical dimensionality reduction processing - Google Patents
High-efficiency broadband digital beam former for hierarchical dimensionality reduction processing Download PDFInfo
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Abstract
A high-efficiency broadband digital beam former for hierarchical dimensionality reduction comprises a high-speed AD sampling circuit, a primary beam preprocessing module, an optical fiber channel transmission link and a high-performance broadband digital beam former, and adopts design ideas such as signal hierarchical dimensionality reduction, data parallel processing, high-capacity data high-speed transmission, high-performance beam forming hardware and the like, on the premise of ensuring the freedom degree of a space signal of a full digital array channel, the broadband self-adaptive digital beam forming is realized by two-stage signal dimensionality reduction, on the premise of ensuring the freedom degree of the space signal of the array channel, the acquisition, transmission and processing of multi-channel broadband data can be efficiently completed, the broadband self-adaptive digital beam forming of no less than 200 digital array channels can be completed within 1ms, the beam pointing precision is superior to 1 degree (rms), the response real-time of a system is improved, and the formed beam is stable, stable and convenient, The beam pointing accuracy is high, and the application of a large digital array radar system in a complex environment can be met.
Description
Technical Field
The utility model belongs to the technical field of signal processing, concretely relates to high-efficient broadband digital beam former of hierarchical dimensionality reduction processing.
Background
The environment of modern radar is increasingly complex, various passive or active interferences inevitably exist, and in order to realize the radar anti-interference and improve the target detection capability, the self-adaptive digital beam forming technology is widely applied and developed. The adaptive beam forming can adaptively update the weight vector along with external change based on a certain criterion, change the beam shape, have better interference suppression capability and more flexible beam control mode, and have stronger adaptive capability to the environment.
In the modern radar 2014, 36 th volume of ' design of high-speed multi-channel time domain broadband digital beam former ' (pages 24-28) ' a text of a broadband phased array radar mass data transmission and large digital multi-beam forming calculation amount, a broadband digital beam forming algorithm based on any time delay filter is provided, and the design realizes the high-speed multi-channel broadband digital beam former based on the algorithm, adopts a design idea of a high-speed serial interface, FPGA parallel calculation and a modularized program structure, maximally supports 48 channels, and can simultaneously synthesize 3 beams if all the channels are used under the bandwidth of 200 MHz; if only 16 channels are used, 8 beams can be synthesized simultaneously. Although a technical approach of broadband digital beam high-speed large-capacity data transmission and high-performance real-time processing is provided, the number of processed channels only supports 48 channels at most, and the timeliness of system data processing is not explained, the technical scheme can only meet the use of a digital array radar system with a small array and low anti-interference capability, and for a large digital array radar system with hundreds of antenna array elements or even thousands of antenna array elements, multi-target detection and tracking, high system real-time response and high airspace anti-interference capability, the technical scheme is difficult to meet engineering application, so that a digital beam former capable of solving the technical problems of large multichannel broadband data parallel processing capacity, poor system real-time response capability, difficult airspace anti-interference advantage application in engineering and the like is urgently needed.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a high-efficient broadband digital beam former of hierarchical dimensionality reduction processing.
The utility model discloses a following technical scheme can realize.
The utility model provides a high-efficient broadband digital beam former of hierarchical dimensionality reduction processing, including high-speed AD sampling circuit, one-level beam preprocessing module, fibre channel transmission link, high performance broadband digital beam former, high-speed AD sampling circuit is connected with one-level beam preprocessing module, and one-level beam preprocessing module is connected with high performance broadband digital beam former through fibre channel transmission link;
the high-speed AD sampling circuit comprises a multi-channel high-speed AD sampling chip and is used for completing high-speed sampling of multi-channel intermediate-frequency echo signals;
the primary wave beam preprocessing module comprises an FPGA preprocessing chip and is used for processing the sampling of the multi-channel intermediate frequency echo signals from the high-speed AD sampling circuit to form multi-channel primary digital wave beams;
the optical fiber channel transmission link comprises a multi-path transmission optical fiber, and transmits multi-path primary digital beams processed and formed by the primary beam preprocessing module to a high-performance broadband digital beam former;
the high-performance broadband digital beam former comprises an FPGA processing chip and a DSP chip, and is used for processing multi-channel primary digital beams from an optical fiber channel transmission link to form beams meeting the detection requirement of a large digital array radar system in a complex environment.
Furthermore, the number of AD sampling channels of an AD sampling chip in the AD sampling circuit is not less than 2, the sampling rate is not less than 200MHz, and the number of AD significant digits is not less than 11.
Furthermore, the number of internal logic units of the FPGA preprocessing chip in the primary beam preprocessing module is not less than 40 ten thousand, the number of the internal logic units of the FPGA preprocessing chip is not less than 42Mb, the number of the DSP Slice is not less than 2800, and the number of the GTH13.1Gb/s transceivers is not less than 50.
Furthermore, the transmission speed of the optical fiber single channel of the optical fiber channel transmission link is not less than 6 Gbps.
Furthermore, the number of internal logic units of the FPGA processing chip in the high-performance broadband digital beam former is not less than 69 ten thousand, the number of internal logic units of the FPGA processing chip is not less than 52Mb, the number of DSP Slice is not less than 3600, and the number of GTH13.1Gb/s transceivers is not less than 80.
Furthermore, more than 8 floating-point digital signal processing cores are configured in the DSP chip in the high-performance broadband digital beam former, the dominant frequency is 1.25GHz, and the peak processing capacity is more than 160 GFlos/s.
Furthermore, the high-speed AD sampling circuit and the primary beam preprocessing module are both provided with a plurality of modules.
Furthermore, the high-speed AD sampling circuits are connected with the primary beam preprocessing modules in a one-to-one correspondence mode, and the multi-path echo signals collected by each high-speed AD sampling circuit are transmitted to the corresponding primary beam preprocessing module to be preprocessed.
Furthermore, the plurality of optical fiber channel transmission links correspond to the plurality of primary beam preprocessing modules one to one, and signals preprocessed by the plurality of primary beam preprocessing modules are transmitted to the high-performance broadband digital beam former.
The beneficial effects of the utility model reside in that: the utility model adopts the design ideas of signal grading dimension reduction, data parallel processing, high-speed transmission of large-capacity data, high-performance beam forming hardware and the like, adopts the broadband self-adaptive digital beam forming technology based on the all-digital array channel according to the requirements of large digital array radar system such as airspace anti-interference and multi-target tracking, and divides the broadband self-adaptive digital beam forming into two-stage signal dimension reduction to realize the real-time response capability of the system under the premise of ensuring the freedom degree of the all-digital array channel spatial signal, can efficiently finish the acquisition, transmission and processing of multi-channel broadband data, can finish the broadband self-adaptive digital beam forming of not less than 200 digital array channels within 1ms, has the beam pointing precision superior to 1 degree (rms), and improves the response real-time of the system, and the formed beam is stable and high in beam pointing accuracy, and can meet the application requirement of a large digital array radar system in a complex environment.
Drawings
Fig. 1 is a schematic view of the module structure of the present invention.
Detailed Description
The technical solution of the present invention is further described below, but the scope of the claimed invention is not limited to the described.
Referring to fig. 1, a high-efficiency wideband digital beam former for hierarchical dimensionality reduction includes a high-speed AD sampling circuit, a primary beam preprocessing module, an optical fiber channel transmission link, and a high-performance wideband digital beam former, where the high-speed AD sampling circuit is connected to the primary beam preprocessing module, and the primary beam preprocessing module is connected to the high-performance wideband digital beam former through the optical fiber channel transmission link;
the high-speed AD sampling circuit comprises a multi-channel high-speed AD sampling chip and is used for completing high-speed sampling of multi-channel intermediate-frequency echo signals;
the primary wave beam preprocessing module comprises an FPGA preprocessing chip and is used for processing the sampling of the multi-channel intermediate frequency echo signals from the high-speed AD sampling circuit to form multi-channel primary digital wave beams;
the optical fiber channel transmission link comprises a multi-path transmission optical fiber, and transmits multi-path primary digital beams processed and formed by the primary beam preprocessing module to a high-performance broadband digital beam former;
the high-performance broadband digital beam former comprises an FPGA processing chip and a DSP chip, and is used for processing multi-channel primary digital beams from an optical fiber channel transmission link to form beams meeting the detection requirement of a large digital array radar system in a complex environment.
Furthermore, the number of AD sampling channels of an AD sampling chip in the AD sampling circuit is not less than 2, the sampling rate is not less than 200MHz, and the number of AD significant digits is not less than 11.
Furthermore, the number of internal logic units of the FPGA preprocessing chip in the primary beam preprocessing module is not less than 40 ten thousand, the number of the internal logic units of the FPGA preprocessing chip is not less than 42Mb, the number of the DSP Slice is not less than 2800, and the number of the GTH13.1Gb/s transceivers is not less than 50.
Furthermore, the transmission speed of the optical fiber single channel of the optical fiber channel transmission link is not less than 6 Gbps.
Furthermore, the number of internal logic units of the FPGA processing chip in the high-performance broadband digital beam former is not less than 69 ten thousand, the number of internal logic units of the FPGA processing chip is not less than 52Mb, the number of DSP Slice is not less than 3600, and the number of GTH13.1Gb/s transceivers is not less than 80.
Furthermore, more than 8 floating-point digital signal processing cores are configured in the DSP chip in the high-performance broadband digital beam former, the dominant frequency is 1.25GHz, and the peak processing capacity is more than 160 GFlos/s.
Furthermore, the high-speed AD sampling circuit and the primary beam preprocessing module are both provided with a plurality of modules.
Furthermore, the high-speed AD sampling circuits are connected with the primary beam preprocessing modules in a one-to-one correspondence mode, and the multi-path echo signals collected by each high-speed AD sampling circuit are transmitted to the corresponding primary beam preprocessing module to be preprocessed.
Furthermore, the plurality of optical fiber signal transmission links correspond to the plurality of primary beam preprocessing modules one to one, and signals preprocessed by the plurality of primary beam preprocessing modules are transmitted to the high-performance broadband digital beam former.
The efficient wideband digital beam former for the hierarchical dimensionality reduction in fig. 1 mainly adopts design ideas such as signal hierarchical dimensionality reduction, data parallel processing, high-capacity data high-speed transmission, high-performance beam forming hardware and the like, and adopts a wideband adaptive digital beam forming technology based on a full-digital array channel according to requirements such as space domain anti-interference and multi-target tracking of a large digital array radar system, so that the real-time response capability of the system is improved, and the wideband adaptive digital beam forming is realized by two-level signal dimensionality reduction on the premise of ensuring the spatial signal freedom of the full-digital array channel; in order to improve the large-capacity data processing and transmission capability of the system, a high-speed multi-channel AD sampling chip is adopted, a high-performance FPGA processing chip is adopted by a primary beam preprocessing module, and a high-performance FPGA + multi-core DSP processing architecture is adopted by a broadband beam former, wherein:
(1) high-speed AD sampling circuit: the device mainly comprises a plurality of multi-channel high-speed AD sampling chips, and is used for completing high-speed sampling of M paths of intermediate frequency echo signals, wherein the number of AD sampling channels is not less than 2, the sampling rate is not less than 200MHz, and the AD effective digit is not less than 11;
(2) a primary beam preprocessing module: the FPGA chip mainly comprises a plurality of high-performance FPGA main processing chips and corresponding peripheral circuits, primary digital beam forming is completed, the M-path signals are reduced to M (M/n), meanwhile, the degree of freedom of space signals formed by space-domain self-adaptive digital beam forming is still guaranteed to be M, the number of logic units in the FPGA chip is not less than 40 ten thousand, the number of internal memory RAMs is not less than 42Mb, the number of DSP Slice is not less than 2800, and the number of transceivers of GTH13.1Gb/s is not less than 50.
(3) Fibre channel transmission link: the system mainly comprises a plurality of transmission optical fibers, and completes high-speed data transmission after primary digital beam forming, wherein the transmission rate of a single channel of the optical fibers is not less than 6 Gbps;
(4) high performance wideband digital beamformer: the system mainly comprises a high-performance FPGA and a multi-core DSP processing circuit, and is used for completing high-efficiency processing of data after a primary beam is formed and forming beams meeting detection requirements of a large digital array radar system in a complex environment, the number of logic units in an FPGA chip is not less than 69 ten thousand, a memory RAM is not less than 52Mb, DSP Slice is not less than 3600, the number of transceivers of GTH13.1Gb/s is not less than 80, 8 or more floating point digital signal processing cores are configured in the DSP chip, the main frequency is 1.25GHz, and the peak processing capacity is greater than 160 GFlops/s.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (9)
1. An efficient wideband digital beamformer with hierarchical dimensionality reduction, comprising: the high-speed AD sampling circuit is connected with the primary beam preprocessing module, and the primary beam preprocessing module is connected with the high-performance broadband digital beam former through the optical fiber channel transmission link;
the high-speed AD sampling circuit comprises a multi-channel high-speed AD sampling chip and is used for completing high-speed sampling of multi-channel intermediate-frequency echo signals;
the primary wave beam preprocessing module comprises an FPGA preprocessing chip and is used for processing the sampling of the multi-channel intermediate frequency echo signals from the high-speed AD sampling circuit to form multi-channel primary digital wave beams;
the optical fiber channel transmission link comprises a multi-path transmission optical fiber, and transmits multi-path primary digital beams processed and formed by the primary beam preprocessing module to a high-performance broadband digital beam former;
the high-performance broadband digital beam former comprises an FPGA processing chip and a DSP chip, and is used for processing multi-channel primary digital beams from an optical fiber channel transmission link to form beams meeting the detection requirement of a large digital array radar system in a complex environment.
2. The high-efficiency wideband digital beamformer with hierarchical dimensionality reduction according to claim 1, wherein: the AD sampling chip in the AD sampling circuit has the advantages that the number of AD sampling channels is not less than 2, the sampling rate is not less than 200MHz, and the AD effective digit is not less than 11.
3. The high-efficiency wideband digital beamformer with hierarchical dimensionality reduction according to claim 1, wherein: the FPGA preprocessing chip in the primary beam preprocessing module has the advantages that the number of internal logic units is not less than 40 ten thousand, the number of internal memory RAMs is not less than 42Mb, the number of DSP Slice is not less than 2800, and the number of GTH13.1Gb/s transceivers is not less than 50.
4. The high-efficiency wideband digital beamformer with hierarchical dimensionality reduction according to claim 1, wherein: the transmission speed of the optical fiber single channel of the optical fiber channel transmission link is not less than 6 Gbps.
5. The high-efficiency wideband digital beamformer with hierarchical dimensionality reduction according to claim 1, wherein: the FPGA processing chip in the high-performance broadband digital beam former has the advantages that the number of internal logic units is not less than 69 ten thousand, the number of internal RAM is not less than 52Mb, the number of DSP Slice is not less than 3600, and the number of GTH13.1Gb/s transceivers is not less than 80.
6. The high-efficiency wideband digital beamformer with hierarchical dimensionality reduction according to claim 1, wherein: the DSP chip in the high-performance broadband digital beam former is internally provided with more than 8 floating-point digital signal processing cores, the main frequency is 1.25GHz, and the peak processing capacity is more than 160 GFlos/s.
7. The high-efficiency wideband digital beamformer with hierarchical dimensionality reduction according to claim 1, wherein: the high-speed AD sampling circuit and the primary beam preprocessing module are multiple.
8. The high-efficiency wideband digital beamformer with hierarchical dimensionality reduction according to claim 7, wherein: the high-speed AD sampling circuits are connected with the first-level beam preprocessing modules in a one-to-one correspondence mode, and the multi-path echo signals collected by each high-speed AD sampling circuit are transmitted to the corresponding first-level beam preprocessing modules to be preprocessed.
9. The highly efficient wideband digital beamformer for hierarchical dimensionality reduction according to any one of claims 7 or 8, wherein: the optical fiber channel transmission links are in one-to-one correspondence with the primary beam preprocessing modules, and transmit signals preprocessed by the primary beam preprocessing modules to the high-performance broadband digital beam former.
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