CN214202073U - IC simulation Debug system - Google Patents
IC simulation Debug system Download PDFInfo
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- CN214202073U CN214202073U CN202023064952.XU CN202023064952U CN214202073U CN 214202073 U CN214202073 U CN 214202073U CN 202023064952 U CN202023064952 U CN 202023064952U CN 214202073 U CN214202073 U CN 214202073U
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Abstract
The utility model discloses an IC simulation Debug system, at least one Debug system, each Debug system comprises a control module and a plurality of Debug modules; the control module comprises a first data transmission submodule, an external transceiving submodule, a first trigger submodule, a transmission channel and a cascade module which is connected with the control submodule by the control submodule; the Debug module comprises a second data transmission submodule, a storage control submodule, a local storage submodule, a second trigger submodule, a shared channel and a probe data receiving submodule; the control module also comprises a first data compression submodule which is simultaneously connected with the first data transmission submodule and the external transceiving submodule; and a second data compression sub-module is also arranged between the first data transmission sub-module and the second data transmission sub-module. Compared with the prior art, the system can better adapt to different scenes, particularly to the multifunctional massive data debugging condition, reasonably distributes the storage space, the processing resources and the transmission channel, and improves the overall efficiency and performance.
Description
Technical Field
The utility model relates to a data communication field especially relates to a IC emulation Debug system.
Background
Along with the development of chip technology, the SOC has an increasingly large scale, the functions of the SOC are increasingly complex, and the simulation verification of the SOC at the design stage is increasingly important, so that the data volume acquired by the probe is increasingly large, which requires a Debug module which can be adapted to large-scale multi-module simulation verification data acquisition and has a large amount of storage space. Therefore, it is an industry research direction to design a debugging system that can flexibly distribute data, fully utilize memory space and have high processing efficiency.
SUMMERY OF THE UTILITY MODEL
The utility model provides a IC emulation Debug system, the resource of having solved prior art Debug module is limited, can't be applied to the problem of large-scale application scene in a flexible way.
The utility model adopts the technical proposal that: an IC simulation Debug system is characterized by comprising at least one debugging system, wherein each debugging system comprises a control module and a plurality of Debug modules connected with the control module;
the Debug module comprises a probe data receiving submodule connected with the simulation verification platform, a storage control submodule connected with the probe data receiving submodule and a local storage submodule connected with the storage control submodule;
the storage control sub-modules of the Debug modules of the same debugging system are connected in series through a shared channel.
Further, the control module comprises a first data transmission submodule, an external receiving and transmitting submodule connected with the first data transmission submodule and used for uploading data, a first trigger submodule connected with the first data transmission submodule, a control submodule connected with the first trigger submodule and the external receiving and transmitting submodule, and a first instruction transmission management submodule connected with the control submodule.
Further, the Debug module includes a second data transmission submodule connected to the first data transmission submodule and the storage control submodule, a second trigger submodule connected to the storage control submodule and the probe data receiving submodule, and a second instruction transmission management submodule connected to the first instruction transmission management submodule and the second trigger submodule.
Further, the control module further comprises a cascade submodule connected with the control submodule.
Furthermore, the control module further comprises a first data compression sub-module, and the first data compression sub-module is simultaneously connected with the first data transmission sub-module and an external transceiving sub-module.
Further, a second data compression sub-module is further arranged between the storage control sub-module and the second data transmission sub-module.
Compared with the prior art, the system adopts a single control module to cooperatively control a plurality of Debug modules, better adapts to different scenes, especially the debugging conditions of multifunctional mass data, has the functions of data sharing and storage management, reasonably distributes storage space, processing resources and transmission channels, and improves the overall efficiency and performance.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments or the prior art descriptions will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.
Fig. 1 is a schematic block diagram of a debugging system according to the present invention.
Detailed Description
In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The application provides an IC simulation Debug system, which comprises at least one Debug system, as shown in figure 1, one Debug system mainly comprises two modules, namely a control module and a plurality of Debug modules, the control module is simultaneously connected with the plurality of Debug modules, so that the maximum data acquisition amount is increased, and the storage space is improved, and the Debug system is suitable for the debugging conditions of especially multifunctional mass data in different scenes better.
Specifically, the control module comprises a first data transmission submodule, an external transceiving submodule, a first trigger submodule, a control submodule, a first instruction transmission management submodule and a cascade submodule, wherein the first data transmission submodule is connected with all the Debug modules to receive data transmitted in the Debug modules, and the first data transmission submodule is connected with the external transceiving submodule, so that the control module processes the data, uploads the data through the external transceiving submodule and receives instruction data from a user of the external transceiving module; meanwhile, the first data transmission submodule is also connected with the first triggering submodule, the control module sets the triggering condition of the first triggering submodule, and when the data meet the triggering condition, the first triggering submodule sends out a triggering signal.
The debugging module interacts with the simulation verification platform under the control of the control module, for example, a clock pause signal is sent or probe data is collected, when a user sets the debugging module to cache the probe data in advance, the debugging module locally stores the collected probe data or sends the collected probe data to other debugging modules of the debugging system for storage according to the setting of the user,
the first instruction transmission management submodule is connected with the control submodule and used for transmitting configuration and control instructions to the Debug module, and when a user instruction is downloaded or is locally and effectively triggered, the control module sends an instruction and transmits the instruction to the Debug module through the first transmission management submodule.
Furthermore, the control submodule is connected with the cascade submodule, every two debugging systems can be cascaded through the cascade submodule, the control module in one debugging system serves as a main control module, and the control submodule uniformly performs instruction transmission, coordination and distribution control.
Furthermore, the control module also comprises a first data compression submodule which is connected with the first data transmission submodule and the external receiving and transmitting submodule simultaneously, when the data volume is large, in order to avoid the limit of the finishing performance of the uploading speed of the control module, the data can be compressed, then the compressed data is uploaded to the upper level (PC and the like) through a transmission channel after being compressed by the external receiving and transmitting submodule, and finally the compressed data is changed into a corresponding oscillogram through graphical processing.
The Debug module comprises a second data transmission submodule, a storage control submodule, a local storage submodule, a second trigger submodule, a probe data receiving submodule, an instruction transmission management submodule and an instruction output submodule, wherein the probe data receiving submodule is responsible for acquiring probe data in the IC simulation verification process; the probe data receiving submodule is connected with the storage control submodule and is connected with the local storage submodule to distribute and store the acquired data.
The probe data receiving submodule is connected with the storage control submodule, and collected probe data are delivered to the storage control submodule to be distributed and stored or directly transmitted. The storage control sub-module is respectively connected with the shared channel module, the local storage sub-module and the second data transmission sub-module, so that the storage control sub-module can share the probe data to the adjacent Debug module or store the probe data locally or directly upload the probe data to the control module. The storage management submodule can also read data from the local storage submodule and the shared channel module and upload the data to a third data transmission module, the data are further transmitted to the control module for processing, and the plurality of Debug modules are connected in series through the shared channel to carry out data cascade connection, so that the local storage submodule can also be transmitted to an adjacent Debug module through the shared channel and distributed by the storage management submodule of the adjacent Debug module.
Furthermore, data cascade connection can be performed between Debug modules of two sides through a shared channel between the two debugging systems, so that the storage capacity of data and the flexibility of distribution are greatly expanded.
The second instruction transmission management submodule is connected with the second triggering submodule, so that a user can set triggering conditions of the second triggering submodule by issuing instructions through the control module.
And a first instruction transmission management submodule in the control module is connected with a second instruction transmission management submodule in each Debug module so that the Debug module can receive the instruction sent from the control module.
Further, a second data compression sub-module (not shown) may be further disposed between the storage control sub-module and the second data transmission sub-module to compress data, so as to increase the data uploading speed.
Based on the Debug system, the control module and the Debug module are respectively provided with a trigger submodule, each trigger submodule comprises a trigger input interface and a trigger output interface and is used for triggering cascade connection, the trigger interface of the control module can be used for cascade connection between systems (namely cascade connection between the Debug systems), the Debug module is used for triggering cascade connection between the inside and the control module, and the trigger conditions are uniformly configured by the control module.
Based on the structure, the user can set two mechanisms for storing and transmitting data through the control module, wherein one mechanism is a trigger type, and the other mechanism is a periodic type.
The trigger type has two conditions, one is that the debugging module is triggered independently, when a user uses one debugging module to complete a task, only the trigger condition in the debugging module needs to be set at the moment, namely, the probe data is directly triggered and detected in the debugging module, and the data or the trigger information meeting the trigger condition is stored or uploaded to the control module on the spot (specifically, whether the data or the trigger information is stored locally or uploaded to the control module and is controlled or set by the user through the control module). When the acquisition probe data uses a plurality of debugging modules, all the data may need to be synthesized for trigger detection, and at this time, the data or trigger out of each debugging module needs to be gathered into the control module for trigger detection.
The periodic type mainly configures a system for a user to fixedly acquire data in a period.
If utilize the utility model discloses when triggering the collection to the bigger system of function, single debug system unsatisfied requirement, at this moment through cascading submodule piece DM _ cascade interface butt joint with two debug systems, when one of them debug system satisfies the trigger condition, send trigger out to this debug system's debugging module beyond, still can send trigger out signal to neighbouring debug system, realize many debug system's cascade cooperation.
Because the utility model discloses a debugging module of each debugging system can adopt a debugging module, also can adopt the mode of two or more than two debugging module cooperations each other, can have a plurality of debugging systems simultaneously again, consequently single debugging system's debugging module quantity can need not set up too much, make single debugging system's complexity reduce, and the debugging system who adopts the debugging chip of the same kind (debuggFpga chip) is whole to be the same, the development degree of difficulty has been reduced, and the production degree of difficulty and the later maintenance degree of difficulty and cost have been reduced. The utility model discloses thereby the biggest data acquisition volume of a plurality of debugging module increase has been connected simultaneously on control module and storage space is promoted to the especially multi-functional a large amount of data debugging condition of different scenes of better adaptation, and there is the data sharing passageway between adjacent debugging module, make collected data can pass through this sharing passageway, nimble distribution storage and processing between the module, in order to reach the purpose that storage space and hardware processing resource among the reasonable, make full use of system improve the treatment effeciency.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. An IC simulation Debug system is characterized by comprising at least one debugging system, wherein each debugging system comprises a control module and a plurality of Debug modules connected with the control module;
the Debug module comprises a probe data receiving submodule connected with the simulation verification platform, a storage control submodule connected with the probe data receiving submodule and a local storage submodule connected with the storage control submodule;
the storage control sub-modules of the Debug modules of the same debugging system are connected in series through a shared channel.
2. The IC emulation Debug system of claim 1, wherein the control module comprises a first data transmission sub-module, an external receiving and transmitting sub-module connected to the first data transmission sub-module for uploading data, a first trigger sub-module connected to the first data transmission sub-module, a control sub-module connected to the first trigger sub-module and the external receiving and transmitting sub-module, and a first instruction transmission management sub-module connected to the control sub-module.
3. The IC emulation Debug system of claim 2, wherein the Debug module comprises a second data transmission sub-module connecting the first data transmission sub-module and a storage control sub-module, a second trigger sub-module connecting the storage control sub-module and a probe data reception sub-module, and a second instruction transmission management sub-module connecting the first instruction transmission management sub-module and the second trigger sub-module.
4. The IC emulation Debug system of claim 1, wherein said control module further comprises a cascade sub-module connected to said control sub-module.
5. The IC emulation Debug system of claim 2, wherein the control module further comprises a first data compression sub-module, and the first data compression sub-module is connected to the first data transmission sub-module and an external transceiver sub-module at the same time.
6. The IC emulation Debug system of claim 1, wherein a second data compression sub-module is further disposed between the storage control sub-module and the second data transmission sub-module.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202023064952.XU CN214202073U (en) | 2020-12-17 | 2020-12-17 | IC simulation Debug system |
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| CN202023064952.XU CN214202073U (en) | 2020-12-17 | 2020-12-17 | IC simulation Debug system |
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| CN214202073U true CN214202073U (en) | 2021-09-14 |
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Effective date of registration: 20230105 Address after: 518000 802, Building 2, Northwest Shenjiu Science and Technology Pioneer Park, intersection of Taohua Road and Binglang Road, Fubao Community, Futian District, Shenzhen, Guangdong Patentee after: Shenzhen Guoweijingrui Technology Co.,Ltd. Address before: 22A, Guoshi building, 1801 Shahe West Road, high tech Zone community, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province Patentee before: GUOWEI GROUP (SHENZHEN) Co.,Ltd. |