CN109148456A - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN109148456A CN109148456A CN201710458822.8A CN201710458822A CN109148456A CN 109148456 A CN109148456 A CN 109148456A CN 201710458822 A CN201710458822 A CN 201710458822A CN 109148456 A CN109148456 A CN 109148456A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
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Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic device, the production method includes: offer semiconductor substrate, the semiconductor substrate includes flash area, and floating gate material layer and the spacer material layer on the floating gate material layer are formed in the semiconductor substrate of the flash area；Form the gate material layers for covering the semiconductor substrate and the spacer material layer；Separation layer window is formed, in the gate material layers with the spacer material layer of exposure lower section；The gate material layers, the spacer material layer and the floating gate material layer of the graphical flash area, to form selection grid stacked structure；The part that first separation layer is located at the separation layer bottom of window is removed, with the first floating gate of the exposure separation layer beneath window.The production method can improve polysilicon resistance and uniformity, make device performance closer to target capabilities, and reduce the cost of manufacture of device.The semiconductor devices has the advantages that similar with electronic device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technique
Embedded flash memory Integration ofTechnology logic process and flash technology, because therefore two techniques different requirements needs
It is balanced between two techniques.In flash cell, due to needing to etch the ONO formed in selection grid is formed
(gate spacer absciss layer) to realize interconnection up and down, control gate (CG) and selection grid (SG) are needed through polysilicon deposition process twice
To be formed.Therefore this to will lead to the logic gate in embedded devices heavy also by polysilicon twice for polysilicon deposition process twice
Product process is formed.And the interface between two-layer polysilicon will increase polysilicon resistance, and cause Rs (sheet resistance, -- i.e.-unit plane
The resistance of product, unit length) consistency variation, this can cause device performance and yield to be deteriorated.
It is therefore desirable to propose a kind of production method of new semiconductor devices, to solve the above problems.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the production method that the present invention proposes a kind of semiconductor devices can improve polysilicon
Resistance and uniformity, make device performance closer to target capabilities, and reduce the cost of manufacture of device.
In order to overcome the problems, such as that presently, there are one aspect of the present invention provides a kind of production method of semiconductor devices, comprising:
Semiconductor substrate is provided, the semiconductor substrate includes flash area, in the semiconductor substrate of the flash area
Upper formation floating gate material layer and the spacer material layer on the floating gate material layer；
Form the gate material layers for covering the semiconductor substrate and the spacer material layer；
Separation layer window is formed, in the gate material layers with the spacer material layer of exposure lower section；
The gate material layers, the spacer material layer and the floating gate material layer of the graphical flash area are with shape
At selection grid stacked structure, the selection grid stacked structure includes the first floating gate on the semiconductor substrate, is located at
The first separation layer on first floating gate and the selection grid on first separation layer, and it is formed in the choosing
Select the separation layer window in grid；
The part that first separation layer is located at the separation layer bottom of window is removed, under the exposure separation layer window
First floating gate of side.
Optionally, in the gate material layers, the spacer material layer and the floating gate of the graphical flash area
Material layer, also forms control gate stacked structure while to form selection grid stacked structure, the control gate stacked structure includes
The second floating gate, the second separation layer and control gate of setting are stacked gradually in the semiconductor substrate of the flash area.
Optionally, the semiconductor substrate further includes logic region, and the gate material layers cover the logic region；
In the gate material layers, the spacer material layer and the floating gate material layer of the graphical flash area,
The gate material layers of the also graphical logic region described while to form the selection grid stacked structure to patrol
It collects and forms logic gate in the semiconductor substrate in region.
Optionally, further includes:
It is formed and covers the semiconductor substrate and the logic gate, the control gate stacked structure and the selection grid heap
The spacer material layer of stack structure；
The graphical clearance material layer, with remove the spacer material layer be located at the semiconductor substrate surface and
The part stated at the top of logic gate, the control gate stacked structure and the selection grid stacked structure retains described in being located at
Part on logic gate, the control gate stacked structure and the selection grid stacked structure side wall, thus in the logic gate
Clearance wall is formed on the side wall of pole, the control gate stacked structure and the selection grid stacked structure.
Optionally, further includes:
It is formed and covers the semiconductor substrate, the logic gate, the control gate stacked structure and the selection grid heap
The silicide shielding layer of stack structure；
The graphical silicide shielding layer, to expose the quasi- region for forming silicide, the quasi- area for forming silicide
Domain includes at the top of the logic gate, at the top of control gate, separation layer bottom of window described in the selection grid stacked structure and
Source-drain area；
Metal silicide is formed in the quasi- region for forming silicide；
Remove the silicide shielding layer.
Optionally, in the process removal of the graphical spacer material layer and/or the graphical silicide shielding layer
The separation layer is located at the part of the separation layer bottom of window.
Optionally, the logic gate, the control gate and the selection grid are made of single level polysilicon.
The production method of semiconductor device according to the invention, by being formed first below exposure in selection grid stacked structure
The separation layer window of floating gate, so as to realize gate electrode function by the first floating gate, and there is no need to redeposited additional grids
Material layer fills separation layer window so that selection grid in structure the first floating gate and selection grid no longer due to needing to deposit two
Layer gate material layers and there are interface, cause to occur such as to increase polysilicon resistance, Rs consistency is deteriorated, device performance and yield
The problems such as variation.
Further, the production method of semiconductor device according to the invention forms institute while forming logic gate
Separation layer window is stated, and the formation of logic gate, control gate, selection grid only needs one layer of gate material layers of deposition, therefore logic gate
There is no the deposition interfaces that grid material is formed twice in extremely, to overcome since there are such as increase polycrystalline caused by interface
The problems such as silicon resistor, Rs consistency variation, device performance and yield are deteriorated, and since logic gate and separation layer window are same
One step is formed, and separation layer window is formed without independent step, to save one layer of light shield, reduces being fabricated to for device
This.
Another aspect of the present invention provides a kind of semiconductor devices, which includes: semiconductor substrate, described partly to lead
Body substrate includes flash area, and selection grid stacked structure, the selection are formed in the semiconductor substrate of the flash area
Grid stacked structure includes the first floating gate in the semiconductor substrate, the first isolation on first floating gate
Layer, and the selection grid on first separation layer are formed with sudden and violent in the selection grid and first separation layer
The separation layer window of dew lower section first floating gate.
Optionally, control gate stacked structure, the control gate are also formed in the semiconductor substrate of the flash area
Stacked structure includes the second floating gate, the second separation layer and control gate for stacking gradually setting on the semiconductor substrate.
Optionally, the semiconductor devices further include: logic region is formed in the semiconductor substrate of the logic region
There is logic gate.
Optionally, described at the top of the logic gate, at the top of control gate and in the selection grid stacked structure
Separation layer bottom of window is formed with silicide.
Optionally, the logic gate, the control gate and the selection grid are made of single level polysilicon.
Semiconductor device according to the invention, by the isolation for forming the first floating gate below exposure in selection grid stacked structure
Layer window, so as to realize gate electrode function by the first floating gate, and there is no need to redeposited additional gate material layers to fill out
Fill separation layer window so that selection grid in structure the first floating gate and selection grid no longer due to needing to deposit two layers of grid material
Layer and there are interface, cause to occur increasing polysilicon resistance, Rs consistency is deteriorated, device performance and yield are deteriorated etc. asks
Topic.
Further, semiconductor device according to the invention, since logic gate, control gate, selection grid are more by single layer
Crystal silicon is constituted, therefore there is no interfaces caused by deposition twice grid material, to overcome since there are all caused by interface
Such as increase the problems such as polysilicon resistance, Rs consistency variation, device performance and yield are deteriorated, so that device has improved polycrystalline
Silicon resistor and uniformity, performance is closer to target capabilities, and cost of manufacture reduces.
Further aspect of the present invention provides a kind of electronic device comprising semiconductor devices as described above and with described half
The electronic building brick that conductor device is connected.
Electronic device proposed by the present invention due to above-mentioned semiconductor device, thus has the advantages that similar.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A -1F shows a kind of production method of embedded flash memory device at present and successively implements the obtained semiconductor of each step
The diagrammatic cross-section of device；
Fig. 2 shows the step flow charts of the production method of semiconductor devices according to an embodiment of the present invention
The production method that Fig. 3 A~Fig. 3 E shows semiconductor devices according to an embodiment of the present invention is successively implemented respectively
The diagrammatic cross-section of the obtained semiconductor devices of step；
Fig. 4 shows the schematic cross sectional view of semiconductor devices according to an embodiment of the present invention；
Fig. 5 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated phase from beginning to end
Identical element is indicated with appended drawing reference.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further include using with
The different orientation of device in operation.For example, then, being described as " below other elements " if the device in attached drawing is overturn
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
There is polysilicon deposition process twice as previously described, because being formed there are control gate and selection grid, and two layers of polycrystalline
Boundary layer between silicon will increase polysilicon resistance, and Rs consistency is caused to be deteriorated, this can cause device performance and yield to be deteriorated,
For a better understanding of the present invention, Figure 1A~Fig. 1 F is combined to carry out a kind of production method of embedded flash memory device at present first
Explanation.
As shown in Figure 1A~Fig. 1 F, the production method of current embedded flash memory device includes:
Firstly, as shown in Figure 1A, providing semiconductor substrate 100, the semiconductor substrate 100 includes at least logic region
100A and flash area 100B.Grid oxygen is formed on the semiconductor substrate of the logic region 100A and flash area 100B
Change layer 101, wherein the grid oxic horizon 101 of logic region 100A and flash area 100B can according to need with different thickness
Degree.Floating gate material layer 102 and the isolation on floating gate material layer 102 are formed in the semiconductor substrate of flash area 100B
Material layer 103.Spacer material layer 103 preferably uses ONO (oxidenitride oxide) structure, with good interface
Performance, and dielectric properties with higher.
Then, as shown in Figure 1B, covering semiconductor substrate 100 and floating gate material layer 102 and spacer material layer 103 are formed
First grid material layer 1040.First grid material layer 1040 is used to form logic gate, selection grid and control gate, the first grid
Pole material layer 1040 illustratively uses polysilicon.
Then, as shown in Figure 1 C, in the first grid material layer 1040 of flash area and spacer material layer 103 formed every
Absciss layer window 105, the separation layer window 105 are formed in the quasi- region for forming selection grid, and the floating gate material layer of exposure lower section
102。
Then, as shown in figure iD, formed and cover the first grid material layer 1040 and fill the separation layer window 105
Second grid material layer 1041.Second grid material layer 1041 is illustratively polysilicon.
Then, as referring to figure 1E, logic gate 106 is formed in the logic region.I.e. by photoetching, etching technics to patrolling
The first grid material layer 1040 and second grid material layer 1041 for collecting region 100A are patterned, to form logic gate
106.Logic gate 106 includes two layers of gate material layers, for example including two-layer polysilicon layer, in this way between the gate material layers
It is formed with interface, to increase polysilicon resistance, Rs consistency is caused to be deteriorated, device performance and yield is caused to be deteriorated.
Then, as shown in fig. 1F, control gate stacked structure 107 is formed in the flash area 100B and selection grid stacks
Structure 108.Pass through first grid material layer 1040, the second grid material layer of photoetching, etching technics to flash area 100B
1041, spacer material layer 103 and floating gate material layer 102 are patterned, to form control gate stacked structure 107 and selection grid heap
Stack structure 108.Due to the first floating gate 102A of the exposure of separation layer window 105 before lower section in selection grid stacked structure 108,
The selection grid 104 of first floating gate 102A and top connects in selection grid stacked structure 108, so as to the use of alternatively grid.
Current embedded flash memory device production method, opened due to needing special step to form separation layer window every
Absciss layer, to realize the interconnection of selection grid upper and lower level, it is therefore desirable to which gate material layers (such as polysilicon) deposit twice, to lead
Foregoing problems are caused, the present invention is based on this, a kind of production method of semiconductor devices is provided, for making embedded flash memory device,
As shown in Fig. 2, the production method includes: step 201, semiconductor substrate is provided, the semiconductor substrate includes at least logic area
Domain and flash area, in the semiconductor substrate of the flash area formed floating gate material layer and be located at the floating gate material layer it
On spacer material layer；Step 202, formed cover the semiconductor substrate and the spacer material layer for making logic gate
Pole, control gate and selection grid gate material layers；Step 203, the graphical gate material layers are in the logic region shape
At logic gate, and separation layer window, separation layer window position are formed in the gate material layers of the flash area
In the quasi- region for forming selection grid, and expose the part spacer material layer in the quasi- region for forming selection grid；Step
Rapid 204, the gate material layers, the spacer material layer and the floating gate material layer of the graphical flash area, with shape
At control gate stacked structure and selection grid stacked structure；Step 205, the isolated material of the separation layer bottom of window is removed
Layer.
The production method of semiconductor device according to the invention is forming logic gate when making embedded flash memory device
Separation layer window is formed while pole, and by a part of the separation layer window alternatively grid stacked structure, and without
Filling, therefore due to only including side gate material layers and no longer bounded face in logic gate, to overcome since there are boundaries
Such as increase the problems such as polysilicon resistance, Rs consistency variation, device performance and yield are deteriorated caused by face, and due to logic
Grid and separation layer window are formed in same step, and separation layer window is formed without independent step, to save one layer of light
Cover, reduces the cost of manufacture of device.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiments.
Embodiment one
It does below with reference to production method of Fig. 3 A~Fig. 3 E to the semiconductor devices of an embodiment of the present invention and retouches in detail
It states.
Firstly, providing semiconductor substrate 300, the semiconductor substrate 300 includes at least logic region 300A and flash memory area
Domain 300B.Grid oxic horizon 301 is formed on the semiconductor substrate of the logic region 300A and flash area 300B, is being dodged
It deposits and is formed with floating gate material layer 302 and the isolated material on floating gate material layer 302 in the semiconductor substrate of region 100B
Layer 303, it is as shown in Figure 3A to be formed by structure.
Wherein, semiconductor substrate 300 can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.In addition, can also be formed in the semiconductor substrate such as
The isolation structure of STI (shallow trench isolation).As an example, in the present embodiment, the constituent material of semiconductor substrate 300 is selected single
Crystal silicon.
Grid oxic horizon 301 can be formed by thermal oxidation method, such as the thermal oxidation methods such as furnace process are formed.And logic
The grid oxic horizon 101 of region 300A and flash area 300B can according to need with different thickness.
Floating gate material layer 302 illustratively uses polycrystalline silicon material, can be by can choose molecular beam epitaxy
(MBE), Metallo-Organic Chemical Vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) with
And one of selective epitaxy growth (SEG) is formed.
Spacer material layer 303 preferably uses ONO (oxidenitride oxide) structure, with good interface characteristics
Can, and dielectric properties with higher.Spacer material layer 303 can pass through PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition
Product), the techniques such as ALD (atomic layer deposition) are formed.
Then, formed cover the semiconductor substrate 300 and the spacer material layer 303 for make logic gate,
The gate material layers 304 of control gate and selection grid, it is as shown in Figure 3B to be formed by structure.
Gate material layers 304 illustratively use polycrystalline silicon material, can be by can choose molecular beam epitaxy
(MBE), Metallo-Organic Chemical Vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) with
And one of selective epitaxy growth (SEG) is formed.In the present embodiment, the thickness of gate material layers 304 and logic gate, control
Grid processed and the thickness of selection grid are corresponding, that is, the first grid material layer in the thickness of gate material layers 304 and aforementioned production method
The sum of 1040 and the thickness of second grid material layer 1041 correspond to.Illustratively, gate material layers 304 with a thickness of
Then, the graphical gate material layers 304 to be to form logic gate 305 in the logic region 300A, and
Separation layer window 306 is formed in the gate material layers 304 of the flash area 300B, the separation layer window 306 is located at
The quasi- region for forming selection grid, and the exposure quasi- part spacer material layer 303 formed in selection gate region, institute's shape
At structure it is as shown in Figure 3 C.
Illustratively, the forming process of logic gate 305 and separation layer window 306 are as follows: firstly, in gate material layers 304
It is upper to form patterned photoresist layer, the patterned photoresist layer define logic gate 305 and 306 shape of separation layer window and
Position；It then, is exposure mask by suitable dry etch process etching grid material layer 304 using the patterned photoresist layer,
And the surface of grid oxic horizon 301 and spacer material layer 303 is stopped at, to form logic gate in the logic region 300A
305, and separation layer window 306 is formed in the gate material layers 304 of the flash area 300B.
It is understood that in this step, dry etch process etching speed with higher to gate material layers
Rate, and there is lower etch rate to oxide layers such as spacer material layers 303, therefore in this step, separation layer window
The separation layer of 306 bottoms will not be opened.
Then, the gate material layers 304, the spacer material layer 303 and the institute of the graphical flash area 300B
Floating gate material layer 302 is stated, to form selection grid stacked structure 307 and control gate stacked structure 308, is formed by structure such as Fig. 3 D
It is shown.
Illustratively, the forming process of selection grid stacked structure 307 and control gate stacked structure 308 are as follows: firstly, partly leading
Patterned photoresist layer is formed in body substrate 300, which covers logic region 300A, and in flash memory area
Domain 300B defines the location and shape of selection grid stacked structure 307 and control gate stacked structure 308, and the filling separation layer
Window 306；Then, pass through the gate material layers 304 in suitable dry etching etching flash area 300B, spacer material layer
303 and floating gate material layer 302, and 301 surface of grid oxic horizon (i.e. floating gate oxide layers) is stopped at, to form selection grid stacking
Structure 307 and control gate stacked structure 308.
Finally, the shape on the side wall of the logic gate 305, selection grid stacked structure 307 and control gate stacked structure 308
At clearance wall 309, and at the top of source-drain area and logic gate, at the top of control gate and the separation layer bottom of window formed metal
Silicide 310 is formed by structure as shown in FIGURE 3 E.
Illustratively, the forming process of clearance wall 309 are as follows: cover the semiconductor substrate 300 firstly, being formed and described patrol
Collect the spacer material layer of grid 305, the selection grid stacked structure 307 and control gate stacked structure 308；Then, graphically
The clearance material layer is located at the semiconductor substrate surface and described states logic gate to remove the spacer material layer
Part at the top of pole, the control gate stacked structure and the selection grid stacked structure retains and states logic gate positioned at described
Part on pole, the control gate stacked structure and the selection grid stacked structure side wall, thus in the logic gate, described
Clearance wall 309 is formed on the side wall of control gate stacked structure and the selection grid stacked structure.
Illustratively, the forming process of the metal silicide 310 are as follows: cover the semiconductor substrate firstly, being formed
300, the logic gate 305, the selection grid stacked structure 307 and control gate stacked structure 308 silicide shielding layer；So
Afterwards, the graphical silicide shielding layer, to expose the quasi- region for forming silicide, the quasi- region for forming silicide includes
At the top of the logic gate, at the top of control gate, separation layer bottom of window and logic area described in the selection grid stacked structure
The source-drain area of source electrode, drain electrode and flash area in domain,；Then, metallic silicon is formed in the quasi- region for forming silicide
Compound；Finally, removing the silicide shielding layer.Beaten in the surface of logic gate, the surface for controlling grid, selection gate
The surface of the intermediate region and source and drain areas of opening separation layer forms metal.Metal silicide is, for example, NiSi, passes through metal
The techniques such as deposition, annealing are formed, and details are not described herein.
In the present embodiment, logic gate 305 only includes one layer of gate material layers, therefore interface is not present, and also would not
The problems such as in the presence of polysilicon resistance, Rs consistency variation, device performance and yield variation is such as increased as caused by interface.
In the present embodiment, the selection grid stacked structure 307 includes the first floating gate in the semiconductor substrate
302A, the first separation layer 303A on the first floating gate 302A and on the first separation layer 303A
Selection grid 304A is formed with first floating gate below exposure in the selection grid 304A and the first separation layer 303A
The separation layer window 306A of 302A.That is, in the present embodiment, the humping structure of selection grid stacked structure 307, in other words in same
The planform of bottom double tower point, that wherein play function in selection grid stacked structure is the first floating gate 302A, and height is equivalent
In the height of the first floating gate 302A.
In the present embodiment, control gate stacked structure 308 includes the second floating gate 302B on semiconductor substrate, position
The second separation layer 303B on the second floating gate 302B, and the control gate 304B on the second separation layer 303B.Control
Grid 304B processed only includes one layer of gate material layers, therefore interface is not present, and would not also exist and such as increase as caused by interface
The problems such as adding polysilicon resistance, Rs consistency variation, device performance and yield to be deteriorated.
It is understood that in the present embodiment, optionally, the first separation layer 303A is located at the first separation layer 303A
The part of bottom is removed in clearance wall etching and/or the etching of silicide shielding layer, so as to the first of its exposing
Silicide is formed on floating gate 302A, realizes the interconnection with superstructure.Certainly, in other embodiments, can also be patrolled in formation
Among the step of volume grid and separation layer window or later by additional etch step remove the first separation layer 303A positioned at every
The part of 306 bottom of absciss layer window, or among the step of forming control gate stacked structure, selection grid stacked structure or later
The part that the first separation layer 303A is located at 306 bottom of separation layer window is removed by additional etch step.
It will also be appreciated that grid oxic horizon 301 is located at logic gate 305, selection grid stacked structure 307 and control gate
Part except stacked structure 308, can in the forming process of the clearance wall 309 and/or the silicide 310 or later
It is removed.
So far, the processing step implemented according to the method for the embodiment of the present invention is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include other needs later
The step of, such as well region injection, ion doping, it is included in the range of this implementation production method.
According to the production method of the semiconductor devices of the present embodiment, when making embedded flash memory device, logic is being formed
Separation layer window is formed while grid, and the formation of logic gate, control gate, selection grid only needs one layer of grid material of deposition
Layer, therefore there is no interfaces in logic gate, to overcome since there are such as increase polysilicon resistance, Rs caused by interface
The problems such as consistency variation, device performance and yield are deteriorated, and since logic gate and separation layer window are in same step shape
At, separation layer window is formed without independent step, thus save one layer of light shield, reduce the cost of manufacture of device.That is, root
According to the production method of the semiconductor devices of embodiment, polysilicon resistance and uniformity are improved, makes device performance closer to target
Performance, and reduce the cost of manufacture of device.
Embodiment two
The present invention also provides a kind of semiconductor devices, as shown in figure 4, the semiconductor devices includes: semiconductor substrate 400,
The semiconductor substrate 400 includes at least logic region 400A and flash area 400B, in logic region 400A and flash area
Grid oxic horizon 401 is formed in the semiconductor substrate of 400B；It is formed with and patrols in the semiconductor substrate of the logic region 400A
Collect grid 402, and the clearance wall 403 on 402 side wall of logic gate and the silicide 404 positioned at logic gate two sides；
Selection grid stacked structure 405 and control gate stacked structure 406 are formed in the semiconductor substrate of the flash area 400B；Institute
Selection grid stacked structure 405 is stated to include the first floating gate 407A on the grid oxic horizon 401, be located at first floating gate
The first separation layer 408A on the 407A and selection grid 409A on the first separation layer 408A, wherein described first
Separation layer 408A and selection grid 409A is located at the lateral area on the surface the first floating gate 407A and surrounds sudden and violent positioned at intermediate region
The separation layer window 410 of dew lower section the first floating gate 407A, namely in the first separation layer 408A and selection grid 409A
Be formed with exposure lower section the first floating gate 407A separation layer window 410,410 bottom of separation layer window be formed with it is described
The silicide 404 of first floating gate 407A contact.The control gate stacked structure 406 includes being located on grid oxic horizon 401
Second floating gate 407B, the second separation layer 408B on the second floating gate 407B and be located at the second separation layer 408B
On control gate 409B, be formed with silicide 404 at the top of the control gate 409B；
In addition, being also formed with silication in the source-drain area of the selection grid stacked structure 405 and control gate stacked structure 406
Object 404.
Wherein semiconductor substrate 400 can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode are also possible to the metal interconnection structure, etc. being electrically connected with transistor.
Further, grid oxic horizon 401 can use material commonly used in the art, such as silica, logic gate
402, the first floating gate 407A, the second floating gate 407B and selection grid 409A and control gate 409B can be using polysilicons etc. often
Use material.And the first separation layer 408A and the second separation layer 408B then preferably use ONO structure, that is, oxide, nitride,
Oxide structure both has good interface performance, it may have higher dielectric constant in this way.Silicide 404 is illustratively adopted
Use NiSi.
According to the semiconductor devices of the present embodiment, there is improved polysilicon resistance and uniformity, performance is closer to target
Performance, and cost of manufacture reduces.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic device, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, which includes: semiconductor substrate, and the semiconductor substrate includes flash area,
Selection grid stacked structure is formed in the semiconductor substrate of the flash area, the selection grid stacked structure includes being located at institute
State the first floating gate in semiconductor substrate, the first separation layer on first floating gate, and be located at described first every
Selection grid on absciss layer is formed with the separation layer of first floating gate below exposure in the selection grid and the separation layer
Window.
Wherein, semiconductor substrate can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode are also possible to the metal interconnection structure, etc. being electrically connected with transistor.In the present embodiment, semiconductor substrate
Constituent material select monocrystalline silicon.
Optionally, control gate stacked structure, the control gate are also formed in the semiconductor substrate of the flash area
Stacked structure includes the second floating gate, the second separation layer and control gate for stacking gradually setting on the semiconductor substrate.
Optionally, the semiconductor devices further include: logic region is formed in the semiconductor substrate of the logic region
There is logic gate.
Optionally, described at the top of the logic gate, at the top of control gate and in the selection grid stacked structure
Separation layer bottom of window is formed with silicide.
Optionally, the logic gate, the control gate and the selection grid are made of single level polysilicon.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.
Wherein, Fig. 5 shows the example of mobile phone.The outside of mobile phone 500 is provided with including the display portion in shell 501
502, operation button 503, external connection port 504, loudspeaker 505, microphone 506 etc..
The electronic device of the embodiment of the present invention, since the semiconductor devices for being included has improveds polysilicon resistance and equal
Even property, performance is closer to target capabilities, and cost of manufacture reduces.Therefore the electronic device equally has the advantages that similar.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of production method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate includes flash area, the shape in the semiconductor substrate of the flash area
At floating gate material layer and the spacer material layer on the floating gate material layer；
Form the gate material layers for covering the semiconductor substrate and the spacer material layer；
Separation layer window is formed, in the gate material layers with the spacer material layer of exposure lower section；
The gate material layers, the spacer material layer and the floating gate material layer of the graphical flash area, to be formed
Selection grid stacked structure, the selection grid stacked structure include the first floating gate on the semiconductor substrate, are located at institute
The first separation layer on the first floating gate and the selection grid on first separation layer are stated, and is formed in the selection
The separation layer window in grid；
The part that first separation layer is located at the separation layer bottom of window is removed, with the exposure separation layer beneath window
First floating gate.
2. the production method of semiconductor devices according to claim 1, which is characterized in that
In the gate material layers, the spacer material layer and the floating gate material layer of the graphical flash area, with shape
At control gate stacked structure is also formed while selection grid stacked structure, the control gate stacked structure is included in the flash memory area
The second floating gate, the second separation layer and control gate of setting are stacked gradually in the semiconductor substrate in domain.
3. the production method of semiconductor devices according to claim 2, which is characterized in that
The semiconductor substrate further includes logic region, and the gate material layers cover the logic region；
In the gate material layers, the spacer material layer and the floating gate material layer of the graphical flash area, with shape
At the gate material layers of the logic region also graphical while the selection grid stacked structure in the logic area
Logic gate is formed in the semiconductor substrate in domain.
4. the production method of semiconductor devices according to claim 3, which is characterized in that further include:
It is formed and covers the semiconductor substrate and the logic gate, the control gate stacked structure and selection grid stacking knot
The spacer material layer of structure；
The graphical clearance material layer is located at the semiconductor substrate surface and described to remove the spacer material layer
Part at the top of logic gate, the control gate stacked structure and the selection grid stacked structure retains and is located at the logic gate
Part on pole, the control gate stacked structure and the selection grid stacked structure side wall, thus in the logic gate, described
Clearance wall is formed on the side wall of control gate stacked structure and the selection grid stacked structure.
5. the production method of semiconductor devices according to claim 4, which is characterized in that further include:
It is formed and covers the semiconductor substrate, the logic gate, the control gate stacked structure and selection grid stacking knot
The silicide shielding layer of structure；
The graphical silicide shielding layer, to expose the quasi- region for forming silicide, the quasi- region packet for forming silicide
Include at the top of the logic gate, at the top of control gate, separation layer bottom of window and source and drain described in the selection grid stacked structure
Area；
Metal silicide is formed in the quasi- region for forming silicide；
Remove the silicide shielding layer.
6. the production method of semiconductor devices according to claim 5, which is characterized in that
First separation layer position is removed in the graphical spacer material layer and/or the graphical silicide shielding layer
In the part of the separation layer bottom of window.
7. the production method of semiconductor devices according to claim 3, which is characterized in that the logic gate, the control
Grid processed and the selection grid are made of single level polysilicon.
8. a kind of semiconductor devices characterized by comprising semiconductor substrate, the semiconductor substrate include flash area,
Selection grid stacked structure is formed in the semiconductor substrate of the flash area, the selection grid stacked structure includes positioned at described
The first floating gate in semiconductor substrate, the first separation layer on first floating gate, and it is located at first isolation
Selection grid on layer is formed with the isolation of first floating gate below exposure in the selection grid and first separation layer
Layer window.
9. semiconductor devices according to claim 8, which is characterized in that in the semiconductor substrate of the flash area also
It is formed with control gate stacked structure, the control gate stacked structure includes stack gradually setting on the semiconductor substrate
Two floating gates, the second separation layer and control gate.
10. semiconductor devices according to claim 9, which is characterized in that further include: logic region, in the logic area
Logic gate is formed in the semiconductor substrate in domain.
11. semiconductor devices according to claim 10, which is characterized in that at the top of the logic gate, control gate top
Portion and silicide is formed in the separation layer bottom of window in the selection grid stacked structure.
12. semiconductor devices according to claim 10, which is characterized in that the logic gate, the control gate and institute
Selection grid is stated to be made of single level polysilicon.
13. a kind of electronic device, which is characterized in that including the semiconductor devices as described in any one in claim 8-12
And the electronic building brick being connect with the semiconductor devices.
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