CN109148456B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
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- CN109148456B CN109148456B CN201710458822.8A CN201710458822A CN109148456B CN 109148456 B CN109148456 B CN 109148456B CN 201710458822 A CN201710458822 A CN 201710458822A CN 109148456 B CN109148456 B CN 109148456B
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a flash memory area, and a floating gate material layer and an isolation material layer positioned above the floating gate material layer are formed on the semiconductor substrate of the flash memory area; forming a gate material layer covering the semiconductor substrate and the isolation material layer; forming an isolation layer window in the gate material layer to expose the underlying isolation material layer; patterning the gate material layer, the isolation material layer and the floating gate material layer of the flash memory region to form a select gate stack structure; and removing the part of the first isolation layer at the bottom of the isolation layer window to expose the first floating gate below the isolation layer window. The manufacturing method can improve the resistance and uniformity of the polysilicon, make the performance of the device closer to the target performance and reduce the manufacturing cost of the device. The semiconductor device and the electronic apparatus have similar advantages.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
Embedded flash technology integrates logic and flash technologies, which require balancing between the two technologies due to their different requirements. In the flash memory cell, since ONO (gate spacer) that has been formed needs to be etched in the formation of the select gate to realize upper and lower interconnections, the Control Gate (CG) and the Select Gate (SG) need to be formed through two polysilicon deposition processes. These two polysilicon deposition processes may result in logic gates in embedded devices also being formed by the two polysilicon deposition processes. The interface between the two polysilicon layers increases the polysilicon resistance and causes Rs (sheet resistance — i.e., -resistance per unit area, per unit length) uniformity to be poor, which may cause device performance and yield to be poor.
Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to solve the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which can improve the resistance and uniformity of polycrystalline silicon, make the performance of the device closer to the target performance and reduce the manufacturing cost of the device.
In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a flash memory area, and a floating gate material layer and an isolation material layer positioned above the floating gate material layer are formed on the semiconductor substrate of the flash memory area;
forming a gate material layer covering the semiconductor substrate and the isolation material layer;
forming an isolation layer window in the gate material layer to expose the underlying isolation material layer;
patterning the gate material layer, the isolation material layer and the floating gate material layer of the flash memory region to form a select gate stack structure, the select gate stack structure including a first floating gate over the semiconductor substrate, a first isolation layer over the first floating gate and a select gate over the first isolation layer, and the isolation layer window formed in the select gate;
and removing the part of the first isolation layer at the bottom of the isolation layer window to expose the first floating gate below the isolation layer window.
Optionally, the gate material layer, the isolation material layer, and the floating gate material layer in the flash memory region are patterned to form a select gate stack structure and a control gate stack structure, where the control gate stack structure includes a second floating gate, a second isolation layer, and a control gate that are sequentially stacked on a semiconductor substrate in the flash memory region.
Optionally, the semiconductor substrate further comprises a logic region, and the gate material layer covers the logic region;
and patterning the gate material layer, the isolation material layer and the floating gate material layer of the flash memory region to form the select gate stack structure, and simultaneously patterning the gate material layer of the logic region to form a logic gate on the semiconductor substrate of the logic region.
Optionally, the method further comprises:
forming a spacer material layer covering the semiconductor substrate and the logic gate, the control gate stack structure and the select gate stack structure;
and patterning the gap material layer to remove the parts of the gap wall material layer on the surface of the semiconductor substrate and the tops of the logic gate, the control gate stack structure and the selection gate stack structure and to reserve the parts on the side walls of the logic gate, the control gate stack structure and the selection gate stack structure, so as to form a gap wall on the side walls of the logic gate, the control gate stack structure and the selection gate stack structure.
Optionally, the method further comprises:
forming a silicide shielding layer covering the semiconductor substrate, the logic gate, the control gate stack structure and the select gate stack structure;
imaging the silicide shielding layer to expose a region to be formed with silicide, wherein the region to be formed with silicide comprises the top of the logic gate, the top of the control gate, the bottom of the isolation layer window in the selective gate stack structure and a source drain region;
forming a metal silicide in the region to be formed with the silicide;
and removing the silicide shielding layer.
Optionally, a portion of the spacer at the bottom of the spacer window is removed during the patterning of the spacer material layer and/or the patterning of the silicide blocking layer.
Optionally, the logic gate, the control gate and the select gate are all made of a single layer of polysilicon.
According to the manufacturing method of the semiconductor device, the isolating layer window exposing the first floating gate below is formed in the selection gate stacking structure, so that a gate function can be realized through the first floating gate, and an additional gate material layer does not need to be deposited to fill the isolating layer window, so that the first floating gate and the selection gate in the selection gate pair structure do not have an interface due to the fact that two gate material layers need to be deposited, and problems such as increase of polycrystalline silicon resistance, deterioration of Rs consistency, deterioration of device performance and yield and the like occur.
Furthermore, according to the manufacturing method of the semiconductor device, the isolation layer window is formed while the logic gate is formed, and only one gate material layer is required to be deposited for forming the logic gate, the control gate and the selection gate, so that an interface formed by depositing the gate material twice in the logic gate is avoided, the problems of increasing polycrystalline silicon resistance, deteriorating Rs consistency, deteriorating device performance and yield and the like caused by the existence of the interface are solved, and the isolation layer window is formed in the same step without a separate step, so that a layer of photomask is saved, and the manufacturing cost of the device is reduced.
Another aspect of the present invention provides a semiconductor device, including: the semiconductor substrate comprises a flash memory area, a selection gate stack structure is formed on the semiconductor substrate of the flash memory area, the selection gate stack structure comprises a first floating gate positioned on the semiconductor substrate, a first isolation layer positioned above the first floating gate and a selection gate positioned above the first isolation layer, and isolation layer windows exposing the first floating gate below are formed in the selection gate and the first isolation layer.
Optionally, a control gate stack structure is further formed on the semiconductor substrate in the flash memory region, and the control gate stack structure includes a second floating gate, a second isolation layer, and a control gate, which are sequentially stacked on the semiconductor substrate.
Optionally, the semiconductor device further comprises: and a logic region having a logic gate formed on the semiconductor substrate of the logic region.
Optionally, a silicide is formed on top of the logic gate, on top of the control gate, and in the select gate stack structure at the bottom of the isolation layer window.
Optionally, the logic gate, the control gate and the select gate are all made of a single layer of polysilicon.
According to the semiconductor device, the isolating layer window exposing the first floating gate is formed in the selection gate stacking structure, so that a gate function can be realized through the first floating gate, and an additional gate material layer does not need to be deposited to fill the isolating layer window, so that the first floating gate and the selection gate in the selection gate pair structure do not have an interface due to the fact that two gate material layers need to be deposited, and problems such as increase of polycrystalline silicon resistance, deterioration of Rs consistency, deterioration of device performance and yield and the like occur.
Further, according to the semiconductor device of the present invention, since the logic gate, the control gate and the select gate are all made of single polysilicon, there is no interface caused by depositing the gate material twice, thereby overcoming the problems such as increased polysilicon resistance, deteriorated Rs uniformity, deteriorated device performance and yield, etc. caused by the existence of the interface, so that the device has improved polysilicon resistance and uniformity, performance closer to the target performance, and reduced manufacturing cost.
A further aspect of the invention provides an electronic device comprising a semiconductor device as described above and an electronic component connected to the semiconductor device.
The electronic device provided by the invention has similar advantages due to the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1A-1F are schematic cross-sectional views of a semiconductor device obtained by implementing steps in sequence in a conventional method for manufacturing an embedded flash memory device;
FIG. 2 is a flow chart illustrating steps in a method of fabricating a semiconductor device according to an embodiment of the present invention
Fig. 3A to 3E are schematic cross-sectional views of a semiconductor device obtained by sequentially performing steps according to a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4 shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention;
fig. 5 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
As mentioned above, since there are two polysilicon deposition processes for forming the control gate and the select gate, and the interface layer between two polysilicon layers may increase the polysilicon resistance and cause Rs uniformity to be poor, which may cause device performance and yield to be poor, for better understanding of the present invention, a method for manufacturing an embedded flash memory device will be described first with reference to fig. 1A to 1F.
As shown in fig. 1A to 1F, the current method for manufacturing an embedded flash memory device includes:
first, as shown in fig. 1A, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including at least a logic region 100A and a flash memory region 100B. A gate oxide layer 101 is formed on the semiconductor substrate of the logic area 100A and the flash area 100B, wherein the gate oxide layer 101 of the logic area 100A and the flash area 100B may have different thicknesses as required. A floating gate material layer 102 and a separation material layer 103 located over the floating gate material layer 102 are formed on the semiconductor substrate of the flash memory region 100B. The isolation material layer 103 preferably has an ONO (oxide-nitride-oxide) structure, which has good interface properties and high dielectric properties.
Next, as shown in fig. 1B, a first gate material layer 1040 is formed covering the semiconductor substrate 100 and the floating gate material layer 102 and the isolation material layer 103. The first gate material layer 1040 is used to form a logic gate, a select gate and a control gate, and the first gate material layer 1040 exemplarily uses polysilicon.
Next, as shown in fig. 1C, a spacer window 105 is formed in the first gate material layer 1040 and the spacer material layer 103 of the flash memory region, the spacer window 105 is formed in the region where the select gate is to be formed, and the floating gate material layer 102 underneath is exposed.
Next, as shown in fig. 1D, a second gate material layer 1041 is formed covering the first gate material layer 1040 and filling the isolation layer window 105. The second gate material layer 1041 is illustratively polysilicon.
Next, as shown in fig. 1E, a logic gate 106 is formed in the logic region. The first gate material layer 1040 and the second gate material layer 1041 in the logic region 100A are patterned by photolithography and etching processes to form the logic gate 106. The logic gate 106 includes two gate material layers, for example, two polysilicon layers, such that an interface is formed between the gate material layers, thereby increasing the polysilicon resistance, resulting in degraded Rs uniformity, which may lead to degraded device performance and yield.
Next, as shown in fig. 1F, a control gate stack structure 107 and a select gate stack structure 108 are formed in the flash memory region 100B. The first gate material layer 1040, the second gate material layer 1041, the isolation material layer 103 and the floating gate material layer 102 of the flash memory region 100B are patterned by photolithography and etching processes to form the control gate stack structure 107 and the select gate stack structure 108. Since the isolation layer window 105 exposes the lower first floating gate 102A in the select gate stack structure 108, the first floating gate 102A in the select gate stack structure 108 is connected to the upper select gate 104, and thus can be used as a select gate.
In the current method for manufacturing an embedded flash memory device, since a special step is required to form an isolation layer window to open an isolation layer, thereby realizing interconnection between an upper layer and a lower layer of a select gate, two times of deposition of a gate material layer (e.g. polysilicon) are required, thereby causing the foregoing problems, the present invention provides a method for manufacturing a semiconductor device, which is used for manufacturing an embedded flash memory device, and as shown in fig. 2, the method for manufacturing the embedded flash memory device includes: step 201, providing a semiconductor substrate, wherein the semiconductor substrate at least comprises a logic region and a flash memory region, and forming a floating gate material layer and an isolation material layer positioned above the floating gate material layer on the semiconductor substrate of the flash memory region; step 202, forming a gate material layer which covers the semiconductor substrate and the isolation material layer and is used for manufacturing a logic gate, a control gate and a selection gate; step 203, patterning the gate material layer to form a logic gate in the logic region, and forming an isolation layer window in the gate material layer of the flash memory region, where the isolation layer window is located in a region where a select gate is to be formed, and exposing a portion of the isolation material layer in the region where the select gate is to be formed; step 204, patterning the gate material layer, the isolation material layer and the floating gate material layer of the flash memory region to form a control gate stack structure and a select gate stack structure; step 205, removing the isolation material layer at the bottom of the isolation layer window.
According to the manufacturing method of the semiconductor device, when the embedded flash memory device is manufactured, the isolation layer window is formed at the same time of forming the logic gate, and the isolation layer window is used as a part of the selection gate stack structure without filling, so that the logic gate only comprises one side gate material layer without an interface, the problems of increasing polycrystalline silicon resistance, deteriorating Rs consistency, deteriorating device performance and yield and the like caused by the existence of the interface are solved, and the isolation layer window is formed in the same step without a separate step, so that a layer of photomask is saved, and the manufacturing cost of the device is reduced.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 3A to 3E.
First, a semiconductor substrate 300 is provided, the semiconductor substrate 300 including at least a logic region 300A and a flash memory region 300B. A gate oxide layer 301 is formed on the semiconductor substrate of the logic region 300A and the flash memory region 300B, and a floating gate material layer 302 and an isolation material layer 303 on the floating gate material layer 302 are formed on the semiconductor substrate of the flash memory region 100B, and the structure is as shown in fig. 3A.
Among them, the semiconductor substrate 300 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). In addition, an isolation structure such as STI (shallow trench isolation) may also be formed in the semiconductor substrate. As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.
The gate oxide layer 301 may be formed by a thermal oxidation method, for example, a furnace process. And the gate oxide layer 101 of the logic area 300A and the flash area 300B may have different thicknesses as needed.
The floating gate material layer 302 is illustratively a polysilicon material, which may be formed by one of selective Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG).
The isolation material layer 303 preferably has an ONO (oxide-nitride-oxide) structure, which has good interface properties and high dielectric properties. The isolation material layer 303 may be formed by PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.
Next, a gate material layer 304 for making logic gates, control gates and select gates is formed to cover the semiconductor substrate 300 and the isolation material layer 303, and the resulting structure is shown in fig. 3B.
The gate material layer 304 illustratively employs a polysilicon material, which may be formed by one of selective Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG). In the present embodiment, the thickness of the gate material layer 304 corresponds to the thickness of the logic gate, the control gate and the select gate, i.e. the thickness of the gate material layer 304 corresponds to the thickness of the first gate in the foregoing manufacturing methodThe sum of the thicknesses of material layer 1040 and second gate material layer 1041 corresponds. Illustratively, the gate material layer 304 has a thickness of
Next, the gate material layer 304 is patterned to form a logic gate 305 in the logic region 300A, and an isolation layer window 306 is formed in the gate material layer 304 in the flash memory region 300B, wherein the isolation layer window 306 is located in a region where a select gate is to be formed, and exposes a portion of the isolation material layer 303 in the region where the select gate is to be formed, and the structure is as shown in fig. 3C.
Illustratively, the formation process of the logic gate 305 and the spacer window 306 is: first, a patterned photoresist layer is formed on the gate material layer 304, the patterned photoresist layer defining the shape and position of the logic gate 305 and the spacer window 306; then, the gate material layer 304 is etched by a suitable dry etching process using the patterned photoresist layer as a mask, and stops on the surfaces of the gate oxide layer 301 and the isolation material layer 303, so as to form a logic gate 305 in the logic region 300A and form an isolation layer window 306 in the gate material layer 304 in the flash memory region 300B.
It will be appreciated that the dry etch process has a higher etch rate for the gate material layer and a lower etch rate for the oxide layer, such as the spacer material layer 303, in this step, so that the spacers at the bottom of the spacer windows 306 are not opened in this step.
Next, the gate material layer 304, the isolation material layer 303 and the floating gate material layer 302 of the flash memory region 300B are patterned to form a select gate stack structure 307 and a control gate stack structure 308, which are shown in fig. 3D.
Illustratively, the formation process of the select gate stack structure 307 and the control gate stack structure 308 is as follows: first, a patterned photoresist layer is formed in the semiconductor substrate 300, the patterned photoresist layer shields the logic region 300A, defines the positions and shapes of the select gate stack structure 307 and the control gate stack structure 308 in the flash memory region 300B, and fills the isolation layer window 306; then, the gate material layer 304, the isolation material layer 303, and the floating gate material layer 302 in the flash memory region 300B are etched by a suitable dry etching and stopped on the surface of the gate oxide layer (i.e., floating gate oxide layer) 301, thereby forming a select gate stack 307 and a control gate stack 308.
Finally, spacers 309 are formed on the sidewalls of the logic gate 305, the select gate stack structure 307 and the control gate stack structure 308, and a metal silicide 310 is formed on the source/drain regions and the top of the logic gate, the top of the control gate and the bottom of the window of the isolation layer, and the formed structure is as shown in fig. 3E.
Illustratively, the spacer 309 is formed by: firstly, forming a spacer material layer covering the semiconductor substrate 300 and the logic gate 305, the select gate stack structure 307 and the control gate stack structure 308; then, the gap material layer is patterned to remove portions of the gap wall material layer on the surface of the semiconductor substrate and on the top of the logic gate, the control gate stack structure and the select gate stack structure, and to leave portions on the sidewalls of the logic gate, the control gate stack structure and the select gate stack structure, so as to form a gap wall 309 on the sidewalls of the logic gate, the control gate stack structure and the select gate stack structure.
Illustratively, the formation process of the metal silicide 310 is as follows: firstly, forming a silicide shielding layer covering the semiconductor substrate 300, the logic gate 305, the select gate stack structure 307 and the control gate stack structure 308; then, the silicide shielding layer is patterned to expose a region to be formed with silicide, wherein the region to be formed with silicide comprises the top of the logic grid electrode, the top of the control grid electrode, the bottom of the isolating layer window in the selective grid stacking structure, and a source electrode, a drain electrode and a source drain region of a flash memory region in the logic region; then, forming metal silicide in the region to be formed with silicide; and finally, removing the silicide shielding layer. Namely, metal is formed on the surface of the logic gate, the surface of the control gate, the middle area of the opening isolation layer in the selection gate and the surface of the source drain area. The metal silicide is, for example, NiSi, which is formed by metal deposition, annealing, and the like, and is not described in detail herein.
In the present embodiment, the logic gate 305 includes only one gate material layer, and thus there is no interface, and there are no problems such as increased polysilicon resistance, deteriorated Rs uniformity, deteriorated device performance, and poor yield due to the interface.
In the present embodiment, the select gate stack 307 includes a first floating gate 302A on the semiconductor substrate, a first isolation layer 303A on the first floating gate 302A, and a select gate 304A on the first isolation layer 303A, and an isolation layer window 306A exposing the first floating gate 302A is formed in the select gate 304A and the first isolation layer 303A. That is, in the present embodiment, the select gate stack 307 has a hump-shaped structure, or a double-pyramid structure with the same bottom, wherein the select gate stack functionally has the first floating gate 302A with a height equal to that of the first floating gate 302A.
In the present embodiment, the control gate stack structure 308 includes a second floating gate 302B over the semiconductor substrate, a second isolation layer 303B over the second floating gate 302B, and a control gate 304B over the second isolation layer 303B. Control gate 304B includes only one layer of gate material and thus has no interface, and thus has no problems such as increased polysilicon resistance, degraded Rs uniformity, degraded device performance and yield due to the interface.
It is understood that in this embodiment, optionally, the portion of the first isolation layer 303A located at the bottom of the first isolation layer 303A is removed during the spacer etching and/or the silicide shielding layer etching, so that silicide can be formed on the exposed first floating gate 302A, thereby realizing interconnection with the upper layer structure. Of course, in other embodiments, the portion of the first isolation layer 303A located at the bottom of the isolation layer window 306 may be removed by an additional etching step during or after the step of forming the logic gate and isolation layer windows, or the portion of the first isolation layer 303A located at the bottom of the isolation layer window 306 may be removed by an additional etching step during or after the step of forming the control gate stack structure, the select gate stack structure, or the like.
It is further understood that the portions of the gate oxide layer 301 outside the logic gate 305, the select gate stack 307, and the control gate stack 308 may be removed during or after the formation of the spacers 309 and/or the silicide 310.
Now, the process steps performed by the method according to the embodiment of the present invention are completed, and it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps, but also other required steps, such as well implantation and ion doping, before, during or after the above steps, which are included in the scope of the method for manufacturing the semiconductor device according to the embodiment of the present invention.
According to the manufacturing method of the semiconductor device of the embodiment, when the embedded flash memory device is manufactured, the isolation layer window is formed while the logic gate is formed, and only one gate material layer is required to be deposited for forming the logic gate, the control gate and the selection gate, so that no interface exists in the logic gate, the problems of increased polysilicon resistance, deteriorated Rs consistency, deteriorated device performance and yield and the like caused by the existence of the interface are solved, and the isolation layer window is formed in the same step without a separate step because the logic gate and the isolation layer window are formed in the same step, so that a layer of photomask is saved, and the manufacturing cost of the device is reduced. That is, according to the method for manufacturing a semiconductor device of the embodiment, the resistance and uniformity of polysilicon are improved, the device performance is made closer to the target performance, and the manufacturing cost of the device is reduced.
Example two
The present invention also provides a semiconductor device, as shown in fig. 4, including: the semiconductor device comprises a semiconductor substrate 400, wherein the semiconductor substrate 400 at least comprises a logic area 400A and a flash memory area 400B, and a gate oxide layer 401 is formed on the semiconductor substrate of the logic area 400A and the flash memory area 400B; a logic gate 402, a spacer 403 on the sidewall of the logic gate 402 and silicides 404 on two sides of the logic gate are formed on the semiconductor substrate of the logic region 400A; a selection gate stack structure 405 and a control gate stack structure 406 are formed on the semiconductor substrate of the flash memory region 400B; the select gate stack structure 405 includes a first floating gate 407A located on the gate oxide layer 401, a first isolation layer 408A located on the first floating gate 407A, and a select gate 409A located on the first isolation layer 408A, wherein the first isolation layer 408A and the select gate 409A are located in an outer region of the surface of the first floating gate 407A and enclose an isolation layer window 410 located in a middle region and exposing the first floating gate 407A, that is, an isolation layer window 410 exposing the first floating gate 407A is formed in the first isolation layer 408A and the select gate 409A, and a silicide 404 contacting the first floating gate 407A is formed at the bottom of the isolation layer window 410. The control gate stack structure 406 comprises a second floating gate 407B located on the gate oxide layer 401, a second isolation layer 408B located on the second floating gate 407B, and a control gate 409B located on the second isolation layer 408B, and a silicide 404 is formed on the top of the control gate 409B;
in addition, silicide 404 is also formed in the source and drain regions of the select gate stack structure 405 and the control gate stack structure 406.
Wherein the semiconductor substrate 400 may be at least one of the materials mentioned below: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like.
Further, the gate oxide layer 401 may be made of a material commonly used in the art, such as silicon dioxide, and the logic gate 402, the first floating gate 407A, the second floating gate 407B, and the select gate 409A and the control gate 409B may be made of a material commonly used in the art, such as polysilicon. The first and second spacers 408A, 408B are preferably ONO structures, i.e., oxide, nitride, oxide structures, which have both good interfacial properties and a high dielectric constant. Silicide 404 is illustratively NiSi.
According to the semiconductor device of the embodiment, the resistance and uniformity of the polysilicon are improved, the performance is closer to the target performance, and the manufacturing cost is reduced.
EXAMPLE III
Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: the semiconductor substrate comprises a flash memory area, a selection gate stack structure is formed on the semiconductor substrate of the flash memory area, the selection gate stack structure comprises a first floating gate positioned on the semiconductor substrate, a first isolation layer positioned above the first floating gate and a selection gate positioned above the first isolation layer, and isolation layer windows exposing the first floating gate below are formed in the selection gate and the isolation layer.
Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In this embodiment, the constituent material of the semiconductor substrate is monocrystalline silicon.
Optionally, a control gate stack structure is further formed on the semiconductor substrate in the flash memory region, and the control gate stack structure includes a second floating gate, a second isolation layer, and a control gate, which are sequentially stacked on the semiconductor substrate.
Optionally, the semiconductor device further comprises: and a logic region having a logic gate formed on the semiconductor substrate of the logic region.
Optionally, a silicide is formed on top of the logic gate, on top of the control gate, and in the select gate stack structure at the bottom of the isolation layer window.
Optionally, the logic gate, the control gate and the select gate are all made of a single layer of polysilicon.
The electronic component may be any electronic component such as a discrete device and an integrated circuit.
The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.
Fig. 5 shows an example of a mobile phone. The exterior of the cellular phone 500 is provided with a display portion 502, operation buttons 503, an external connection port 504, a speaker 505, a microphone 506, and the like, which are included in a housing 501.
According to the electronic device provided by the embodiment of the invention, as the semiconductor device has improved polysilicon resistance and uniformity, the performance is closer to the target performance, and the manufacturing cost is reduced. The electronic device also has similar advantages.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (5)
1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a logic area and a flash memory area, and a grid oxide layer is formed on the semiconductor substrate of the logic area and the flash memory area;
forming a floating gate material layer and an isolation material layer positioned above the floating gate material layer on the gate oxide layer of the flash memory region;
forming a gate material layer covering the gate oxide layer and the isolation material layer;
patterning the gate material layer to form a logic gate in the logic region and forming an isolation layer window in the gate material layer of the flash memory region to expose the isolation material layer below;
patterning the gate material layer, the isolation material layer and the floating gate material layer of the flash memory region to form a select gate stack structure, the select gate stack structure including a first floating gate over the semiconductor substrate, a first isolation layer over the first floating gate and a select gate over the first isolation layer, and the isolation layer window formed in the select gate;
forming a spacer material layer covering the gate oxide layer, the logic gate and the select gate stack structure; patterning the spacer material layer to remove portions of the spacer material layer on the surface of the gate oxide layer and the tops of the logic gate and the select gate stack structure, and to retain portions on sidewalls of the logic gate and the select gate stack structure, so as to form spacers on the sidewalls of the logic gate and the select gate stack structure; and removing the spacer material layer and simultaneously removing the part of the first isolation layer at the bottom of the isolation layer window so as to expose the first floating gate below the isolation layer window.
2. The method for manufacturing a semiconductor device according to claim 1,
the gate material layer, the isolation material layer and the floating gate material layer in the flash memory region are patterned to form a selection gate stack structure and a control gate stack structure at the same time, wherein the control gate stack structure comprises a second floating gate, a second isolation layer and a control gate which are sequentially stacked on a semiconductor substrate in the flash memory region.
3. The method for manufacturing a semiconductor device according to claim 2, further comprising:
forming a spacer material layer covering the gate oxide layer and the logic gate, the control gate stack structure and the select gate stack structure;
and patterning the gap material layer to remove the parts of the gap wall material layer positioned on the surface of the gate oxide layer and the tops of the logic gate, the control gate stack structure and the selection gate stack structure and to reserve the parts positioned on the side walls of the logic gate, the control gate stack structure and the selection gate stack structure, so as to form a gap wall on the side walls of the logic gate, the control gate stack structure and the selection gate stack structure.
4. The method for manufacturing a semiconductor device according to claim 3, further comprising:
forming a silicide shielding layer covering the gate oxide layer, the logic gate, the control gate stack structure and the select gate stack structure;
imaging the silicide shielding layer to expose a region to be formed with silicide, wherein the region to be formed with silicide comprises the top of the logic gate, the top of the control gate, the bottom of the isolation layer window in the selective gate stack structure and a source drain region;
forming a metal silicide in the region to be formed with the silicide;
and removing the silicide shielding layer.
5. The method of manufacturing a semiconductor device according to claim 2, wherein the logic gate, the control gate, and the select gate are each formed of a single layer of polysilicon.
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