CN109148315B - Method for distinguishing through hole connection between two metal layers in chip - Google Patents
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- CN109148315B CN109148315B CN201810978762.7A CN201810978762A CN109148315B CN 109148315 B CN109148315 B CN 109148315B CN 201810978762 A CN201810978762 A CN 201810978762A CN 109148315 B CN109148315 B CN 109148315B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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Abstract
The invention discloses a method for distinguishing through hole connection between two metal layers in a chip, which is characterized in that when a second metal layer is formed, whether a through hole false connection state exists or not is preliminarily judged, the positions of a plurality of through holes are determined, FIB longitudinal cutting confirmation is carried out, if the chip is confirmed to use the false through holes in the manufacturing process, IBE is used for slightly etching the surface of the second metal layer, the through holes are simultaneously etched on the same plane with the height, and secondary electronic scanning of a scanning electron microscope is used for distinguishing the through holes with actual connection relation. Through the method for distinguishing the connection of the through holes between the two metal layers in the chip, disclosed by the invention, the IBE is used for slightly etching the surface of the chip, the two types of through holes are simultaneously reduced on the same plane with the height, and the secondary electronic scanning imaging effect is enhanced, so that the through holes in false connection are distinguished, the influence of the through holes in false connection on later-stage circuit analysis is eliminated, and the correctness of circuit reverse analysis can be greatly improved.
Description
Technical Field
The invention relates to the field of chips, in particular to a method for distinguishing through hole connection between two metal layers in a chip.
Background
The chip design is a systematic project, and from the research and establishment in the former stage to the design and production in the later stage, the design and production are very complicated and delicate, and the cost of each stage is very huge. At present, chip production is a work-substituting system, and for a chip designer, the borne risk is not only the success in design, but also various uncertain factors brought by a third party. In order to bring the chip into the market smoothly and reduce trial and error cost, a designer can implant a modifiable place in the layout design in advance, so that time and production cost can be reduced in subsequent revising, meanwhile, the method can meet the version requirements of different customers with different requirements, and has a protection against design for the design of the designer.
When carrying out circuit analysis to the chip, to the chip of abnormal structure, because the connection form of the through-hole can't be distinguished fast and accurate, cause reverse designer to take place logical mistake when circuit analysis easily, the unable fine situation whether the through-hole is connected between adjacent two-layer intermetallic of differentiateing in the chip of current technique.
Therefore, when an image of a chip with an abnormal structure is acquired, how to display through holes of two forms in the chip on the image and how to quickly and accurately distinguish the through holes in the acquired image layer are a difficult problem to be solved in the field.
Disclosure of Invention
The invention mainly solves the technical problem of providing a method for distinguishing the connection of through holes between two metal layers in a chip, wherein IBE is used for slightly etching the surface of the chip, two types of through holes are simultaneously reduced on the same plane of the height, and the secondary electronic scanning imaging effect is enhanced, so that the through holes in false connection are distinguished, the influence of the through holes in false connection on later-stage circuit analysis is eliminated, and the correctness of circuit reverse analysis can be greatly improved.
In order to solve the technical problems, the invention adopts a technical scheme that: a method for distinguishing the connection between through holes in chip is provided, the chip includes a substrate and metal layers prepared on the substrate from bottom to top, the metal layers include a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer, the fourth metal layer and the third metal layer are removed from top to bottom in sequence by a dry-wet method, when the second metal layer is used, the surface of the second metal layer is scanned by the secondary electron characteristics of a scanning electron microscope, the surface appearance of a sample is observed and displayed, the state of through hole false connection is preliminarily judged, the positions of multiple through holes are determined, the FIB longitudinal cutting confirmation is carried out, if the chip uses the false through holes in the manufacturing process, IBE is used for slightly etching the surface of the second metal layer, the through holes are simultaneously etched on the same plane of height, then, the secondary electron scanning of the scanning electron microscope is used for distinguishing the through holes with actual connection relations, and the method comprises the following specific steps:
step 1, sequentially removing the fifth metal layer, the fourth metal layer and the third metal layer from top to bottom by adopting a dry-wet method combination method:
a1, removing an oxide layer on the surface of the chip by RIE to expose the fifth metal layer, removing the fifth metal layer by using a corrosion reagent to expose the barrier layer, and removing the barrier layer by using a grinding method to expose the fourth metal layer;
b1, removing the oxide layer on the surface of the fourth metal layer by RIE to expose the fourth metal layer, removing the fourth metal layer by using a corrosive agent to expose the barrier layer, and removing the barrier layer by using a grinding method to expose the third metal layer;
c1, removing the oxide layer on the surface of the third metal layer by RIE to expose the third metal layer, removing the third metal layer by using a corrosion reagent to expose the barrier layer, and removing the barrier layer by using a grinding method to expose the second metal layer;
step 2, observing the second metal layer by using the secondary electron characteristics of the scanning electron microscope
a2, putting the sample into a sample chamber of a scanning electron microscope, and opening a secondary electron scanning mode;
b2, adjusting the voltage of an electron beam of the scanning electron microscope to be within the range of 5kv-10kv, and scanning the surface of the second metal layer;
c2, through the adjustment of voltage, the brightness of the through hole changes, the through hole connected with the lower layer keeps high brightness, the through hole not connected with the lower layer is dark, and the brightness is continuously reduced along with the reduction of voltage;
d2, in the scanning area of the scanning electron microscope, using brightness and darkness as sampling conditions, selecting a plurality of through holes with characteristics as the positions for FIB longitudinal confirmation;
step 3, confirming the connection mode of the through hole by using a mode of FIB longitudinal cutting
a3, cutting the longitudinal surface of the selected through hole by FIB to confirm the connection state of the two through holes with different brightness and the lower layer metal;
b3, comparing the longitudinal section structure of FIB with the secondary electron scanning form of scanning electron microscope to confirm the through hole connection mode;
step 4, carrying out slight etching on the metal surface by using IBE, and then carrying out secondary electron scanning by using a scanning electron microscope:
a4, slightly etching the surface of the second metal layer by IBE, and simultaneously etching the through holes at the same plane height;
b4, carrying out secondary electron scanning on the etched sample by using a scanning electron microscope and collecting an image;
c4, accurately distinguishing the type of the through hole from the collected image, wherein the through hole with high brightness is connected with the lower metal layer, and the through hole with low brightness is not connected with the lower metal layer.
In a preferred embodiment of the present invention, the chip is a printer cartridge chip.
In a preferred embodiment of the present invention, the metal material of the fifth metal layer is aluminum, and the metal materials of the fourth metal layer, the third metal layer, the second metal layer and the first metal layer are all copper materials.
In a preferred embodiment of the present invention, the through holes are located at least three positions.
The invention has the beneficial effects that: according to the method for distinguishing the connection of the through holes between the two metal layers in the chip, the IBE is used for slightly etching the surface of the chip, the two types of through holes are simultaneously reduced on the same plane with the height, the secondary electronic scanning imaging effect is enhanced, the through holes in false connection are distinguished, the influence of the through holes in false connection on later-stage circuit analysis is eliminated, and the accuracy of circuit reverse analysis can be greatly improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a flow chart of a method for identifying via connections between two metal layers in a chip according to a preferred embodiment of the present invention;
fig. 2 is a longitudinal structure of a via hole in a normal process, which includes a first metal layer (M1), a second metal layer (M2), and a third metal layer (M3) from bottom to top;
FIG. 3 is a longitudinal structure of a via hole in an abnormal process, which is a first metal layer (M1), a second metal layer (M2) and a third metal layer (M3) from bottom to top;
FIG. 4 is a schematic illustration of a dummy via after etching using IBE;
FIG. 5 is a schematic illustration of secondary electron scanning of a chip surface using a scanning electron microscope.
Fig. 6 is a schematic diagram showing the effect of image acquisition by a scanning electron microscope using a secondary electron mode after IBE etching, where the luminance of a through hole not connected to a lower layer is substantially 0, a black circle represents an actual connection hole, and a gray circle represents a dummy hole.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 to 5, the embodiment of the present invention includes:
a method for distinguishing the connection of through holes between two metal layers in a chip comprises a substrate and metal layers prepared on the substrate from bottom to top, wherein the metal layers comprise a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer, the fourth metal layer and the third metal layer are sequentially removed from top to bottom by adopting a dry-wet method combination method, when the second metal layer is used, the surface of the second metal layer is scanned by the secondary electron characteristics of a scanning electron microscope, the surface appearance of a sample is observed and displayed, whether the state of false connection of the through holes exists or not is preliminarily judged, the positions of a plurality of (at least three) through holes are determined, FIB longitudinal cutting confirmation is carried out, if the false through holes are used in the manufacturing process of the chip, IBE is used for slightly etching the surface of the second metal layer, and the through holes are simultaneously etched on the same plane with the height, then, the secondary electron scanning of the scanning electron microscope is used for distinguishing the through holes with actual connection relations, and the method comprises the following specific steps:
step 1, sequentially removing the fifth metal layer, the fourth metal layer and the third metal layer from top to bottom by adopting a dry-wet method combination method:
a1, removing an oxide layer on the surface of the chip by RIE to expose the fifth metal layer, removing the fifth metal layer by using a corrosion reagent to expose the barrier layer, and removing the barrier layer by using a grinding method to expose the fourth metal layer;
b1, removing the oxide layer on the surface of the fourth metal layer by RIE to expose the fourth metal layer, removing the fourth metal layer by using a corrosive agent to expose the barrier layer, and removing the barrier layer by using a grinding method to expose the third metal layer;
c1, removing the oxide layer on the surface of the third metal layer by RIE to expose the third metal layer, removing the third metal layer by using a corrosion reagent to expose the barrier layer, and removing the barrier layer by using a grinding method to expose the second metal layer;
step 2, observing the second metal layer by using the secondary electron characteristics of the scanning electron microscope
a2, putting the sample into a sample chamber of a scanning electron microscope, and opening a secondary electron scanning mode;
b2, adjusting the voltage of an electron beam of the scanning electron microscope to be within the range of 5kv-10kv, and scanning the surface of the second metal layer;
c2, through the adjustment of voltage, the brightness of the through hole changes, the through hole connected with the lower layer keeps high brightness, the through hole not connected with the lower layer is dark, and the brightness is continuously reduced along with the reduction of voltage;
d2, in the scanning area of the scanning electron microscope, using brightness and darkness as sampling conditions, selecting a plurality of through holes with characteristics as the positions for FIB longitudinal confirmation;
step 3, confirming the connection mode of the through hole by using a mode of FIB longitudinal cutting
a3, cutting the longitudinal surface of the selected through hole by FIB to confirm the connection state of the two through holes with different brightness and the lower layer metal;
b3, comparing the longitudinal section structure of FIB with the secondary electron scanning form of scanning electron microscope to confirm the through hole connection mode;
step 4, carrying out slight etching on the metal surface by using IBE, and then carrying out secondary electron scanning by using a scanning electron microscope:
a4, slightly etching the surface of the second metal layer by IBE, and simultaneously etching the through holes at the same plane height;
b4, carrying out secondary electron scanning on the etched sample by using a scanning electron microscope and collecting an image;
c4, accurately distinguishing the type of the through hole from the collected image, wherein the through hole with high brightness is connected with the lower metal layer, and the through hole with low brightness is not connected with the lower metal layer.
In the above, the chip is a printer cartridge chip. The metal material of fifth metal layer be the aluminium material, the metal material of fourth metal level, third metal level, second metal level, first metal level be the copper material. The third metal layer and the second metal layer are connected and conducted through a copper through hole.
The through holes are in conductive connection with two adjacent layers of metal, but in practice, the through holes are not connected with the lower layer of metal, the through holes which are connected with the lower layer of metal are slightly etched by IBE metal, the through holes which are not connected with the lower layer of metal are removed, and then the scanning electron microscope is used for scanning in a secondary electron mode.
The scanning electron microscope must use a secondary electron mode, and secondary electrons are generally emitted in the depth range of 5-10nm of the surface layer and are very sensitive to the surface topography of a sample, so that the characteristic of the surface topography of the sample can be very effectively displayed. Wherein, the sample finally collected by the secondary electron must be etched by IBE, the through hole which is not connected with the lower layer metal is removed, and then scanning collection is carried out. The through holes actually connected with the lower layer metal can be easily and accurately distinguished by using the secondary electron mode of the scanning electron microscope to collect images and through the difference of the reflectivity of the secondary electrons to the two through holes.
When observing in the secondary electron mode of the scanning electron microscope for the first time, according to the actual condition of a sample, the observation is carried out by using low voltage as far as possible, because the through hole which is not connected with the lower layer metal is adopted, the quantity of the secondary electrons fed back and the quantity of the secondary electrons fed back by the through hole which is connected with the lower layer metal have great difference, so certain difference can be generated in brightness, and the connected through hole can be brighter. Therefore, the position of the point needing longitudinal dissection can be better selected from the FIB. Selecting through hole points at a plurality of (at least three) positions, using FIB to perform longitudinal dissection of fixed point positions, and confirming the actual connection form of the through holes and the upper layer and the lower layer. After the abnormal connection state is confirmed, IBE is used for carrying out small-energy ion etching on metal on the surface of the chip, and the main purpose is to reduce the height of the through hole on the same plane until the through hole is removed without being connected with the lower layer metal. And then scanning in a secondary electron mode by using a scanning electron microscope, and finding that the brightness of the through hole which is not connected with the lower layer metal on the collected image is basically 0, and the brightness of the through hole which is connected with the lower layer is unchanged. Therefore, the actual connection relation between the through hole on the current layer and the two adjacent layers of metal is easily and accurately distinguished, namely the embodiment of the distinguishing method for judging whether the through holes between the two adjacent layers of metal in the chip are connected is realized in the actual action. The FIB mainly performs longitudinal dissection of fixed-point positions on through holes to confirm whether the through hole connection mode between two layers exists in two forms.
The invention utilizes the characteristic of secondary electrons of a scanning electron microscope, the secondary electrons are generally emitted in the depth range of 5-10nm on the surface layer and are very sensitive to the surface topography of a sample, so the surface topography of the sample can be effectively displayed, and the surface of a metal layer of a chip is scanned.
In summary, according to the method for identifying the connection of the through holes between the two metal layers in the chip, the IBE is used for slightly etching the surface of the chip, the two types of through holes are simultaneously reduced on the same plane with the height, the secondary electronic scanning imaging effect is enhanced, the through holes in false connection are identified, the influence of the through holes in false connection on later-stage circuit analysis is eliminated, and the accuracy of circuit reverse analysis can be greatly improved.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by the present specification, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (4)
1. A method for distinguishing through hole connection between two metal layers in a chip is characterized in that the chip comprises a substrate and metal layers prepared on the substrate from bottom to top, the metal layers comprise a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer, the fourth metal layer and the third metal layer are sequentially removed from top to bottom by adopting a dry-wet method combination method, when the second metal layer is used, the surface of the second metal layer is scanned by secondary electron characteristics of a scanning electron microscope, the surface appearance of a sample is observed and displayed, whether a through hole false connection state exists or not is preliminarily judged, the positions of a plurality of through holes are determined, FIB longitudinal cutting confirmation is carried out, if the false through holes are confirmed in the manufacturing process of the chip, IBE is used for slightly etching the surface of the second metal layer, the through holes are simultaneously etched on the same plane of height, then, the secondary electron scanning of the scanning electron microscope is used for distinguishing the through holes with actual connection relations, and the method comprises the following specific steps:
step 1, sequentially removing the fifth metal layer, the fourth metal layer and the third metal layer from top to bottom by adopting a dry-wet method combined method
a1, removing an oxide layer on the surface of the chip by RIE to expose the fifth metal layer, removing the fifth metal layer by using a corrosion reagent to expose the barrier layer, and removing the barrier layer by using a grinding method to expose the fourth metal layer;
b1, removing the oxide layer on the surface of the fourth metal layer by RIE to expose the fourth metal layer, removing the fourth metal layer by using a corrosive agent to expose the barrier layer, and removing the barrier layer by using a grinding method to expose the third metal layer;
c1, removing the oxide layer on the surface of the third metal layer by RIE to expose the third metal layer, removing the third metal layer by using a corrosion reagent to expose the barrier layer, and removing the barrier layer by using a grinding method to expose the second metal layer;
step 2, observing the second metal layer by using the secondary electron characteristics of the scanning electron microscope
a2, putting the sample into a sample chamber of a scanning electron microscope, and opening a secondary electron scanning mode;
b2, adjusting the voltage of an electron beam of the scanning electron microscope to be within the range of 5kv-10kv, and scanning the surface of the second metal layer;
c2, through the adjustment of voltage, the brightness of the through hole changes, the through hole connected with the lower layer keeps high brightness, the through hole not connected with the lower layer is dark, and the brightness is continuously reduced along with the reduction of voltage;
d2, in the scanning area of the scanning electron microscope, selecting a plurality of through holes as the longitudinal confirmation positions of the FIB by taking the brightness and darkness as the sampling conditions;
step 3, confirming the connection mode of the through hole by using a mode of FIB longitudinal cutting
a3, cutting the longitudinal surface of the selected through hole by FIB to confirm the connection state of the two through holes with different brightness and the lower layer metal;
b3, comparing the longitudinal section structure of FIB with the secondary electron scanning form of scanning electron microscope to confirm the through hole connection mode;
step 4, IBE is used for slightly etching the metal surface, and secondary electron scanning of a scanning electron microscope is applied;
a4, slightly etching the surface of the second metal layer by IBE, and simultaneously etching the through holes at the same plane height;
b4, carrying out secondary electron scanning on the etched sample by using a scanning electron microscope and collecting an image;
c4, accurately distinguishing the type of the through hole from the collected image, wherein the through hole with high brightness is connected with the lower metal layer, and the through hole with low brightness is not connected with the lower metal layer.
2. The method of claim 1, wherein the chip is a printer cartridge chip.
3. The method according to claim 1, wherein the fifth metal layer is made of aluminum, and the fourth metal layer, the third metal layer, the second metal layer and the first metal layer are made of copper.
4. The method of claim 1, wherein the number of vias is at least three.
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