CN109148315A - The discriminating conduct of two through-hole between metallic layers connection in a kind of chip - Google Patents
The discriminating conduct of two through-hole between metallic layers connection in a kind of chip Download PDFInfo
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- CN109148315A CN109148315A CN201810978762.7A CN201810978762A CN109148315A CN 109148315 A CN109148315 A CN 109148315A CN 201810978762 A CN201810978762 A CN 201810978762A CN 109148315 A CN109148315 A CN 109148315A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses the discriminating conducts that two through-hole between metallic layers in a kind of chip connect, in second metal layer, tentatively judge whether there is the state of through-hole falseness connection, determine the position of many places through-hole, carry out the longitudinal sectional confirmation of FIB, after if confirmation chip has used false through-hole in manufacture craft, slight etching is carried out with surface of the IBE to second metal layer, through-hole is performed etching simultaneously on the same plane of height, then identifies the through-hole of practical connection relationship with the secondary electron scanning of scanning electron microscope.By above-mentioned, the discriminating conduct that two through-hole between metallic layers connect in chip of the invention, slight etching is carried out to chip surface with IBE, two class through-holes are reduced simultaneously on the same plane of height, reinforce secondary electron scanning imagery effect, to distinguish the through-hole of false connection, eliminates since the through-hole of falseness connection influences later period circuit analysis, the correctness of circuit conversed analysis can be greatly improved.
Description
Technical field
The present invention relates to the discriminating conducts that two through-hole between metallic layers in the field of chip more particularly to chip connect.
Background technique
Chip design be a system engineering, from early period investigate set up the project, to the later period design production be all one very
Complicated and elaboration, the cost in each stage are very huge.Chip production is all foundry system at this stage, right
For the designer of a chip, the risk undertaken is not only merely the success or not in design, but also there are also third parties
Brought various probabilistic factors.Designer can set for the smooth listing and reduction trial and error cost of chip in domain
The place that can be modified is implanted into meter in advance, time and production cost can be reduced in subsequent correcting in this way, while can be with needle
To the release requirement of different clients different demands, and the protection of a mimetic design is had for the design of itself.
When carrying out circuit analysis to chip, for the chip of improper structure, due to that can not distinguish fast and accurately
The connection form of through-hole be easy to cause reverse engineer personnel that logicality mistake occurs in circuit analysis, and existing technology can not
The situation that whether through-hole connects between adjacent two layers metal in chip is distinguished well.
Therefore, when carrying out the Image Acquisition of chip of improper structure, how the through-hole of two kinds of forms in chip to be existed
Showed on image, in figure layer after acquisition, how distinguishing quickly and accurately, be this field difficulty urgently to be resolved
Topic.
Summary of the invention
The invention mainly solves the technical problem of providing the discriminating conducts that two through-hole between metallic layers in chip connect, and use
IBE carries out slight etching to chip surface, and two class through-holes are reduced simultaneously on the same plane of height, reinforce secondary electricity
Sub- scanning imagery effect eliminates the through-hole due to falseness connection for later period circuit to distinguish the through-hole of false connection
Analyzing influence can greatly improve the correctness of circuit conversed analysis.
In order to solve the above technical problems, one technical scheme adopted by the invention is that: provide two metals in a kind of chip
The discriminating conduct of inter-level vias connection, the metal layer that the chip includes substrate and is prepared on substrate from bottom to top, institute
The metal layer stated includes the first metal layer, second metal layer, third metal layer, the 4th metal layer and fifth metal layer, using dry
The method that wet process combines successively removes fifth metal layer, the 4th metal layer and third metal layer from top to bottom, in the second metal
When layer, the surface of second metal layer is scanned by the secondary electron characteristic of scanning electron microscope, observation display sample
Surface topography, tentatively judge whether there is the state of through-hole falseness connection, determine the position of many places through-hole, carry out the vertical of FIB
Confirmation is cut, if after confirmation chip has used false through-hole in manufacture craft, carrying out with surface of the IBE to second metal layer light
Through-hole is performed etching simultaneously on the same plane of height, then swept with the secondary electron of scanning electron microscope by microetch
It retouches to identify the through-hole of practical connection relationship, comprising the following specific steps
Step 1, the method combined using wet-dry change successively remove fifth metal layer, the 4th metal layer and the from top to bottom
Three metal layers:
A1, the oxide layer of chip surface is removed with RIE, exposes fifth metal layer, with corrosion reagent by fifth metal
Layer removal exposes barrier layer, then removes barrier layer with polishing, exposes the 4th metal layer；
B1, the oxide layer of the 4th layer on surface of metal is removed with RIE, exposes the 4th layer of metal, with corrosion reagent by the
The removal of four metal layers exposes barrier layer, then removes barrier layer with polishing, exposes third metal layer；
C1, the oxide layer of third layer on surface of metal is removed with RIE, exposes third metal layer, with corrosion reagent by the
The removal of three metal layers exposes barrier layer, then removes barrier layer with polishing, exposes second metal layer；
Step 2 observes second metal layer using the secondary electron characteristic of scanning electron microscope
A2, sample is put into the sample room of scanning electron microscope, opens secondary electron scan pattern；
B2, the electron-beam voltage of scanning electron microscope is adjusted within the scope of 5kv-10kv, to the surface of second metal layer
It is scanned；
C2, the adjustment by voltage, the brightness of through-hole change, and the through-hole connecting with lower layer can keep highlighted, under
The disjunct through-hole of layer shades and with the reduction of voltage, and brightness persistently reduces；
D2, the scanning area in scanning electron microscope, using the light and shade of brightness as sampling condition, choosing many places has feature
The position that longitudinally confirms as FIB of through-hole；
Step 3, the connection type that through-hole is confirmed with the longitudinally cutting mode of FIB
A3, the cutting for carrying out longitudinal surface to the through-hole of selection with FIB, to confirm the different through-hole of two kinds of brightness and lower layer's gold
Belong to attached state；
B3, it is compared, is confirmed by the longitudinal profile structure of FIB and the secondary electron scanning form of scanning electron microscope
Through-hole connection type；
Step 4 carries out slight etching to metal surface with IBE, then scans with the secondary electron of scanning electron microscope:
A4, slight etching is carried out with surface of the IBE to second metal layer, will be carried out simultaneously in the through-hole of same plane height
Etching；
B4, the sample after etching is subjected to secondary electron scanning with scanning electron microscope and acquires image；
C4, the type that through-hole can be accurately identified from the image after acquisition, of high brightness is to be connected with lower metal layer
The through-hole connect, low brightness is the through-hole not being connected with lower metal layer.
In a preferred embodiment of the present invention, the chip is ink-cases of printers chip.
In a preferred embodiment of the present invention, the metal material of the fifth metal layer is aluminium material, described the
Four metal layers, third metal layer, second metal layer, the first metal layer metal material be copper material.
In a preferred embodiment of the present invention, the position of the through-hole is at least at three.
The beneficial effects of the present invention are: the discriminating conduct that two through-hole between metallic layers connect in chip of the invention, with IBE
Slight etching is carried out to chip surface, two class through-holes are reduced simultaneously on the same plane of height, reinforce secondary electron
Scanning imagery effect eliminates the through-hole due to falseness connection for later period circuit point to distinguish the through-hole of false connection
Analysis influences, and can greatly improve the correctness of circuit conversed analysis.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, in which:
Fig. 1 is the process signal of a preferred embodiment of the discriminating conduct that two through-hole between metallic layers connect in chip of the present invention
Figure；
Fig. 2 is the through-hole vertical structure under normal process, is successively the first metal layer (M1), second metal layer from bottom to top
(M2), third metal layer (M3)；
Fig. 3 is the through-hole vertical structure under non-normal process, is successively the first metal layer (M1), the second metal from bottom to top
Layer (M2), third metal layer (M3)；
Fig. 4 is after being etched using IBE, by schematic diagram of the false via etch after complete；
Fig. 5 be using scanning electron microscope secondary electron schematic diagram that chip surface is scanned.
Fig. 6 is after IBE is etched, and scanning electron microscope is illustrated using the effect that secondary electron mode carries out Image Acquisition
Figure, the through-hole brightness not connecting with lower layer are essentially 0, and black circle represents practical connecting hole, and gray circular represents false hole.
Specific embodiment
The technical scheme in the embodiments of the invention will be clearly and completely described below, it is clear that described implementation
Example is only a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's all other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.
As shown in Figures 1 to 5, the embodiment of the present invention includes:
The discriminating conduct of two through-hole between metallic layers connection in a kind of chip, the chip include substrate and from bottom to top
The metal layer being prepared on substrate, the metal layer include the first metal layer, second metal layer, third metal layer, the 4th gold medal
Belong to layer and fifth metal layer, fifth metal layer, the 4th metal layer are successively removed using the method that wet-dry change combines from top to bottom
With third metal layer, in second metal layer, by the secondary electron characteristic of scanning electron microscope to the table of second metal layer
Face is scanned, and the surface topography of observation display sample tentatively judges whether there is the state of through-hole falseness connection, determines many places
The position of (at least three) through-hole, carries out the longitudinal sectional confirmation of FIB, if confirmation chip has used false through-hole in manufacture craft
Afterwards, slight etching is carried out with surface of the IBE to second metal layer, through-hole is carved simultaneously on the same plane of height
Erosion, then the secondary electron scanning of scanning electron microscope is used to identify the through-hole of practical connection relationship, including following
Specific steps:
Step 1, the method combined using wet-dry change successively remove fifth metal layer, the 4th metal layer and the from top to bottom
Three metal layers:
A1, the oxide layer of chip surface is removed with RIE, exposes fifth metal layer, with corrosion reagent by fifth metal
Layer removal exposes barrier layer, then removes barrier layer with polishing, exposes the 4th metal layer；
B1, the oxide layer of the 4th layer on surface of metal is removed with RIE, exposes the 4th layer of metal, with corrosion reagent by the
The removal of four metal layers exposes barrier layer, then removes barrier layer with polishing, exposes third metal layer；
C1, the oxide layer of third layer on surface of metal is removed with RIE, exposes third metal layer, with corrosion reagent by the
The removal of three metal layers exposes barrier layer, then removes barrier layer with polishing, exposes second metal layer；
Step 2 observes second metal layer using the secondary electron characteristic of scanning electron microscope
A2, sample is put into the sample room of scanning electron microscope, opens secondary electron scan pattern；
B2, the electron-beam voltage of scanning electron microscope is adjusted within the scope of 5kv-10kv, to the surface of second metal layer
It is scanned；
C2, the adjustment by voltage, the brightness of through-hole change, and the through-hole connecting with lower layer can keep highlighted, under
The disjunct through-hole of layer shades and with the reduction of voltage, and brightness persistently reduces；
D2, the scanning area in scanning electron microscope, using the light and shade of brightness as sampling condition, choosing many places has feature
The position that longitudinally confirms as FIB of through-hole；
Step 3, the connection type that through-hole is confirmed with the longitudinally cutting mode of FIB
A3, the cutting for carrying out longitudinal surface to the through-hole of selection with FIB, to confirm the different through-hole of two kinds of brightness and lower layer's gold
Belong to attached state；
B3, it is compared, is confirmed by the longitudinal profile structure of FIB and the secondary electron scanning form of scanning electron microscope
Through-hole connection type；
Step 4 carries out slight etching to metal surface with IBE, then scans with the secondary electron of scanning electron microscope:
A4, slight etching is carried out with surface of the IBE to second metal layer, will be carried out simultaneously in the through-hole of same plane height
Etching；
B4, the sample after etching is subjected to secondary electron scanning with scanning electron microscope and acquires image；
C4, the type that through-hole can be accurately identified from the image after acquisition, of high brightness is to be connected with lower metal layer
The through-hole connect, low brightness is the through-hole not being connected with lower metal layer.
Among the above, the chip is ink-cases of printers chip.The metal material of the fifth metal layer is aluminium material,
4th metal layer, third metal layer, second metal layer, the first metal layer metal material be copper material.Wherein,
Three metal layers and second metal layer are to be attached conducting by the through-hole of copper material.
Adjacent two layers metal is carried out conducting connection by through-hole, but exists do not do the form connecting with lower metal in practice,
The through-hole not connecting with lower metal is removed with IBE metal slight etching by the through-hole being connect to it with lower metal,
The secondary electron mode for reusing scanning electron microscope is swept.
Scanning electron microscope is had to using secondary electron mode, because secondary electron is typically all in surface layer 5-10nm depth
It is emitted in degree range, it is very sensitive to the pattern of sample surfaces, therefore can the very effective surface for showing sample
The characteristic of pattern.Wherein, the sample that secondary electron finally acquires has to be etched with IBE, will not be with lower metal phase
The through-hole of connection removes, then is scanned acquisition.The image being acquired using the secondary electron mode of scanning electron microscope,
By secondary electron to the difference of two kinds of through-hole reflectivity, reality can be identified easily and accurately and be connect with lower metal
Through-hole.
When being observed using the secondary electron mode of scanning electron microscope first time, according to the practical shape of sample
Condition is observed using low-voltage as far as possible, is the secondary electron fed back due to not doing the through-hole connecting with lower metal
The quantity of the secondary electron fed back with the through-hole connecting with lower metal has huge gap, so can be in brightness
Upper to generate certain difference, the through-hole of connection can be brighter.The point longitudinally dissected need to be done by doing so as to preferably choosing FIB
Position.Through-hole point is chosen in many places (at least three), is the longitudinal of fixed position with FIB and dissects, and confirms through-hole and upper and lower level
Practical connection form.Confirmation is the ion etching using IBE to the small energy of chip surface metal after improper connection form, main
Syllabus is to reduce the height of the through-hole on same plane, until not connecting through-hole removal with lower metal.It reuses and sweeps
Face electron microscope carries out secondary electron Mode scans, it is found that the through-hole not connecting with lower metal on the image of acquisition
Brightness is essentially 0, and the through-hole brightness connecting with lower layer is constant.To be easy and accurately identify current layer through-hole with it is adjacent
The practical connection relationship of double layer of metal, the discriminating conduct that as whether through-hole connects between adjacent two layers metal in chip is in practical work
Embodiment.Wherein, FIB is mainly to pass through its longitudinal dissection that fixed position is done to through-hole, the through-hole connection of two interlayers of confirmation
Mode whether there is two kinds of forms.
The present invention utilizes the characteristic of scanning electron microscope secondary electron, and secondary electron is typically all in surface layer 5-10nm depth
It is emitted in degree range, it is very sensitive to the pattern of sample surfaces, therefore can the very effective surface for showing sample
Pattern is scanned the layer on surface of metal of chip.
In conclusion the discriminating conduct that two through-hole between metallic layers connect in chip of the invention, with IBE to chip surface
Slight etching is carried out, two class through-holes are reduced simultaneously on the same plane of height, reinforce secondary electron scanning imagery effect
Fruit eliminates to distinguish the through-hole of false connection since the through-hole of falseness connection influences later period circuit analysis, can be with
Greatly improve the correctness of circuit conversed analysis.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright description is applied directly or indirectly in other relevant technology necks
Domain is included within the scope of the present invention.
Claims (4)
1. the discriminating conduct that two through-hole between metallic layers connect in a kind of chip, which is characterized in that the chip include substrate with
And it is prepared in the metal layer on substrate from bottom to top, the metal layer includes the first metal layer, second metal layer, third metal
Layer, the 4th metal layer and fifth metal layer successively remove fifth metal layer, the using the method that wet-dry change combines from top to bottom
Four metal layers and third metal layer, in second metal layer, by the secondary electron characteristic of scanning electron microscope to the second gold medal
The surface for belonging to layer is scanned, and the surface topography of observation display sample tentatively judges whether there is the state of through-hole falseness connection,
It determines the position of many places through-hole, carries out the longitudinal sectional confirmation of FIB, if after confirmation chip has used false through-hole in manufacture craft,
Slight etching is carried out with surface of the IBE to second metal layer, through-hole is performed etching simultaneously on the same plane of height, then
With the secondary electron scanning of scanning electron microscope to identify the through-hole of practical connection relationship, including walk in detail below
It is rapid:
Step 1 successively removes fifth metal layer, the 4th metal layer and third gold using the method that wet-dry change combines from top to bottom
Belong to layer:
A1, the oxide layer of chip surface is removed with RIE, exposes fifth metal layer, is gone fifth metal layer with corrosion reagent
It removes, exposes barrier layer, then remove barrier layer with polishing, expose the 4th metal layer；
B1, the oxide layer of the 4th layer on surface of metal is removed with RIE, exposes the 4th layer of metal, with corrosion reagent by the 4th gold medal
Belong to layer removal, exposes barrier layer, then remove barrier layer with polishing, expose third metal layer；
C1, the oxide layer of third layer on surface of metal is removed with RIE, exposes third metal layer, it is with corrosion reagent that third is golden
Belong to layer removal, exposes barrier layer, then remove barrier layer with polishing, expose second metal layer；
Step 2 observes second metal layer using the secondary electron characteristic of scanning electron microscope
A2, sample is put into the sample room of scanning electron microscope, opens secondary electron scan pattern；
B2, the electron-beam voltage of scanning electron microscope is adjusted within the scope of 5kv-10kv, the surface of second metal layer is carried out
Scanning；
C2, the adjustment by voltage, the brightness of through-hole change, and the through-hole connecting with lower layer can keep highlighted, not with lower layer
Connected through-hole shades and with the reduction of voltage, and brightness persistently reduces；
D2, the scanning area in scanning electron microscope, using the light and shade of brightness as sampling condition, choosing many places has the logical of feature
The position that hole longitudinally confirms as FIB；
Step 3, the connection type that through-hole is confirmed with the longitudinally cutting mode of FIB
A3, the cutting for carrying out longitudinal surface to the through-hole of selection with FIB, to confirm the different through-hole of two kinds of brightness and lower metal phase
Even state；
B3, it is compared by the longitudinal profile structure of FIB and the secondary electron scanning form of scanning electron microscope, confirms through-hole
Connection type；
Step 4 carries out slight etching to metal surface with IBE, then scans with the secondary electron of scanning electron microscope:
A4, slight etching is carried out with surface of the IBE to second metal layer, will be carved simultaneously in the through-hole of same plane height
Erosion；
B4, the sample after etching is subjected to secondary electron scanning with scanning electron microscope and acquires image；
C4, the type that through-hole can be accurately identified from the image after acquisition, it is of high brightness to be connected with lower metal layer
Through-hole, low brightness is the through-hole not being connected with lower metal layer.
2. the discriminating conduct that two through-hole between metallic layers connect in chip according to claim 1, which is characterized in that described
Chip is ink-cases of printers chip.
3. the discriminating conduct that two through-hole between metallic layers connect in chip according to claim 1, which is characterized in that described
The metal material of fifth metal layer is aluminium material, the 4th metal layer, third metal layer, second metal layer, the first metal
The metal material of layer is copper material.
4. the discriminating conduct that two through-hole between metallic layers connect in chip according to claim 1, which is characterized in that described
The position of through-hole is at least at three.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810978762.7A CN109148315B (en) | 2018-08-27 | 2018-08-27 | Method for distinguishing through hole connection between two metal layers in chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810978762.7A CN109148315B (en) | 2018-08-27 | 2018-08-27 | Method for distinguishing through hole connection between two metal layers in chip |
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| CN109148315B CN109148315B (en) | 2020-11-10 |
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