JP4695909B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a manufacturing technology of a semiconductor integrated circuit device, and more particularly to a technology effective when applied to detection of a defect or foreign matter of a plug formed on a main surface of a semiconductor wafer.

  Patent Document 1 discloses a method for inspecting connection holes (contact holes) that uses secondary electrons or reflected electrons, sets the electron beam current (beam current) to 50 pA to 5 nA, suppresses the edge effect, and makes the contrast substantially uniform. It is disclosed.

  Patent Document 2 discloses a method of detecting an electric potential contrast defect by setting an optimum value of irradiation energy suitable for the structure of an inspection object using secondary electrons.

  In Patent Document 3, a secondary electron or a reflected electron is used to switch a high electron beam current (high probe current) of 1 nA to 100 nA and a low electron beam current (low probe current) of 50 pA to 200 pA to observe a plug. A method is disclosed.

Non-Patent Document 1 includes a study on an electron beam current for obtaining a practical image forming time while ensuring a high signal-to-noise ratio (SNR) of a scanning electron microscope (SEM) image. The configuration of the SEM optical system is described.
Japanese Patent Laid-Open No. 2000-48752 JP 2000-314710 A JP 2003-133379 A Hiroyuki Shinada, Hiroshi Makino, Yuko Takafuji, Yutaka Kaneko, Hisaya Murakoshi, “High-speed, high-current SEM optics for wafer inspection”, LSI test symposium materials, pp. 151-156, 2000.

  In a semiconductor integrated circuit device, each element structure is miniaturized for high integration and high performance, and the wiring that forms an IC (Integrated Circuit) or LSI (Large Scale Integration) by connecting each element is also fine. It has become. These wirings are formed in multiple layers on, for example, MIS (Metal Insulator Semiconductor) transistors, diodes, etc. formed on the main surface of the semiconductor wafer, and the wirings of the respective layers are connected by plugs penetrating the insulating film. Due to such miniaturization of the plug or wiring, various defects or foreign matters are generated, which cause a defect in the semiconductor integrated circuit device.

  A plug defect (hereinafter referred to as “defective plug”) occurring in the semiconductor integrated circuit device will be described. FIG. 32 is a cross-sectional view schematically showing plugs formed on the multilayer wiring layer. Normal plugs P1 that are not defective plugs, embedded defective plugs P2 that are defective plugs, non-conductive plugs P3, and non-opening plugs P4. The semi-embedded defective plug P5 and the embedded defective plug P6 without the barrier conductor film are shown. Normally, a “plug” refers to a “normal plug”, but in the present application, a defect that has not been formed as a normal plug is also referred to as a plug in order to facilitate explanation. Also, defective plugs that are not normal plugs are distinguished from “normal plugs” as “embedded defective plugs”, “non-conductive plugs”, “non-open plugs”, and “half-embedded defective plugs”.

First, the normal plug P1 will be described. FIG. 32 shows an n-th layer (n is a natural number) wiring layer 101, a cap layer 102 on the wiring layer 101, a barrier layer 103 below the wiring layer 101, and an interlayer insulating film 104 on the cap layer 102. A connection hole 105 opened in the interlayer insulating film 104, a barrier conductor film 106 on the side wall of the connection hole 105, and a conductive film 107 embedded in the connection hole 105 are shown. The wiring layer 101 is made of, for example, Al (aluminum), the cap layer 102 is made of, for example, TiN (titanium nitride), and the barrier layer 103 is made of, for example, TiN / Ti (TiN layer on the Ti layer). The barrier conductor film 106 is made of, for example, Ti (titanium) / TiN (titanium nitride), and the conductive film is made of, for example, W (tungsten). Therefore, the plug formed by embedding the conductive film 107 in the connection hole 105 penetrating to the cap layer 102 is electrically connected to the wiring layer 101, that is, electrically connected to the wiring layer 101. Plug (normal plug) P1. The interlayer insulating film 104 is made of, for example, SiO ₂ (silicon oxide) in order to physically and electrically cut off the wiring layers.

  Next, in contrast to the normal plug P1, an embedded defective plug P2, which is a defective plug, a non-conductive plug P3, a non-opening plug P4, a semi-embedded defective plug P5, and an embedded defective plug P6 without the barrier conductor film 106. Will be described. The defective plug P2 is a plug in which the conductive film 107 embedded in the connection hole 105 is not embedded in the normal plug P1 and cannot be electrically connected to the wiring layer formed in the upper layer of the wiring layer 101. It is a plug. Further, a plug that is not coated with the barrier film 106 is a poorly plugged plug P6.

  The non-conducting plug P3 is a plug in which the connection hole 105 penetrating to the cap layer 102 is not penetrated in the normal plug P1 and cannot be brought into contact with the wiring layer, and thus is a defective plug. In addition, the non-opening plug P4 is originally a region where the normal plug P1 is formed on the wiring layer, but is not formed and cannot contact the wiring layer and the wiring layer above it. Is done. The semi-embedded defective plug P5 is a plug in which the conductive film 107 in which the connection hole 105 is completely embedded in the normal plug P1 is not completely embedded, and the wiring formed in the upper layer of the wiring layer 101 Since there is a case where the layer cannot be electrically connected, it is regarded as a defective plug.

  Such defective plugs of defective plugs, non-conductive plugs, non-open plugs, and semi-embedded defective plugs cause defects in the semiconductor integrated circuit device. Therefore, identifying the defective plug during the manufacturing process of the semiconductor integrated circuit device is important for improving the manufacturing yield.

  Next, foreign matter generated in the semiconductor integrated circuit device will be described. FIG. 33 is a schematic diagram showing an example of the foreign material 10 existing during the manufacturing process of the multilayer wiring layer of the semiconductor integrated circuit device. The state in which the foreign material 10 exists on the normal plug P1 and the interlayer not on the normal plug P1 are shown. A state of being present on the insulating film 104 is shown.

  Due to the miniaturization of the plug or the wiring, the presence of the foreign material 10 causes a failure of the semiconductor integrated circuit device. As shown in FIG. 33, when the foreign matter 10 is present on the normal plug P1, the wiring layer (not shown) formed on the normal plug P1 and electrically connected to the normal plug P1 is a foreign matter. 10 is considered to be an obstacle and cannot be electrically connected. In addition to the normal plug P1, for example, even when the foreign material 10 is present on the interlayer insulating film 104, it may affect the subsequent formation of plugs and wiring layers and cause defective plugs. It is done. Therefore, it is important to detect foreign matters during the manufacturing process of the semiconductor integrated circuit device in order to improve the manufacturing yield.

  Next, a method studied by the present inventors for detecting the above-described defective plug or foreign matter will be described. FIG. 34 is a configuration diagram schematically showing an electron microscope. Reference numeral 110 is an electron beam, reference numeral 111 is an electron gun, reference numeral 112 is a condenser lens, reference numeral 113 is an extraction electrode, reference numeral 114 is an anode electrode, reference numeral 115 is a blanking deflector, reference numeral 116 is a diaphragm, and reference numeral 117 is a reflector. Reference numeral 118 denotes an E × B deflector, and reference numeral 119 denotes a semiconductor wafer to be inspected. Reference numeral 120 is an objective lens, 121 is a scanning deflector, 122 is an X stage, 123 is a Y stage, 124 is a sample stage, 125 is a sample height detector, 126 is a secondary electron detector, Reference numeral 127 denotes a light source, reference numeral 128 denotes an optical lens, and reference numeral 129 denotes a CCD camera. Reference numeral 130 denotes a condenser lens power source, reference numeral 131 denotes a scanning signal generator, reference numeral 132 denotes an objective lens power source, reference numeral 133 denotes a sample height measuring instrument, reference numeral 134 denotes a position monitor length measuring instrument, and reference numeral 135 denotes a control circuit. Reference numeral 136 denotes a secondary electron detection signal conversion circuit, reference numeral 137 denotes an image observation monitor, reference numeral 138 denotes a secondary electron first image drawing circuit, reference numeral 139 denotes a secondary electron second image drawing circuit, and reference numeral 140 denotes a comparison operation circuit. Reference numeral 141 denotes a defect determination processing circuit, and reference numeral 142 denotes a sample chamber.

  In this image formation by an electron microscope, incident electrons accelerated to about 10 kV are used to irradiate the surface of a semiconductor wafer 119 to be inspected with electrons decelerated as irradiation energy of about 300 V to 3 kV onto the sample. The secondary electrons obtained in (1) are image-formed by the secondary electron detector 126.

  In this method, by using an electron beam, an electrical defect is detected as a change in plug contrast, that is, a so-called potential contrast defect, which is not detected by an optical inspection device using white light, laser, or UV light. It has features that can be done. In order to observe this potential contrast defect with good contrast, the current of the electron beam is set to about 100 nA (high electron beam current) so as to obtain a high SN ratio, for example, an SN ratio of 10 to 18.

FIG. 35 is a diagram showing the dependence of secondary electron emission efficiency on incident electron energy. In FIG. 35, θ ₁ to θ ₃ are angles formed by the incident direction of the electron to the sample and a normal line perpendicular to the sample, and the secondary electron emission efficiency δ becomes 1 as the incident electron becomes perpendicular to the sample. It shows that the range of incident energy exceeding is reduced. The maximum value δ _max of the secondary electron emission efficiency is proportional to the work function of the irradiated material. Under the condition that the secondary electron emission efficiency is 1 or more, for example, the non-conductive plug P3 shown in FIG. 32 can be detected as a black plug with a lowered contrast (dark potential contrast defect). On the other hand, contrast inversion occurs under conditions where the secondary electron emission efficiency is 1 or less, and defects can be detected as white and bright plugs (bright potential contrast defects).

  In general, an electron beam is incident on a sample perpendicularly, but as is clear from FIG. 35, the stage for mounting the sample to be inspected is equipped with a sample tilting function, and the sample is tilted to obtain secondary electron emission efficiency. It is possible to intentionally enlarge or reduce the region where the value of 1 becomes 1 or more, or the region where 1 becomes 1 or less.

  The detection of defects or foreign matters by this method will be described. 36A and 36B are diagrams for explaining detection of a defective plug by the method examined by the present inventors, in which FIG. 36A is a difference image, FIG. 36B is a reference image showing a planar state of the plug P, c) shows an inspection image showing the planar state of the plug P, and (d) shows a detection threshold of a defective plug.

  An inspection image (FIG. 36C) obtained by processing the secondary electron detection signal obtained by irradiating the sample with incident electrons on the secondary electron first image drawing circuit 138 and a secondary image obtained at another location. The reference image (FIG. 36B) obtained by processing the electron detection signal by the secondary electron second image drawing circuit 139 is compared by the comparison operation circuit 140 to obtain a difference image (FIG. 36A). As shown in FIG. 36 (d), the difference image brightness (gradation value) is set to a detection threshold value corresponding to each intensity, whereby an optimum threshold of the difference image brightness as a defect is set. A value is obtained, and defect determination is performed by the defect determination processing circuit, and at the same time, a defective portion is detected.

  FIG. 37 is a diagram showing an example of a reference image or an inspection image obtained at the time of a high electron beam current by the method examined by the present inventors. FIG. 37 (a) shows an embedding failure plug P2 and a normal plug P1, (b) ) Shows the non-conductive plug P3 and the normal plug P1, (c) shows the non-opening plug P4 and the normal plug P1, (d) shows the foreign material 10 on the normal plug P1, and (e) shows the foreign material 10 on the interlayer insulating film 104. ing.

  As a result of studies by the present inventors, when the electron beam current is about 100 nA, the potential contrast defect can be observed with high contrast, but the resolution is lowered. Therefore, there is a problem that it is difficult to distinguish the non-conductive plug P3 in FIG. 37B shown in FIG. 37 as a secondary electron image at the time of high electron beam current and the non-opening plug P4 in FIG. occured.

  Similarly, in the secondary electron image at the time of high electron beam current, when the defective plug P2 as shown in FIG. 37A is generated, the embedded image in the secondary electron image at the time of high electron beam current is generated. A phenomenon was encountered in which it was difficult to distinguish between the defective plug P2 and the normal plug P1.

  Further, similarly, in the secondary electron image at the time of high electron beam current, the foreign material 10 on the normal plug P1 as shown in FIG. 37 (d) can be detected, but as shown in FIG. It is difficult to detect the foreign material 10 on the interlayer insulating film 104. That is, the foreign material 10 on the interlayer insulating film 104 in FIG. 37 (e) is gradually darkened because the foreign material 10 is obstructed by the lower interlayer insulating film 104 and electrons are not supplied from the semiconductor wafer. As a result, the image formed as the secondary electron signal becomes black as shown in FIG. 5E, which is assimilated with the brightness of the interlayer insulating film 104 and becomes difficult to detect as a foreign substance.

  The objective of this invention is providing the technique which can detect and discriminate | determine the defect or foreign material on the main surface of a semiconductor wafer.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  One invention disclosed in this application relates to secondary electrons generated by irradiating an inspection region to be inspected on a main surface of a semiconductor wafer to be inspected placed on a sample stage of an electron microscope. And backscattered electrons are detected by a secondary electron detector and a backscattered electron detector, respectively, and defects or foreign matter are detected and discriminated by a detection signal conversion circuit, an image drawing circuit, a comparison operation circuit, and a defect determination processing circuit.

Moreover, the outline | summary of the other invention disclosed by this application is shown as a bullet.
1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A step of detecting secondary electrons and reflected electrons generated by irradiating an electron beam to a plurality of unit inspection regions to be inspected on a main surface of a semiconductor wafer placed on a stage of an electron microscope ;
(B) comparing the first secondary electron image formed by the secondary electrons and the second secondary electron image to form a first difference image;
(C) a step of comparing the first reflected electron image formed by the reflected electrons and the second reflected electron image to form a second difference image;
(D) A step of comparing the first difference image and the second difference image to detect defects or foreign matters in the plurality of unit inspection areas.
2. In the method of manufacturing a semiconductor integrated circuit device according to the first item, the current of the electron beam is 1 nA or more and 100 nA or less.
3. In the method of manufacturing a semiconductor integrated circuit device according to the first item, the current of the electron beam is 60 nA or more and 100 nA or less.
4). In the method of manufacturing a semiconductor integrated circuit device according to the first item, the current of the electron beam is 1 nA or more and less than 60 nA.
5. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the current of the electron beam is 1 nA or more and less than 30 nA.
6). 2. The manufacturing method of a semiconductor integrated circuit device according to claim 1, wherein the electron beam current is 1 nA or more and less than 10 nA.
7). 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the detection of the secondary electrons and the reflected electrons includes a first detector for the secondary electrons and a second detection for the reflected electrons. Use a vessel.
8). In the method of manufacturing a semiconductor integrated circuit device according to the item 1, a plurality of plugs are formed in the same layout in each of the plurality of unit inspection regions.
9. The method for manufacturing a semiconductor integrated circuit device according to the item 1, further includes the following steps.
(E) forming an insulating film on the wiring layer formed on the main surface of the semiconductor wafer;
(F) After the step (e), after forming a resist film on the insulating film, a step of exposing a pattern of connection holes to the resist film;
(G) After the step (f), after developing the resist film to form a resist pattern, etching the insulating film using the resist pattern as an etching mask;
(H) After the step (g), a step of embedding a conductive film in the connection hole;
(I) a step of discriminating the defect from an imbedding defect, non-conduction, or non-opening defect;
(J) When the defect of the embedding defect occurs in the step (h), the non-conductive defect occurs in the step (g), or the non-opening defect occurs in the step (f). The step of determining.
10. A method of manufacturing a semiconductor integrated circuit device including the following steps.
(A) First secondary electrons generated by irradiating a first electron beam to a plurality of unit inspection regions to be inspected on a main surface of a semiconductor wafer placed on a stage of an electron microscope Detecting step;
(B) a second electron beam lower than the current value of the first electron beam with respect to a plurality of unit inspection regions to be inspected on the main surface of the semiconductor wafer placed on the stage of the electron microscope Detecting second secondary electrons generated by irradiation with;
(C) comparing the first secondary electron image formed by the first secondary electrons and the second secondary electron image to form a first difference image;
(D) comparing a third secondary electron image formed by the second secondary electrons with a fourth secondary electron image to form a second difference image;
(E) A step of comparing the first difference image and the second difference image to detect defects or foreign matters in the plurality of unit inspection areas.
11. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein the current of the first electron beam is 60 nA or more and 100 nA or less, and the current of the second electron beam is 1 nA or more and less than 60 nA.
12 11. The method for manufacturing a semiconductor integrated circuit device according to the item 10, further including the following steps.
(F) a step of detecting reflected electrons simultaneously with the detection of the first or second secondary electrons;
(G) comparing the first reflected electron image formed by the reflected electrons and the second reflected electron image to form a third difference image;
(H) A step of comparing the first difference image, the second difference image, and the third difference image to detect defects or foreign matters in the plurality of unit inspection areas.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  By forming a secondary electron image and a reflected electron image and making a determination, it is possible to detect a defect or foreign matter in the plug formed on the main surface of the semiconductor wafer.

  Before describing the present invention in detail, the meaning of terms in the present application will be described as follows.

  A semiconductor integrated circuit device is not only a semiconductor substrate such as a silicon substrate (silicon wafer) or a sapphire substrate, or an insulating substrate, but a TFT (Thin-Film) unless otherwise specified. -Transistor) and STN (Super-Twisted-Nematic) liquid crystal such as those made on other insulating substrates typified by glass.

  In addition, the substrate is a single crystal silicon substrate (generally a substantially planar circular shape) used for manufacturing a semiconductor integrated circuit, an epitaxial silicon substrate, a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, and a composite thereof. It refers to a target substrate and is not limited to a semiconductor wafer.

  In addition, when limited to a material in the present application, for example, “silicon (Si)” means a material containing silicon as a main component except when particularly pure material is specified (for example, Including SiGe). The same applies to “aluminum (Al)” (including, for example, an AlCu alloy).

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a configuration diagram schematically showing an electron microscope according to the first embodiment. The electron microscope according to the first embodiment is different from the electron microscope shown in FIG. 34 in the reflected electron detector 1, the reflected electron detection signal conversion circuit 2, the reflected electron first image drawing circuit 3, and the reflected electron second image drawing circuit 4. Is added.

  As the secondary electron detector 126 shown in FIG. 1, for example, a combination of a scintillator (phosphor) and a photomultiplier tube can be applied. In order to efficiently collect secondary electrons with low energy emitted from the semiconductor wafer 119 to be inspected by electron beam irradiation, a positive potential of about 10 kV is applied to the sample in the scintillator. The accelerated secondary electrons are converted into visible light by a scintillator, guided to a photomultiplier tube, converted into an electric signal and amplified.

  Further, as the backscattered electron detector 1 shown in FIG. 1, for example, a semiconductor detector using a pn junction can be applied. The reflected electron detector 1 is disposed immediately above the semiconductor wafer 119 to be inspected, and takes out reflected electrons as an electric signal. It is also possible to employ a method in which both secondary electrons and reflected electrons are efficiently extracted as an electronic signal with a single detector using an annular detector to which a semiconductor detector is applied.

  FIG. 2 is a flowchart showing a method of inspecting a semiconductor wafer to be inspected using the electron microscope of FIG. 1 (hereinafter referred to as “electron beam inspection method”). First, a semiconductor wafer cassette is set on the loader (step S10). That is, a semiconductor wafer cassette containing a semiconductor wafer to be inspected is set on a loader.

  Subsequently, an inspection mode is selected, and inspection conditions are input (steps S20 and S30). For example, a semiconductor wafer to be inspected is selected from the operation screen and an inspection condition file registered in advance is designated.

  Subsequently, it is confirmed whether or not a condition different from the normal inspection is added (option addition) (step S40). For example, it is possible to optionally change conditions such as data output destination, inspection area change, defect visual confirmation presence / absence, and automatic / manual (steps S41 to S43).

  Subsequently, start / semiconductor wafer loading is performed (step S50). That is, the semiconductor wafer to be inspected is loaded into the sample exchange chamber by the semiconductor wafer transfer means. As shown in FIG. 1, the semiconductor wafer 119 to be inspected is mounted on a sample stage 124, held and fixed, and then evacuated. When the sample exchange chamber reaches a certain degree of vacuum, it is transferred to the sample chamber 142 for inspection. Is done. In the sample chamber 142, the sample holder is placed on the X stage 122 and the Y stage 123 and held and fixed.

  Subsequently, the calibration sample is moved to the calibration pattern position on the stage (step S60). The sample holder is mounted with a calibration sample for adjusting the focus and astigmatism, which are the irradiation conditions of the incident electron beam. When the semiconductor wafer 119 to be inspected is loaded into the sample chamber 142, the X stage 122 and the Y stage 123 are moved based on the position coordinates recorded in advance so that the calibration sample is placed under the electron optical system.

  Subsequently, beam calibration is performed (step S70). Then, an electron beam image for calibration is acquired, and focus and astigmatism adjustments are performed manually or automatically. At this time, based on the contents of the inspection condition file that has already been input and set, irradiation energy of the incident electron beam, electron beam current, pixel size, detection system gain and brightness adjustment parameters, filter and defect determination in image processing For example, a threshold value is set and various images are acquired and displayed after these parameters are input.

  FIG. 3 is a diagram showing an example of changing the electron beam current set value during inspection in the electron microscope of FIG. It is not limited to inputting parameters, but can be easily changed by setting conditions so that low electron beam current inspection, medium electron beam current inspection, and high electron current inspection can be performed in advance. The set value of the electron beam current can be set to, for example, 10 nA for the low electron beam current test, 60 nA for the medium electron beam current test, and 100 nA for the high electron beam current test, for example.

  Subsequently, the wafer is moved to the semiconductor wafer alignment mark position and alignment is executed (step S80). Next, the semiconductor wafer is moved to the calibration position on the semiconductor wafer and calibration is executed (step S90).

  Subsequently, an inspection is performed (step S100). That is, when the alignment of the semiconductor wafer 119 to be inspected is completed, a secondary electron image and a backscattered electron image of the semiconductor wafer 119 to be inspected are acquired, and inspection is executed.

  FIG. 4 is a plan view schematically showing the semiconductor wafer 119 to be inspected. FIG. 4A shows the inspection region 5 on the semiconductor wafer 119 to be inspected, and FIG. 4B shows the units in the inspection region 5. Inspection areas 5a and 5b are shown. Here, FIG. 4B shows a case where, for example, a plurality of plugs P are laid out at regular intervals, and the layout of the plurality of plugs P is the same in the unit inspection areas 5a and 5b. Yes. The plurality of plugs P include normal plugs and defective plugs.

  The inspection area 5 is designated in advance in the inspection condition file. At the time of inspection, an X-ray 122 and a Y-stage 123 are moved continuously or intermittently to irradiate a predetermined region of the semiconductor wafer 119 to be inspected, and secondary electron images and reflected electron images are sequentially formed. The secondary electron image and the reflected electron image are images formed by secondary electrons and reflected electrons generated when the incident electron beam is irradiated onto the inspection semiconductor wafer 119. Acquired as an image by reflected electrons. Here, in the present application, a region acquired as a secondary electron image and a reflected electron image is set as a unit inspection region. For example, the region obtained by irradiating the inspection region 5 of the semiconductor wafer 119 to be inspected shown in FIG. 4B with the incident electron beam and acquired as the secondary electron image and the reflected electron image becomes the unit inspection region 5a, for example.

  Next, while forming the secondary electron image and the reflected electron image, the image signal is passed through the secondary electron detection signal conversion circuit 136 and the reflection electron detection conversion circuit 2, and the secondary electron first image drawing circuit 138, the secondary electron first The image is transmitted to the two-image drawing circuit 139, the backscattered electron first image drawing circuit 3, and the backscattered electron second image drawing circuit 4, and the comparison operation circuit 140 performs processing such as difference image formation while comparing each image signal.

  For example, when the electron beam current is about 100 nA and the plug P on the semiconductor wafer 119 to be inspected includes the non-conductive plug P3 and the non-opening plug P4 which are defects of the plug P in addition to the normal plug P1, Detection and determination of the non-conductive plug P3 and the non-opening plug P4 will be described.

  FIG. 5 is an explanatory diagram showing secondary electron images and reflected electron images for the normal plug P1, the non-conductive plug P3, and the non-opening plug P4, and FIG. 5 (a) shows the normal plug P1 and the non-conductive plug P3 or non-conductive plug P3. Secondary electron first image of secondary plug P4, secondary electron second image and its difference image, FIG. 5B shows the reflected electron first image, reflected electron second image of normal plug P1 and non-conductive plug P3, and those FIG. 5C shows the reflected electron first image, the reflected electron second image, and the difference image of the normal plug P1 and the non-opening plug P4.

  As shown in FIG. 5, a secondary image is used as a reference image, a secondary electron first image is used as an inspection image, and a difference image between the reference image and the inspection image is formed to determine the presence or absence of a defect. can do. The secondary electron first image and the secondary electron second image correspond to the unit inspection areas 5a and 5b in FIG. 4B, respectively. Therefore, when a defect location is detected from the difference image, it can be detected that there is a defect in the unit inspection region 5a that is the region indicated by the secondary electron first image that is the inspection image.

  Further, as shown in FIG. 5A, the normal plug P1 and the non-conductive plug P3 or the non-opening plug P4 are distinguished from the secondary electron first image, the secondary electron second image, and their difference images. can do. However, as explained in the problem to be solved by the invention, the non-conductive plug P3 and the non-opening plug P4 are distinguished from the secondary electron first image, the secondary electron second image, and their difference images. Can not do it. Therefore, as shown in FIG. 5B and FIG. 5C, the non-conductive plug P3 and the non-opening plug P4 are obtained by using the reflected electron first image, the reflected electron second image, and the difference image thereof. A method that enables distinction is presented.

  That is, a defect is detected from the secondary electron first image, the secondary electron second image and the difference image thereof, and the reflected electron first image, the reflection electron second image and the difference image thereof, and the non-conductive plug P3. It can be determined that the plug is non-opening plug P4.

  Subsequently, defect location image acquisition, visual confirmation, and classification input are performed (step S110). That is, after the inspection is completed, images of these defective portions are confirmed, and necessary operations such as image acquisition, visual confirmation, and classification input, and storage and transfer to an external storage medium are performed.

  Subsequently, the inspection result is output (step S120). That is, the location determined as a defect by the defect determination processing circuit 141 is automatically stored with the coordinates of the defective location, the signal value, the size of the defect, etc., and there is a defect at the corresponding location on the semiconductor wafer map in the operation screen. Is displayed. Also, by specifying these marks, the X stage 122 and the Y stage 123 are moved to the specified coordinates, and the secondary electron image and the reflected electron image of the specified coordinates are displayed on the image observation monitor 137. Moreover, it is also possible to display a secondary electron image and a reflected electron image of the same adjacent location, and a difference image thereof.

  Subsequently, the semiconductor wafer to be inspected is unloaded (step S130). That is, the inspection is finished and the semiconductor wafer 119 to be inspected is unloaded.

  As described above, a defective plug formed on the main surface of the semiconductor wafer can be detected with high sensitivity. In other words, the present invention is not limited to potential contrast defects, and it is also effective for increasing the sensitivity of shape defect detection by a detection method using reflected electrons.

  Here, the reason why the detection method using the reflected electrons is more effective in increasing the sensitivity of the shape defect detection will be described below. FIG. 6 is a spectrum diagram of electrons emitted from the irradiated surface when irradiated with incident electrons. FIG. 7 is an explanatory view schematically showing the behavior of secondary electrons and reflected electrons with respect to the detector.

  When the generation amount of the emitted electrons is viewed according to the energy of the electrons, the secondary electrons are low energy within 10 eV of the region A, and the reflected electrons are high energy of several hundred eV to several keV of the region B. When a part of the incident beam collides with an atom in the sample, secondary electrons give energy to the electron in the atom. When the applied energy exceeds a certain value, electrons in the atom jump out of the sample. is there. For this reason, the secondary electrons are floating in the vicinity of the sample surface with a low energy of about several eV.

  On the other hand, the reflected electrons are electrons that are scattered elastically or inelasticly in the sample, and jump out to the sample surface on which the electrons are incident, and therefore have almost the same energy as the incident electrons. For this reason, since the reflected electrons are emitted at an emission angle depending on the incident angle of the sample, the sample shape can be strongly reflected in the image as a contrast by detecting the reflected electrons and forming an image.

  FIG. 8 is an explanatory view schematically showing the behavior of secondary electrons and reflected electrons on the surface of the semiconductor wafer to be inspected. As shown in FIG. 8A, the secondary electrons are strongly affected by the electric field on the sample surface because the energy of the secondary electrons at the time of emission is low. A normal plug has a potential of an electric field almost parallel to the sample surface, so it is relatively easy to extract secondary electrons, but secondary electrons emitted at non-conducting locations are strongly affected by the electric field on the sample surface, and the electric field Is returned to the plug again. Therefore, a potential contrast is generated, and a dark potential contrast defect is generated, so that a non-conductive portion can be detected.

  On the other hand, as shown in FIG. 8B, the reflected electrons are high in the energy of the reflected electrons at the time of emission, and thus are not affected by the electric field on the sample surface. The contrast is uniform and does not contribute to image formation as a potential contrast defect. However, since it has a strong directionality with respect to the sample surface, it is possible to exert its power to increase the sensitivity with respect to shape defects or imbedding defects.

  Next, a method for manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to the drawings.

  FIG. 9 is a flowchart showing an outline of the process flow of the semiconductor integrated circuit device. After element isolation and semiconductor elements are formed (step S200), an interlayer insulating film is formed (step S210). Next, after forming a connection hole with a semiconductor element or the like, a conductive film is embedded to form a contact plug (step S220). Next, film formation and processing for forming the first wiring layer are performed (step S230). Next, after depositing an interlayer insulating film on the first wiring layer (step S210), a connection hole with the second wiring layer is formed, and the conductive film is buried via as well as the contact plug. A plug is formed (step S220). Next, a second wiring layer is formed in the same manner as the first layer (step S230). For example, if the semiconductor integrated circuit device has a four-layer wiring structure, after repeating this cycle up to the fourth wiring layer, a passivation film is deposited (step S240), and a pad for electrical connection to the outside is formed. And exit.

  Next, plug formation (step S220) of the semiconductor integrated circuit device shown in FIG. 9 will be described in detail. FIG. 10 is a cross-sectional view schematically showing a semiconductor integrated circuit device having a four-layer wiring structure. FIG. 11 is a flowchart showing an example of the process flow of the via plug formed in the multilayer wiring layer. 12 to 17 are cross-sectional views schematically showing the semiconductor integrated circuit device during the manufacturing process. 18 and 19 are explanatory views schematically showing secondary electron images and reflected electron images obtained by the electron beam inspection method. An example in which the electron beam inspection method described in this embodiment is applied in the manufacturing process of the via plug P on the wiring layer 101 illustrated in FIG. 10 will be described.

  As shown in FIG. 10, a wiring layer 101 having a cap layer 102 and a barrier layer 103 above and below the wiring layer 101, a via plug P in which a conductive film 107 is surrounded by a barrier conductor film 106, and A cross-sectional view of a wiring layer 101 and a plug P having a four-layer wiring structure having an interlayer insulating film 104 that physically and electrically cuts off the wiring layers 101 is shown.

  An example of the cap layer 102 is TiN (titanium nitride), an example of the barrier layer 103 is TiN / Ti (TiN layer on the Ti layer), and an example of the wiring layer 101 is Al (aluminum). be able to.

As an example of the interlayer insulating film 104, PTEOS (plasma TEOS: tetraethyl orthosilicate: Si (OC ₂ H ₅ )) / PSiO (plasma SiO) / SiOF (fluorine-doped SiO ₂ ) / SRO (silicon rich oxide) Can be mentioned.

  An example of the barrier conductor film 106 is Ti (titanium) / TiN (titanium nitride), and an example of the conductive film 107 is W (tungsten).

  By applying the electron beam inspection method shown in the present embodiment before plug embedding and after plug embedding at the conduction state analysis locations C1 to C3 shown in FIG. It is possible to determine whether the plug is defective.

  As shown in FIG. 12, after the antireflection film 6 and the positive photoresist film 7 are formed on the interlayer insulating film 104 (step S221), exposure is performed using the photomask 9 on which the mask pattern 8 is formed. This is performed (step S222). Here, it is assumed that the foreign material 10 exists on the photoresist film 7. Further, when exposure is performed, the portion to which the foreign material 10 is attached is not exposed to the foreign material 10, and a non-opening portion 11 shown in FIG. 13 is formed. The non-opening portion 11 becomes the non-opening plug P4 after the plug formation process is completed. Note that reference numeral 16 in FIG. 12 denotes an exposure source.

  Subsequently, as shown in FIG. 13, development is performed and the interlayer insulating film 104 is etched using the photoresist film 7 as a mask (step S223). Here, the non-conductive hole 12 may be formed due to insufficient etching. This non-conductive hole 12 is a place where the hole processing is not sufficient, and becomes a non-conductive plug P3 after the plug forming process. Note that the connection hole 105 shown in FIG. 13 is a portion that has been etched normally.

  Subsequently, as shown in FIG. 14, the photoresist film is removed by ashing (step S224). The electron beam inspection method described above can be applied at this stage. For example, when a secondary electron image with a high electron beam current of 100 nA is used for inspection, as shown in FIG. 18, the connection hole 105 is a normal connection hole, and the non-conduction hole 12 and the non-opening 11 are potential contrast defects. Detected. That is, when the irradiation energy is in a range exceeding the secondary electron emission efficiency 1, the non-conductive hole 12 and the non-opening 11 are darker and darker than the normal connection hole 105. Moreover, when it inspects using a backscattered electron image, it can discriminate | determine that the non-conduction hole 12 exists and a non-opening part 11 does not have a hole.

  Further, for example, when the foreign material 10 is present on the interlayer insulating film 104 so as to block the connection hole 105, as shown in FIG. 18, the secondary electron image with a high electron beam current is compared with a normal connection hole 105. As in the case of the non-conductive hole 12 and the non-opening portion 11, the foreign material 10 is detected as a potential contrast defect. Further, when inspected using the reflected electron image, the foreign material 10 can be distinguished from the non-conductive hole 12 and the non-opening 11.

  Subsequently, as shown in FIG. 15, the barrier conductor film 106 is covered in the connection hole 105 (step S225). Here, when the foreign material 10 adheres so as to block the connection hole 105, the barrier conductor film 106 is not covered in the connection hole 105, and further, the conductive film in the subsequent process is not embedded. Therefore, the location of the connection hole 105 becomes a buried defective plug (no barrier conductor film) P6 after the plug forming process is completed.

  Subsequently, as shown in FIG. 16, the conductive film 107 is embedded in the connection hole 105 (step S226). Here, when the foreign material 10 adheres to the connection hole 105 after the barrier conductor film 106 is embedded until the conductive film 107 is embedded, the conductive film 107 is not embedded in the connection hole 105. Therefore, the location of the connection hole 105 becomes a poorly plugged plug (with a barrier conductor film) P2 after the plug forming process is completed. In FIG. 16, reference numeral 12 'denotes a non-conductive plug.

  Further, for example, when the connection hole 105 has a high aspect ratio, or when the diameter of the connection hole 105 is small, a seam (seam) due to insufficient gas entering the conductive film 107 in the connection hole 105 is obtained. ) 15 may occur and implantation failure may occur. Therefore, the location of the connection hole 105 becomes the semi-embedded defective plug P5 after the plug formation process is completed.

  Subsequently, as shown in FIG. 17, the uneven step on the surface after embedding the conductive film 107 is flattened (step S227). Examples of the planarization treatment include a technique such as CMP (chemical and mechanical polishing). The plug forming process is thus completed. In the above-mentioned semi-embedded defective plug P5, the charge accumulation by CMP after embedding the conductive film 107 reacts with the CMP chemical solution to generate a current between the plug and the substrate, thereby dissolving the conductive film 107. It may be formed also by what is called a battery effect.

  In the stage after the manufacturing process shown in FIG. 17, that is, after the plug formation process is completed, the above-described electron beam inspection method can be applied to detect and determine plug defects after filling. As shown in FIG. 19, for example, using a secondary electron image of a high electron beam current of 100 nA, a normal plug P1, a poorly embedded plug P2, a semi-embedded defective plug P5, and an embedded defective plug without the barrier conductor film 106 are used. P6, and non-conductive plug P3 and non-opening plug P4 are detected and determined. Subsequently, using the reflected electron image of the high electron beam current, the normal plug P1, the embedded defective plug P2, the semi-embedded defective plug P5, the embedded defective plug P6 without the barrier conductor film, the non-conductive plug P3, and the non-opening The plug P4 can be detected and determined.

  Therefore, for example, during the manufacturing process of the semiconductor integrated circuit device, it is possible to detect a defective plug by applying the electron beam inspection method shown in the present embodiment, and further to identify a specific defective plug from various defective plugs. By examining the process in which a large amount of the identified defective plugs are generated and the abnormalities and conditions of the processes before and after the process, it is possible to suppress a decrease in the manufacturing yield of the semiconductor integrated circuit device due to the defective plugs. In other words, the manufacturing yield of the semiconductor integrated circuit device can be improved.

  More specifically, referring to FIG. 11, after the plug formation process is completed, if the embedding failure plug P2 is detected by applying the electron beam inspection method shown in this embodiment, the conductive film embedding process (step The manufacturing yield of the semiconductor integrated circuit device can be improved by investigating abnormalities and conditions of S226) and the processes before and after that. Similarly, when the non-conductive plug P3 is detected, the etching process (step S223), when the non-opening plug P4 is detected, the exposure process (step S222), and when the semi-embedded defective plug P5 is detected By investigating the conductive film embedding process (step S226) or planarization process (step S227), in the case of an improper embedding plug P6, the barrier conductor film covering process (step S225), and the abnormalities and conditions before and after the process, The manufacturing yield of the semiconductor integrated circuit device can be improved.

  Further, as described with reference to FIG. 5, the non-conductive plug P3 and the non-opening plug P4 (which could not be distinguished only by the secondary electron image in the range from the middle electron beam current to the high electron beam current (about 60 nA to 100 nA) ( 5 (a)) can be discriminated by using it together with the reflected electron image. That is, as shown in FIG. 5, for the potential contrast defect detected by the medium electron beam current or the high electron beam current, by comparing the reflected electron images, the reflected electron difference image has no defect signal. A non-conductive plug P3 (see FIG. 5B) and a defect signal appear as a non-opening plug P4 (see FIG. 5C).

  Further, the two types of defective filling plugs P2 and P6 are obtained by using a reflection electron image, and the defective filling plug P2 covered with the barrier conductor film and the defective filling plug not covered with the barrier conductor film in FIG. Since P6 can be distinguished from the image, it is possible to limit the generation process of the foreign matter that causes the occurrence of the defective plug, the generation process and the generation process of the defect. Can be used to identify

  In addition, when an incident electron region in which the secondary electron emission efficiency is 1 or more is used, the foreign matter 10 on the normal plug P1 (see FIG. 37 (d)) is white and bright in the defect inspection using the secondary electron image. While it can be manifested as a potential contrast defect, the foreign material 10 (see FIG. 37 (e)) on the interlayer insulating film 104 is in a black and dark state, so that it does not manifest and is not easily recognized as a defect. There was a problem. Even in such a case, it is possible to detect defects by emphasizing the shape by using the reflected electron image and revealing the foreign material 10.

(Embodiment 2)
The first embodiment detects secondary electrons and reflected electrons generated by irradiating an electron beam with an electron beam current of 60 nA or more and 100 nA or less onto a semiconductor wafer surface, and detects defects or foreign matters on the semiconductor wafer surface. Explained when to do. In this embodiment, after the inspection performed with the high electron beam current of 60 nA or more and 100 nA or less shown in the above embodiment, the detection is performed with the low electron beam current of 1 nA or more and less than 60 nA, and the semiconductor wafer surface is more reliably detected. A case where a defect or a foreign object is detected will be described. In addition, the description which overlaps with the said embodiment is omitted.

  In the present embodiment, the electron beam inspection method described in the first embodiment is applied after the inspection performed with a high electron beam current of 60 nA or more and 100 nA or less. When performing the beam calibration (step S70), for example, a low electron beam current of 10 nA can be set. In addition, as shown in FIG. 3, by setting the conditions so that the low electron beam current inspection, the middle electron beam current inspection, and the high electron beam current inspection can be performed in advance, the low electron beam current inspection can be easily performed. And can be changed.

  Therefore, in the present embodiment, a secondary electron image and a reflected electron image having a high electron beam current, and a secondary electron image and a reflected electron image having a low electron beam current are detected. These image signals are passed through the secondary electron detection signal conversion circuit 136 and the reflected electron detection signal conversion circuit 2 shown in FIG. 1, and further, a secondary electron first image drawing circuit 138, a secondary electron second image drawing circuit 139, The comparison operation circuit 140 performs processing such as difference image formation while transmitting the image to the reflected electron first image drawing circuit 3 and the reflected electron second image drawing circuit 4 and comparing each image signal.

  FIG. 20 is an explanatory diagram showing a secondary electron image at the time of high electron beam current and a secondary electron image at the time of low electron beam current for the normal plug P1, the embedding failure plug P2, and the non-conductive plug P3. a) Secondary electron first image, secondary electron second image and difference image of normal plug P1 and non-conductive plug P3 at high electron beam current, FIG. 20 (b) is normal plug at high electron beam current The secondary electron first image of the P1 and the poorly embedded plug P2, the secondary electron second image and the difference image thereof, FIG. 20C shows the secondary of the normal plug P1 and the poorly embedded plug P2 at the time of low electron beam current. The electronic 1st image, the secondary electron 2nd image, and its difference image are shown.

  As shown in FIG. 20, using the secondary electron second image as the reference image and the secondary electron first image as the inspection image, a difference image between the reference image and the inspection image is formed, and the presence or absence of a defect is determined. can do. The secondary electron first image and the secondary electron second image correspond to the unit inspection areas 5a and 5b in FIG. 4B, respectively. During inspection, a differential image is formed while the X stage 122 and Y stage 123 are moved continuously or intermittently, and the presence or absence of defects is determined with inspection sensitivity corresponding to the inspection threshold (see FIG. 36). Go.

  In the high electron beam current inspection, after removing the resist by ashing (see FIG. 14) and flattening the uneven step after embedding the conductive film (see FIG. 17), as shown in FIG. The normal plug P1 and the non-conductive plug P3 can be detected as potential contrast defects. However, as a side effect, the defective plug P2 in which the plug material is not embedded at all becomes equivalent to the connection hole 105 that is normally opened at the stage after the resist is removed by ashing (see FIG. 14). For this reason, as shown in FIG. 20B, the normal plug P1 and the embedded defective plug P2 have the same contrast.

  However, as shown in FIG. 20C, the buried defective plug P2, which could not be distinguished by the high electron beam current inspection shown in FIG. 20B, is used with a low electron beam current (ideally about 1 nA). It can be detected by comparison inspection between the secondary electron images. This is because the emission angle of the incident electrons is narrowed by the condenser lens and the objective lens in order to obtain a low electron beam current, so that the trajectory of the incident electrons is narrowed and the substantial resolution is improved. Specific numerical values of the emission angle are disclosed in Japanese Patent Laid-Open No. 2003-133379.

  FIG. 21 is an explanatory diagram showing the appropriateness of detection of each defect for each electron beam current inspection. FIG. 22 is an explanatory diagram showing the influence on the image acquisition time with respect to the electron beam current.

In FIG. 21, the inspection suitability is shown as a comparison table divided into a low electron beam current inspection and a middle / high electron beam current inspection. Further, Non-Patent Document 1 discusses an image acquisition time with respect to an electron beam current, and it is generally known that an image acquisition time increases when a low electron beam current is used as shown in FIG. . Therefore, when using a low electron beam current, it is recommended to perform a fixed point inspection with limited inspection points of the sample to be inspected. In the above examination, from FIG. 22, it is considered appropriate to use an electron beam current of about 10 nA which requires about 16 minutes per 1 cm ² as an inspection time applied in an actual semiconductor wafer manufacturing process.

  Next, the case where the electron beam inspection method shown in the present embodiment is applied in the manufacturing process of the via plug P on the wiring layer 101 shown in FIG. 10 will be described. FIG. 23 is an explanatory view schematically showing a secondary electron image and a reflected electron image obtained by the electron beam inspection method.

  First, for example, using a secondary electron image of a high electron beam current of 100 nA, non-conducting with a normal plug P1, a poorly embedded plug P2, a semi-embedded defective plug P5, and a defective defective plug P6 without a barrier conductor film. The plug P3 and the non-opening plug P4 are detected and discriminated. Subsequently, using the secondary electron image of the low electron beam current, the normal plug P1, the embedded defective plug P2, the semi-embedded defective plug P5, the embedded defective plug P6 without the barrier conductor film, the non-conductive plug P3 and the non-conductive plug P3 are used. The opening plug P4 can be detected and discriminated. Subsequently, using the reflected electron image of the high electron beam current or the low electron beam current, the normal plug P1, the embedded defective plug P2, the semi-embedded defective plug P5, the embedded defective plug P6 without the barrier conductor film, The conductive plug P3 and the non-opening plug P4 can be detected and discriminated more reliably.

(Embodiment 3)
In the first and second embodiments, the application of the electron beam inspection method in the manufacturing process of the plug P on the wiring layer 101 shown in FIG. 10 has been described. In the present embodiment, application of an electron beam inspection method in the process of manufacturing a Cu dual damascene will be described. In addition, the description which overlaps with the said Embodiment 1 and 2 is omitted.

24 to 30 are cross-sectional views schematically showing the semiconductor integrated circuit device during the manufacturing process. Insulating film barrier layer composed of liner layer (Cu diffusion preventing layer) 21, etch stopper layer 22, hard mask layer 23, Cu interlayer insulating film 24, Cu plating layer 25, and Cu seed film / barrier conductor film 26 An example of a cross-sectional configuration of a Cu dual damascene is shown. An example of the liner layer 21 and the etch stopper layer 22 may be SiCN, and an example of the hard mask layer 23 may be SiN. Moreover, TEOS / FSG (SiO ₂ doped with F) can be cited as an example of the interlayer insulating film 24 for Cu. An example of the barrier conductor film 26 under the Cu seed film is Ta (tantalum) / TaN (tantalum nitride).

  First, as shown in FIG. 24, the photoresist film 7 formed on the antireflection film 6 is exposed and developed. Subsequently, as shown in FIG. 25, only the hard mask layer 23 is grooved. Subsequently, as shown in FIG. 26, the photoresist film 7 is removed, and after forming the antireflection film 6, the photoresist film 7 is formed again, and exposure and development are performed.

  Subsequently, as shown in FIG. 27, via processing is performed up to the liner layer 21 on the Cu plating layer 25. Subsequently, as shown in FIG. 28, the photoresist film 7 is removed, and groove processing is performed using the hard mask layer 23 as a mask.

  Subsequently, as shown in FIG. 29, the Cu surface appears at the stage where the liner layer 21 on the Cu plating layer 25 is processed. Here, an electron beam inspection method can be applied to the conduction state analysis portion C4 to perform a defect inspection before Cu filling. For example, when there is a residual film of the liner layer 21 on the Cu plating layer 25 in FIG. 29, when via processing is insufficient, or when an insulating reaction product is deposited by etching during via processing. The corresponding part can be detected as a potential contrast defect. At this stage, when a secondary electron image of a high electron beam current, a medium electron beam current, or a low electron beam current is used for the inspection, in the range where the irradiation energy exceeds the secondary electron emission efficiency 1, non-conducting, residual film When an insulative reaction product is deposited, and a non-opening via portion becomes a black potential contrast defect. In addition, when an inspection is performed using a backscattered electron image, if there is a non-conductive hole, a residual film at the bottom of the conductive hole, or an insulating reaction product deposited on the bottom of the conductive hole, the presence of the hole is indicated. It can be distinguished that there is no part. Similarly, even when the groove processing is insufficient, it is possible to detect a defect as a pattern defect that is a residue on the etch stopper layer 22 in the groove or a defective shape of the groove itself.

  Subsequently, as shown in FIG. 30, after the Cu seed film / barrier conductor film 26 is coated, Cu electrolytic plating and Cu planarization are performed using the Cu seed film as a seed layer to form a Cu plating layer 25. Here, as the Cu planarization treatment, CMP (Chemical Mechanical Polishing) can be cited as an example.

  Here, an electron beam inspection method can be applied to the conduction state analysis portion C5. When inspection is performed using a secondary electron image of a high electron beam current, a medium electron beam current, or a low electron beam current, non-conduction and non-opening of the via portion can be detected as a potential contrast defect. Further, when the inspection is performed using the reflected electron image, the shape defect of the groove can be detected as a pattern defect.

  As described above, at the stage of processing the liner layer 21 on the Cu plating layer 25 shown in FIG. 29, the residue on the etch stopper layer 22 in the groove or the shape defect in the groove and via is an image using reflected electrons. In the via portion, non-conduction or non-opening can be distinguished from a secondary electron image and a reflected electron image by a high electron beam current, a medium electron beam current, or a low electron beam current. Similarly, when an insulating reaction product is deposited by etching in the via portion or the groove portion, the location can be detected as a potential contrast defect.

  In addition, in the stage of FIG. 30, the via portion non-conduction can be detected by a secondary electron image by a high electron beam current, a medium electron beam current, or a low electron beam current, and in addition, a secondary electron image of a groove portion non-opening It is also possible to make a distinction with a reflected electron image. In addition, a via portion conduction failure location can be detected as a potential contrast defect.

  In both cases of FIG. 29 and FIG. 30, it is possible to detect the location where a groove (wiring portion) shape defect, pattern defect, or the like has occurred using either a secondary electron image or a reflected electron image as a defect. Yes, in the case of using a reflected electron image, in addition to foreign matter and Cu embedding failure, it is a powerful method for revealing so-called shape defects and pattern defects such as chipping and disconnection of wiring, or Cu scratches generated at the leveling process stage. It becomes.

  The electron beam inspection method shown in the present application is not limited to the dual damascene structure shown in the present embodiment, but is the same in the single damascene structure, and the embedding material is limited to Cu electrolytic plating. However, it is clear that the same effect can be obtained even by using possible materials and methods.

  FIG. 31 is a cross-sectional view schematically showing a semiconductor integrated circuit device having local connection plugs and contact plugs.

  A local connection hole or a local connection plug (conduction) having the form of a local connection hole or local connection plug (conduction state analysis location C6) or a shared contact (distributed connection between a gate and a source / drain diffusion layer) as shown in FIG. The electron beam inspection method can also be applied to the state analysis location C7) and the contact hole (connection hole) or contact plug (conduction state analysis location C8) on the local connection plug.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the case where the defect or foreign matter on the main surface of the semiconductor wafer is applied to detection and discrimination has been described. However, the present invention is also applicable to metal materials, medical materials, biomaterials, electrical / electronic device materials, and the like. can do.

  The present invention is widely used in the manufacturing industry for manufacturing semiconductor integrated circuit devices.

It is a block diagram which shows typically the electron microscope in Embodiment 1 of this invention. It is the flowchart which showed the method to test | inspect a to-be-inspected semiconductor wafer using the electron microscope of FIG. It is a figure which shows an example of the electron beam current setting value change at the time of the inspection in the electron microscope of FIG. It is a top view which shows typically a to-be-inspected semiconductor wafer, (a) shows an inspection field on a to-be-inspected semiconductor wafer, and (b) shows a unit inspection field in an inspection field. It is explanatory drawing which shows the secondary electron image and reflected electron image with respect to a normal plug, a non-conduction plug, and a non-opening plug, (a) is a normal plug and a non-conduction plug or a non-opening plug, (b) is a normal plug and non- Conductive plug, (c) is an explanatory diagram of a normal plug and a non-opening plug. It is a spectrum figure of the electron discharge | released from a to-be-irradiated surface when incident electron is irradiated. It is explanatory drawing which shows typically the behavior of the secondary electron and reflected electron with respect to a detector. It is explanatory drawing which shows typically the behavior of the secondary electron and reflected electron in the to-be-inspected semiconductor wafer surface. It is a flowchart which shows the outline of the process flow of a semiconductor integrated circuit device. It is sectional drawing which shows typically the semiconductor integrated circuit device of a 4 layer wiring structure. It is a flowchart which shows an example of the process flow of the plug for vias formed in the multilayer wiring layer. FIG. 3 is a cross-sectional view schematically showing the semiconductor integrated circuit device during the manufacturing process in the first embodiment. FIG. 13 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 12. FIG. 14 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 13. FIG. 15 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 14. FIG. 16 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 15. FIG. 17 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 16. It is explanatory drawing which shows typically the secondary electron image and reflected electron image which were obtained by the electron beam type | mold inspection method. It is explanatory drawing which shows typically the secondary electron image and reflected electron image which were obtained by the electron beam type | mold inspection method. It is explanatory drawing which shows the secondary electron image at the time of the high electron beam current with respect to a normal plug, an embedding defect plug, and a non-conducting plug, and the secondary electron image at the time of a low electron beam current, (a) is at the time of a high electron beam current. Normal plug and non-conducting plug, (b) is an explanatory diagram of a normal plug and a buried defective plug at a high electron beam current, and (c) is an explanatory diagram of a normal plug and a buried defective plug at a low electron beam current. It is explanatory drawing which shows the detection appropriateness of each defect with respect to each electron beam current test | inspection. It is explanatory drawing which shows the influence on the image acquisition time with respect to an electron beam current. It is explanatory drawing which shows typically the secondary electron image and reflected electron image which were obtained by the electron beam type | mold inspection method. FIG. 10 is a cross-sectional view schematically showing a semiconductor integrated circuit device during a manufacturing process in a third embodiment. FIG. 25 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 24. FIG. 26 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 25. FIG. 27 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 26. FIG. 28 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 27. FIG. 29 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 28. FIG. 30 is a cross-sectional view schematically showing the semiconductor integrated circuit device in the manufacturing process subsequent to FIG. 29. It is sectional drawing which shows typically the semiconductor integrated circuit device which has a local connection plug and a contact plug. It is sectional drawing which shows typically the plug formed on the multilayer wiring layer which the present inventors examined. It is a schematic diagram which shows an example of the foreign material which exists in the manufacturing process of the multilayer wiring layer of a semiconductor integrated circuit device. It is a block diagram which shows an electron microscope typically. It is a figure which shows the incident electron energy dependence of secondary electron emission efficiency. It is explanatory drawing which shows the defect plug detection by the system which the present inventors examined, (a) is a difference image, (b) is a reference image which shows the planar state of a plug, (c) is the planar state of a plug. (D) is an explanatory diagram of a detection threshold for a defective plug. It is explanatory drawing which shows an example of the reference image or test | inspection image obtained by the system which the present inventors examined, (a) is an embedding defect plug and a normal plug, (b) is a non-conduction plug and a normal plug, (c) () Is a non-opening plug and a normal plug, (d) is an explanatory view of foreign matter on the normal plug, and (e) is an explanatory view of foreign matter on the oxide film.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Backscattered electron detector 2 Backscattered electron detection signal conversion circuit 3 Backscattered electron 1st image drawing circuit 4 Backscattered electron 2nd image drawing circuit 5 Inspection area 5a Unit inspection area 5b Unit inspection area 6 Antireflection film 7 Photoresist film 8 Mask pattern DESCRIPTION OF SYMBOLS 9 Photomask 10 Foreign material 11 Non-opening part 12 Non-conductive hole 12 'Non-conductive plug 15 Seam 16 Exposure source 21 Liner layer 22 Etch stopper layer 23 Hard mask layer 24 Interlayer insulating film for Cu 25 Cu plating layer 26 Cu seed film / barrier Conductor film 101 Wiring layer 102 Cap layer 103 Barrier layer 104 Interlayer insulating film 105 Connection hole 106 Barrier conductor film 107 Conductive film 110 Electron beam 111 Electron gun 112 Condenser lens 113 Extraction electrode 114 Anode electrode 115 Blanking deflector 116 Aperture 117 Reflection Plate 118 E × B bias 119 Semiconductor wafer 120 to be inspected 120 Objective lens 121 Scanning deflector 122 X stage 123 Y stage 124 Sample stage 125 Sample height detector 126 Secondary electron detector 127 Light source 128 Optical lens 129 CCD camera 130 Condenser lens power supply 131 Scan signal generation Instrument 132 Objective lens power supply 133 Sample height measuring instrument 134 Position monitor length measuring instrument 135 Control circuit 136 Secondary electron detection signal conversion circuit 137 Image observation monitor 138 Secondary electron first image drawing circuit 139 Secondary electron second image drawing Circuit 140 Comparison operation circuit 141 Defect determination processing circuits C1 to C8 Conduction state analysis location P plug P1 normal plug P2 embedded defective plug (with barrier conductor film)
P3 Non-conductive plug P4 Non-opening plug P5 Semi-embedded defective plug P6 Implanted defective plug (no barrier conductor film)

Claims (4)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) a step of detecting secondary electrons and reflected electrons generated by irradiating an electron beam to an inspection region to be inspected on a main surface of a semiconductor wafer placed on a stage of an electron microscope;
(B) comparing the first secondary electron image formed by the secondary electrons and the second secondary electron image to form a first difference image;
(C) a step of comparing the first reflected electron image formed by the reflected electrons and the second reflected electron image to form a second difference image;
(D) comparing the first difference image and the second difference image to detect a defect in the inspection region;
(E) forming an insulating film on the wiring layer formed on the main surface of the semiconductor wafer;
(F) After the step (e), after forming a resist film on the insulating film, a step of exposing a pattern of connection holes to the resist film;
(G) After the step (f), after developing the resist film to form a resist pattern, etching the insulating film using the resist pattern as an etching mask;
(H) After the step (g), a step of embedding a conductive film in the connection hole;
(I) a step of discriminating the defect from an imbedding defect, non-conduction, or non-opening defect;
(J) When the defect of the embedding defect occurs in the step (h), the non-conductive defect occurs in the step (g), or the non-opening defect occurs in the step (f). The step of determining. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) The process of detecting the 1st secondary electron which generate | occur | produced by irradiating the 1st electron beam with respect to the test | inspection area | region which becomes the test object on the main surface of the semiconductor wafer placed on the stage of an electron microscope ;
(B) irradiating the inspection region to be inspected on the main surface of the semiconductor wafer placed on the stage of the electron microscope with a second electron beam lower than the current of the first electron beam Detecting the generated secondary secondary electrons;
(C) comparing the first secondary electron image formed by the first secondary electrons and the second secondary electron image to form a first difference image;
(D) comparing a third secondary electron image formed by the second secondary electrons with a fourth secondary electron image to form a second difference image;
(E) A step of comparing the first difference image and the second difference image to detect a defect or a foreign substance in the inspection region.   3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the current of the first electron beam is 60 nA or more and 100 nA or less, and the current of the second electron beam is 1 nA or more and less than 60 nA. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, further comprising the following steps:
(F) a step of detecting reflected electrons simultaneously with the detection of the first or second secondary electrons;
(G) comparing the first reflected electron image formed by the reflected electrons and the second reflected electron image to form a third difference image;
(H) A step of comparing the first difference image, the second difference image, and the third difference image to detect a defect or a foreign substance in the inspection region.

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