CN109103178B - 静电放电装置 - Google Patents

静电放电装置 Download PDF

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CN109103178B
CN109103178B CN201810598690.3A CN201810598690A CN109103178B CN 109103178 B CN109103178 B CN 109103178B CN 201810598690 A CN201810598690 A CN 201810598690A CN 109103178 B CN109103178 B CN 109103178B
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G·博塞利
M·Y·阿里
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Texas Instruments Inc
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Abstract

本申请公开了静电放电装置。根据至少一个实施例，ESD装置(100)包括：半导体(102)；焊盘(106)；接地轨(110)；在半导体中形成的p阱(112)；在p阱中形成并且电耦合到接地轨的第一p型区(116)；在p阱中形成并且电耦合到焊盘的第一n型区(118)；在p阱中形成并且电耦合到接地轨的第二n型区(122)；在半导体中形成的n阱(114)；在n阱中形成的第一n型区(108)；在n阱中形成并且电耦合到焊盘的第一p型区(128)；以及在n阱中形成并且电耦合到在n阱中形成的第一n型区的第二p型区(124)。

Description

静电放电装置
相关领域的交叉引用
本申请要求在2017年6月20日提交的、美国临时专利申请序号为62/522,176、标题为“具有嵌入式横向SCR的双二极管ESD单元实现分布式电源ESD网络”(“Dual-Diode ESDCell With Embedded Lateral SCR To Enable Distributed Power Supply ESDNetwork”)的申请的优先权，在此通过引用将其全部内容并入本文。
背景技术
由于经封装集成电路的一个或更多个引脚(或球或引线)上的电压尖峰或跳动引起的静电放电(ESD)能量可能损坏集成电路。ESD装置(或ESD单元)通过将受影响的引脚短接到接地轨和电源轨来帮助保护敏感集成电路免受ESD能量损害。期望ESD装置在耗散ESD能量方面是有效的，同时在集成电路中消耗相对小的硅面积。
发明内容
根据本发明的至少一个实施例，ESD装置包括：半导体；焊盘；接地轨；在半导体中形成的p阱；在p阱中形成并且电耦合到接地轨的第一p型区；在p阱中形成并且电耦合到焊盘的第一n型区；在p阱中形成并且电耦合到接地轨的第二n型区；在半导体中形成的n阱；在n阱中形成的第一n型区；在n阱中形成并且电耦合到焊盘的第一p型区；以及在n阱中形成并且电耦合到在n阱中形成的第一n型区的第二p型区。
根据本发明的至少一个实施例，在ESD中，接地轨处于接地电位。
根据本发明的至少一个实施例，ESD还包括集成电路封装；以及I/O封装引脚，其中焊盘电耦合到I/O封装引脚。
根据本发明的至少一个实施例，在ESD中，在p阱中形成的第一p型区被高掺杂以形成与p阱的欧姆接触，并且在n阱中形成的第一n型区被高掺杂以形成与n阱的欧姆接触。
根据本发明的至少一个实施例，ESD还包括电源轨，其电耦合到在n阱中形成的第一n型区和在n阱中形成的第二p型区。
根据本发明的至少一个实施例，ESD还包括：集成电路封装；以及I/O封装引脚，其中焊盘电耦合到I/O封装引脚。
根据本发明的至少一个实施例，ESD还包括电源轨，其电耦合到在n阱中形成的第一n型区和在n阱中形成的第二p型区。
根据本发明的至少一个实施例，ESD还包括在p阱中形成的第二p型区。
根据本发明的至少一个实施例，ESD还包括触发电路，触发电路电耦合到在n阱中形成的第一n型区和接地轨，并且包括输出端口，输出端口电耦合到在p阱中形成的第二p型区。
根据本发明的至少一个实施例，ESD还包括：电源轨，其电耦合到在n阱中形成的第一n型区；其中触发电路包括RC电路，RC电路包括电阻器和与电阻器串联的电容器，其中RC电路电耦合到在n阱中形成的第一n型区和接地轨。
根据本发明的至少一个实施例，在ESD中，触发电路还包括耦合到RC电路的触发缓冲器，触发缓冲器响应于焊盘上的电压尖峰而在触发电路的输出端口处拉(source)电流。
根据本发明的至少一个实施例，ESD还包括：在n阱中形成的第二n型区；以及电源轨，其电耦合到在n阱中形成的第一n型区和在n阱中形成的第二p型区。
根据本发明的至少一个实施例，ESD还包括：触发电路，其电耦合到电源轨和接地轨，并且包括第一输出端口和第二输出端口，第一输出端口电耦合到p阱中的第二p型区，第二输出端口电耦合到n阱中的第二n型区。
根据本发明的至少一个实施例，在ESD中，触发电路包括RC电路，RC电路包括电阻器和与电阻器串联的电容器，其中RC电路电耦合到电源轨和接地轨。
根据本发明的至少一个实施例，在ESD中，触发电路进一步包括耦合到RC电路的触发缓冲器，触发缓冲器响应于焊盘上的电压尖峰而在触发电路的第一输出端口处拉电流，以及响应于焊盘上的电压尖峰而在触发电路的第二输出端口处灌(sink)电流。
根据本发明的至少一个实施例，ESD还包括：第一隔离区，其在形成于p阱中的第一p型区与形成于p阱中的第一n型区之间；第二隔离区，其在形成于p阱中的第一n型区与形成于p阱中的第二p型区之间；第三隔离区，其在形成于p阱中的第二p型区与形成于p阱中的第二n型区之间；第四隔离区，其在形成于p阱中的第二n型区与形成于n阱中的第二p型区之间；第五隔离区，其在形成于n阱中的第二p型区与形成于n阱中的第二n型区之间；第六隔离区，其在形成于n阱中的第二n型区与形成于n阱中的第一p型区之间；以及第七隔离区，其在形成于n阱中的第一p型区与形成于n阱中的第一n型区之间。
根据本发明的至少一个实施例，一种方法包括：在半导体上形成接地轨；在半导体上形成焊盘；在半导体中形成p阱；在p阱中形成第一p型区；将在p阱中形成的第一p型区耦合到接地轨；在p阱中形成第一n型区；将在p阱中形成的第一n型区耦合到焊盘；在p阱中形成第二n型区；将在p阱中形成的第二n型区耦合到接地轨；在半导体中形成n阱；在n阱中形成第一n型区；在n阱中形成第一p型区；将在n阱中形成的第一p型区耦合到焊盘；在n阱中形成第二p型区；以及将在n阱中形成的第二p型区耦合到在n阱中形成的第一n型区。
根据本发明的至少一个实施例，该方法进一步包括：在半导体上形成电源轨；将电源轨耦合到形成在n阱中的第一n型区和形成在n阱中的第二p型区；在p阱中形成第二p型区；以及在n阱中形成第二n型区。
根据本发明的至少一个实施例，一种ESD包括：半导体；接地轨；电源轨；焊盘；在半导体中形成的第一二极管，其将焊盘耦合到电源轨；在半导体中形成的第二二极管，其将焊盘耦合到接地轨；在半导体中形成的可控硅整流器，其将电源轨耦合到接地轨；以及触发电路，其将电源轨和接地轨耦合到可控硅整流器。
附图说明
将参考附图做出对于各种示例的详细描述，在附图中：
图1示出了根据各种示例的ESD装置；
图2示出了根据各种示例的ESD装置的电路表示；
图3示出了根据各种示例的ESD装置的电路表示；
图4示出了根据各种示例的用于保护多个焊盘的ESD装置的电路表示；以及
图5示出了根据各种示例的用于制造ESD装置的方法。
具体实施方式
许多集成电路使用一个或更多个ESD装置，其中ESD装置包括将I/O(输入—输出)焊盘耦合到电源轨或接地的双二极管布置，以及用于当在I/O焊盘上检测到电压尖峰或跳动时将电源轨短接到接地的有源场效应晶体管。在一些应用中，发现与硅的固有限制相比，这种ESD装置可能无法有效地耗散ESD能量，并且可能在集成电路上消耗太多的硅面积。
根据所公开的实施例，一种系统包括ESD装置以保护集成电路的I/O焊盘免受电压尖峰或跳动的影响。ESD装置包括一个或更多个触发电路以触发一个或更多个可控硅整流器以将电源轨短接到接地轨。预期这些实施例在耗散ESD能量方面是有效的同时消耗相对小的集成电路面积。
图1示出了说明性的ESD装置100。图1将说明性的ESD装置100的一部分说明为未按比例绘制的简化横截面，而说明性的ESD装置100的其他部分用电路符号说明。
半导体102具有p型衬底104，但是一些实施例可以具有n型衬底。图1示出了I/O焊盘106，处于电压Vdd的电源轨108以及处于接地或衬底电压Vss处的接地轨110。接地轨110可以被称为接地。在半导体102的p型衬底104中形成p阱112和n阱114。
在p阱112和n阱114中形成若干p型区和n型区。这些区在若干处理步骤中形成，其中光刻胶层(未示出)被图案化并刻蚀以暴露p阱112和n阱114的选定区域，其中掺杂剂被注入选定区域以形成若干p型区和n型区。形成在p阱112中的是：p型区116、n型区118、p型区120、和n型区122。形成在n阱114中的是：p型区124、n型区126、p型区128、和n型区130。p型区116和120被高掺杂以与p阱112形成体接触且与金属化(未示出)互连形成欧姆接触。n型区118和122也是高掺杂区，以与p阱112形成PN结，并且与金属化互连形成欧姆接触。n型区126和130被高掺杂以与n阱114形成体接触，并且与金属化互连形成欧姆接触。p型区124和128也是高掺杂的区，以与n阱114形成PN结，并与金属化互连形成欧姆接触。在一些实施例中，作为示例，尽管一些实施例的掺杂剂浓度分布(profile)的范围可以包括与本示例不同的值，但是高掺杂区可以具有范围从1015cm-3到1020cm-3的掺杂剂浓度分布。
在形成p型区和n型区之前形成若干浅沟槽隔离(STI)区，使得STI区位于成对的p型区与n型区之间以提供电隔离。STI区132位于p型区116与n型区118之间以隔离这两个区，STI区134位于n型区118与p型区120之间以隔离这两个区，STI区136位于p型区120与n型区122之间以隔离这两个区，STI区138位于n型区122与p型区124之间以隔离这两个区，STI区140位于p型区124与n型区126之间以隔离这两个区，STI区142位于n型区126与p型区128之间以隔离这两个区，以及STI区144位于p型区128与n型区130之间以隔离这两个区。
n型区118和p型区128电耦合到I/O焊盘106。图1示出了与包括互连146的简化电路连接的这种电耦合。为了提供n型区118和p型区128与I/O焊盘106的电耦合，在n型区118和p型区128中形成电接触，并且在后段制程(BEOL)过程中在的半导体102的有源区域之上的一层或更多层中形成各种互连，但是为了便于说明，电路符号被用于指示电耦合。p型区116和n型区122电耦合到接地轨110。P型区124和n型区130电耦合到电源轨108。简单电路符号被用于说明这些电耦合。
包括电阻器150和电容器152的电阻器—电容器(RC)电路148被耦合到电源轨108和接地轨110。如图1所说明的具体的实施例，电阻器150具有直接连接到电源轨108的端子，并且电容器152具有直接连接到接地轨110的端子。电阻器150和电容器152的相对位置可以互换，其中在一些实施例中电阻器150具有直接连接到接地轨110的端子，并且电容器152具有直接连接到电源轨108的端子。
RC电路148的节点154处的电压被提供给触发缓冲器158的输入端口156。RC电路148和触发缓冲器158的组合可以被称为触发电路164.。触发电路164(或触发缓冲器158)具有输出端口160和输出端口162。输出端口160电耦合至n型区126，其中至n型区126的输入端口160具有与输出端口160相同的标签来指示该电连接。输出端口162电耦合至p型区120，其中至p型区120的输入端口162具有与输出端口162相同的标签来指示该电连接。
在一些实施例中，触发电路164可以具有输出160，而不具有输出端口162，使得p型区120不直接耦合到触发电路164的输出端口。在一些实施例中，触发电路164可以具有输出162，但不具有输出端口160，使得n型区126不直接耦合到触发电路164的输出端口。触发电路164的操作在稍后更详细地论述。
图1提供了包括半导体102的说明性的ESD装置100的部分的简化横截面图。电路组件用于说明说明性的ESD装置100中的该部分，说明性的ESD装置100包括I/O焊盘106、电源轨108、接地轨110、输入端口160和162、以及触发电路164。在一些实施例中，图1中说明的电路组件在半导体102中制造，或者在与半导体102集成的层中制造。
图2说明可以在图1的说明性的ESD装置100中识别的说明性的寄生电路组件。参考图2，包括p型区128和n阱114的PN结形成二极管202。P型区128用作二极管202的阳极，并且n阱114用作二极管202的阴极。包括n型区118和p阱112的PN结形成二极管204。n型区118用作二极管204的阴极，并且p阱112用作二极管204的阳极。电阻器206表示从二极管202的阴极到n型区130的分布电阻Rn1。电阻器208表示从二极管204的阳极到p型区116的分布电阻Rs2。
包括p型区124和n阱114的PN结与包括p型衬底104和n阱114的PN结的组合形成PNP晶体管210。p型区124用作晶体管210的发射极，n阱114用作晶体管210的基极，并且p型衬底104用作晶体管210的集电极。包括p阱112和n阱114的PN结与包括p阱112和n型区122的PN结的组合形成NPN晶体管212。n型区122用作晶体管212的发射极，p阱112用作晶体管212的基极，并且n阱114用作晶体管212的集电极。
晶体管210的基极电耦合到晶体管212的集电极和n型区126。晶体管210的集电极电耦合到晶体管212的基极和p形区120，电阻器214表示从晶体管210的基极到二极管202的阴极的分布电阻Rn2。电阻器216表示从晶体管212的基极到二极管204的阳极的分布电阻Rs1。
图3示出了表示图2中说明的寄生电路组件和图1中说明的电路组件的说明性电路。电阻器302表示电源轨108中的分布电阻RVdd，以及电阻器304表示接地轨110中的分布电阻RVss。之前参照图1和图2已经论述过图3中说明的其它电路组件。
参考图3，晶体管210和晶体管212的配置可以被认为是可控硅整流器(SCR)。将足够量的电流拉入到晶体管212的基极中(即，到输入端口162中)，闩锁导通(latch ON)SCR。从晶体管210的基极(即，从输入端口160)灌足够量的电流，闩锁导通SCR。当被闩锁导通时，SCR提供从电源轨108到接地轨110的低阻抗路径。
对于一些实施例，触发电路164可以利用输出端口160和输出端口162两者，而在一些实施例中，触发电路164可以仅采用这些输出端口中的一个。首先考虑触发电路164利用输出端口162而不利用输出端口160的情况。在这种情况下，触发电路164不直接影响晶体管210的基极。
如果相对于接地轨110的接地(或衬底电压)Vss，I/O焊盘106上的正向电压尖峰(或跳动)足够地大于电源轨108上的电压Vdd，将正向偏置二极管202。随着二极管202正向导通，在节点154产生的电压开始减小。如果该电压下降到第一阈值以下，则触发缓冲器158在输出端口162处拉足够的电流以开启晶体管212，从而闩锁导通SCR。在电源轨108与接地轨110之间提供低阻抗路径以使I/O焊盘106上的正向电压尖峰放电。
选择RC电路148的电阻和电容的值并选择第一阈值的值，确定包括晶体管210和212的SCR被触发导通(ON)的环境条件(情况)。可以选择这些参数以减少不需要的错误触发，但是要调整这些参数以充分保护半导体102上的电路免受I/O焊盘106上的有害电压尖峰的影响。
考虑触发电路164利用输出端口160而不利用输出端口162的情况。在这种情况下，触发电路164不直接影响晶体管212的基极。如果I/O焊盘106上的正向电压尖峰(或跳动)充分地大于电源轨108上的电压Vdd，将正向偏置二极管202。在二极管202正向导通的情况下，在节点154处产生的电压开始减小。如果该电压下降到第二阈值以下，则触发缓冲器158在输出端口160处灌足够的电流以接通晶体管210，从而闩锁导通SCR。在电源轨108与接地轨110之间提供低阻抗路径以使I/O焊盘106上的正向电压尖峰放电。
选择用于RC电路148的电阻和电容的值，以及选择用于第二阈值的值来确定包括晶体管210和212的SCR被触发导通(ON)的环境条件(情况)。
对于一些实施例，触发缓冲器158(或触发电路164)可以利用输出端口160和输出端口162两者，在这种情况下，触发缓冲器158的行为可以是前述触发缓冲器158仅利用输出端口160和162中的一者的情况中的行为的组合。例如，对于I/O焊盘106上的正向电压尖峰，可以配置触发缓冲器158，使得如果在节点154处的电压下降到第三阈值以下，触发缓冲器158在输出端口160处灌足够的电流以接通晶体管210并且在输出端口162处拉足够的电流以接通晶体管212，从而闩锁导通SCR。
不管触发缓冲器158使用输出端口160、输出端口162、还是其两者，二极管204通过变为正向导通来提供针对负向电压尖峰(或跳动)的保护。如果相对于接地(或衬底电压)Vss 110，I/O焊盘106上的负向电压尖峰(或跳动)充分地低于接地轨110的接地或衬底电压Vss，将正向偏置二极管204。
在一些应用中，例如其中I/O焊盘106与电源轨108之间的低阻抗路径不可用的故障保护应用，示例性的ESD装置100适用于使I/O焊盘106上的正向电压尖峰放电。例如，参考图3，如果到电源轨108的耦合不存在，则针对在I/O焊盘106上的、足够大以至正向偏置二极管202的正向电压尖峰，触发缓冲器158可以经配置以使得当在节点154处的电压下降到第四阈值以下时，触发缓冲器158闩锁导通SCR，使得提供从I/O焊盘106到接地轨110的低阻抗路径。
第一、第二、第三、和第四阈值可以各自具有不同的数值，但是对于一些实施例，这些阈值中的一些或全部可以具有相同的数值。
图4示出了用于保护多个I/O焊盘的一个实施例。一个实施例包括图1中说明的的示例性的ESD装置100的多个示例，其中每个受保护的I/O焊盘都具有ESD装置。一个实施例包括多个触发电路，其中每个受保护的I/O焊盘都具有触发电路。触发电路的输出端口被硬连线到网络中以触发多个SCR。
图4明确示出了两个I/O焊盘，I/O焊盘402和I/O焊盘404以及两个SCR和两个触发电路。晶体管406和408被配置成SCR，其可以与I/O焊盘402相关联。晶体管410和412被配置到另一个SCR中，其可以与I/O焊盘404相关联。因为SCR各自耦合到电源轨108和接地轨110，当SCR被触发时，无论是单独地还是组合，都有助于使在I/O焊盘的任何组合上的电压尖峰放电。
触发电路414的输出端口418被硬连线到触发电路416的相应的输出(也标记为418)。输出端口418被硬连线到晶体管406的基极和晶体管410的基极。触发电路414的输出端口420被硬连线到触发电路416的相应的输出(也标记为420)。输出端口420被硬连线到晶体管408的基极和晶体管412的基极。图4中的触发电路具有与关于图3的触发电路164所描述的相同的结构和操作，即，触发缓冲器158与包括电阻器150和电容器152的RC电路的组合。
图5示出了在半导体中制造ESD装置100的说明性的过程。在图5中说明的列表即不意味着过程步骤的任何特定顺序，也不意味所有步骤都被需要。此外，为了简洁起见，省略了许多步骤，例如生长或沉积氧化物层、光刻胶层、刻蚀，注入掺杂剂等。
在步骤502中形成电源轨，并且在步骤504中形成接地轨。在步骤506中，形成焊盘。在步骤508中，形成p阱。在步骤510中，在p阱中形成第一p型区。在步骤512中，在p阱中形成的第一p型区耦合到接地轨。在步骤514中，在p阱中形成第一n型区。在步骤516中，在p阱中形成的第一n型区耦合到焊盘。在步骤518中，在p阱中形成第二n型区。在步骤520中，在p阱中形成的第二n型区耦合到接地轨。在步骤522中，形成n阱。在步骤524中，在n阱中形成第一n型区。在步骤526中，在n阱中形成第一p型区。在步骤528中，在n阱中形成的第一p型区耦合到焊盘。在步骤530中，在n阱中形成第二p型区。在步骤532中，在n阱中形成的第二p型区耦合到在n阱中形成的第一n型区。在步骤534中，电源轨耦合到在n阱中的第一n型区和在n阱中的第二p型区。在步骤536中，在p阱中形成第二p型区。在步骤538中，在n阱中形成第二n型区。
以上论述意在说明本公开的原理和各种实施例。只要完全理解了上述公开内容，对于本领域技术人员来说许多变化和修改将变得显而易见。意图是将以下权利要求解释为包含所有这些变化和修改。

Claims (16)

1.一种静电放电装置，其包括：
半导体衬底；
焊盘；
接地轨和电源轨；
p阱，其在所述半导体衬底中；
第一p型区，其在所述p阱中并且电耦合到所述接地轨；
第一n型区，其在所述p阱中并且电耦合到所述焊盘；
第二n型区，其在所述p阱中并且电耦合到所述接地轨；
n阱，其在所述半导体衬底中；
第一n型区，其在所述n阱中并且电耦合到所述电源轨；
在所述n阱中的第二n型区，所述第二n型区耦合到触发电路的输出端口，所述触发电路耦合到所述接地轨和所述电源轨；
第一p型区，其在所述n阱中并且电耦合到所述焊盘；以及
第二p型区，其在所述n阱中并且电耦合到在所述电源轨。
2.根据权利要求1所述的静电放电装置，其中所述触发电路包括：
RC电路，所述RC电路包括电阻器和电容器，所述电阻器和所述电容器与所述电阻器和所述电容器之间的节点串联，所述RC电路耦合到所述接地轨和所述电源轨；以及
耦合到所述RC电路的触发缓冲器，所述触发缓冲器被配置为当响应于所述焊盘处的电压尖峰，在所述节点处的电压低于阈值时在所述输出端口处灌电流。
3.根据权利要求1所述的静电放电装置，其中所述接地轨处于接地电位。
4.根据权利要求1所述的静电放电装置，还包括：
集成电路封装；以及
I/O封装引脚，其中所述焊盘电耦合到所述I/O封装引脚。
5.根据权利要求1所述的静电放电装置，其中在所述p阱中的所述第一p型区被高掺杂，以与所述p阱形成欧姆接触，并且在所述n阱中的所述第一n型区被高掺杂，以与所述n阱形成欧姆接触。
6.根据权利要求1所述的静电放电装置，其中所述输出端口是所述触发电路的第一输出端口，所述静电放电装置还包括：
在所述p阱中形成的第二p型区，所述第二p型区耦合到所述触发电路的第二输出端口。
7.根据权利要求6所述的静电放电装置，其中所述触发电路包括：
RC电路，所述RC电路包括电阻器和电容器，所述电阻器和所述电容器与所述电阻器和所述电容器之间的节点串联，所述RC电路耦合到所述接地轨和所述电源轨；以及
耦合到所述RC电路的触发缓冲器，所述触发缓冲器被配置为当响应于所述焊盘处的电压尖峰，在所述节点处的电压低于阈值时在所述第二输出端口处拉电流。
8.根据权利要求1所述的静电放电装置，还包括：
第一隔离区，其在所述p阱中的所述第一p型区与所述p阱中的所述第一n型区之间；
第二隔离区，其在所述p阱中的所述第一n型区与所述p阱中的所述第二p型区之间；
第三隔离区，其在所述p阱中的所述第二p型区与所述p阱中的所述第二n型区之间；
第四隔离区，其在所述p阱中的所述第二n型区与所述n阱中的所述第二p型区之间；
第五隔离区，其在所述n阱中的所述第二p型区与所述n阱中的所述第二n型区之间；
第六隔离区，其在所述n阱中的第二n型区与所述n阱中的所述第一p型区之间；以及
第七隔离区，其在所述n阱中的所述第一p型区与所述n阱中的所述第一n型区之间。
9.一种静电放电装置，包括：
半导体衬底；
焊盘；
接地轨和电源轨；
在所述半导体衬底中的p阱；
在所述p阱中并且电耦合到所述接地轨的第一p型区；
在所述p阱中的第二p型区，所述第二p型区耦合到触发电路的第二输出端口；
在所述p阱中并且电耦合到所述焊盘的第一n型区；
在所述p阱中并且电耦合到所述接地轨的第二n型区；
在所述半导体衬底中的n阱；
在所述n阱中并且电耦合到所述电源轨的第一n型区；
在所述n阱中的第二n型区，所述第二n型区耦合到所述触发电路的第一输出端口；
在所述n阱中并且电耦合到所述焊盘的第一p型区；以及
在所述n阱中并且电耦合到所述电源轨的第二p型区。
10.根据权利要求9所述的静电放电装置，其中所述触发电路包括：
RC电路，所述RC电路包括电阻器和电容器，所述电阻器和所述电容器与所述电阻器和所述电容器之间的节点串联，所述RC电路耦合到所述接地轨和所述电源轨；以及
耦合到所述RC电路的触发缓冲器，所述触发缓冲器被配置为当响应于所述焊盘处的电压尖峰，在所述节点处的电压低于阈值时在所述第二输出端口处拉电流。
11.根据权利要求9所述的静电放电装置，还包括：
集成电路封装；以及
I/O封装引脚，其中所述焊盘电耦合到所述I/O封装引脚。
12.根据权利要求9所述的静电放电装置，其中所述触发电路包括：
RC电路，所述RC电路包括电阻器和电容器，所述电阻器和所述电容器与所述电阻器和所述电容器之间的节点串联，所述RC电路耦合到所述接地轨和所述电源轨；以及
耦合到所述RC电路的触发缓冲器，所述触发缓冲器被配置为当响应于所述焊盘处的电压尖峰，在所述节点处的电压低于阈值时在所述第一输出端口处灌电流。
13.根据权利要求9所述的静电放电装置，其中所述触发电路包括：
RC电路，所述RC电路包括电阻器和电容器，所述电阻器和所述电容器与所述电阻器和所述电容器之间的节点串联，所述RC电路耦合到所述接地轨和所述电源轨；以及
耦合到所述RC电路的触发缓冲器，所述触发缓冲器被配置为当响应于所述焊盘处的电压尖峰，在所述节点处的电压低于阈值时在所述第一输出端口处灌电流以及在所述第二输出端口处拉电流。
14.一种静电放电装置，包括：
半导体衬底；
焊盘
接地轨和电源轨；
在所述半导体衬底中的n阱；
在所述n阱中并且电耦合到所述电源轨的第一n型区；
在所述n阱中的第二n型区，所述第二n型区耦合到触发电路的第一输出端口，所述触发电路耦合到所述接地轨和所述电源轨；
第一p型区，其在所述n阱中并且电耦合到所述焊盘；
第二p型区，其在所述n阱中并且电耦合到在所述电源轨；
在所述半导体衬底中的p阱；
在所述p阱中并且电耦合到所述接地轨的第一p型区；
在所述p阱中的第二p型区，所述第二p型区耦合到所述触发电路的第二输出端口；
在所述p阱中并且电耦合到所述焊盘的第一n型区；
在所述p阱中并且电耦合到所述接地轨的第二n型区。
15.根据权利要求14所述的静电放电装置，还包括：
集成电路封装；以及
I/O封装引脚，其中所述焊盘电耦合到所述I/O封装引脚。
16.根据权利要求14所述的静电放电装置，其中所述触发电路包括：
RC电路，所述RC电路包括电阻器和电容器，所述电阻器和所述电容器与所述电阻器和所述电容器之间的节点串联，所述RC电路耦合到所述接地轨和所述电源轨；以及
耦合到所述RC电路的触发缓冲器，所述触发缓冲器被配置为当响应于所述焊盘处的电压尖峰，在所述节点处的电压低于阈值时在所述第一输出端口处灌电流以及在所述第二输出端口处拉电流。
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