CN109075137B - 芯片封装结构、芯片模组及电子终端 - Google Patents

芯片封装结构、芯片模组及电子终端 Download PDF

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CN109075137B
CN109075137B CN201780012913.7A CN201780012913A CN109075137B CN 109075137 B CN109075137 B CN 109075137B CN 201780012913 A CN201780012913 A CN 201780012913A CN 109075137 B CN109075137 B CN 109075137B
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chip
substrate
electrical connection
packaging structure
plastic
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CN109075137A (zh
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张胜斌
刘凯
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Abstract

一种芯片封装结构、芯片模组、电子终端，其中的芯片封装结构通过将芯片(2)放置基板(1)的开槽中以缩减芯片封装结构的厚度及封装体积；同时通过在放置了芯片后基板的表面增加塑封体(3)对芯片进行塑封，既能够保证芯片封装结构的结构强度，还能够尽可能地降低芯片封装结构因厚度缩减后可能造成的翘曲，此外通过将塑封体的表面处理成平面，使得芯片模组具有良好的平整度，增加芯片模组的适配性。

Description

芯片封装结构、芯片模组及电子终端
技术领域
本申请属于芯片封装技术领域，尤其涉及一种芯片封装结构、芯片模组及电子终端。
背景技术
随着移动终端越来越朝着小型化、超薄化的方向发展，应用到移动终端中的功能模块同样地朝着体积越小、厚度越薄的方向发展。举例来说，绝大多数的移动终端配置了芯片封装结构，借助芯片封装结构对用户的身份进行验证以开启移动终端。
但是，体积越小、厚度越薄的芯片封装结构容易出现翘曲，因此如何减少芯片封装结构的翘曲度成为亟待解决的技术问题。
发明内容
本申请实施例的目的在于提供一种芯片封装结构、芯片模组及电子终端，用于解决现有技术中上述技术问题。
本申请实施例第一方面一种芯片封装结构，包括：基板和塑封体；
其中，所述基板上设置有开槽，所述开槽用于放置芯片；
所述塑封体用于覆盖放置了芯片后的所述基板的上表面，所述塑封体的上表面为一平面；和/或，所述塑封体用于覆盖放置了芯片后的所述基板的下表面，所述塑封体的下表面为一平面。
可选地，所述芯片的上表面与所述基板的上表面处于同一水平面；
和/或，所述芯片的下表面与所述基板的下表面处于同一水平面；
可选地，所述基板还设置有与外围电路连接的第一电连接结构，所述第一电连接结构用于与所述芯片上设置的第二电连接结构电连接。
可选地，所述第一电连接结构与设置于所述芯片上的沟槽底部的第二电连接结构电连接。
可选地，所述第一电连接结构与所述第二电连接结构通过引线键合的方式连接。
可选地，所述第一电连接结构与设置于所述芯片上的硅通孔结构电连接。
可选地，所述第一电连接结构为球栅阵列。
可选地，所述塑封体为注入的EMC经交联固化反应形成的塑封体。
可选地，所述基板通过粘合层与放置的所述芯片粘合。
可选地，所述粘合层为注入的环氧树脂经交联固化反应形成的粘合层。
本申请实施例第二方面一种芯片模组，包括：芯片和本申请第一方面提供的任一所述的芯片封装结构；其中，所述芯片放置于所述芯片封装结构中的基板上的开槽中。
本申请实施例第三方面一种电子终端，包括本申请第二方面提供的任一所述的芯片模组。
本申请实施例提供的芯片封装结构、芯片模组、电子终端，其中的芯片封装结构通过将芯片放置基板的开槽中以缩减芯片封装结构的厚度及封装体积；同时通过在放置了芯片后基板的表面增加塑封体对芯片进行塑封，既能够保证芯片封装结构的结构强度，还能够尽可能地降低芯片封装结构因厚度缩减后可能造成的翘曲，此外通过将塑封体的表面处理成平面，使得芯片模组具有良好的平整度，增加芯片模组的适配性。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例示例性一的芯片封装结构的结构示意图；
图2是本申请实施例示例性二的芯片封装结构的结构示意图；
图3是本申请实施例示例性三的芯片封装结构的结构示意图；
图4是本申请实施例示例性四的芯片封装结构的结构示意图；
图5是本申请实施例示例性五的芯片封装结构的结构示意图；
图6是本申请实施例示例性六的芯片封装结构的结构示意图；
图7是本申请实施例示例性七的芯片封装结构的结构示意图；
图8是本申请实施例示例性八的芯片封装结构的结构示意图。
附图标记说明：
1：基板； 2：芯片；
21：沟槽； 3：塑封体；
4：引线； 5：球栅阵列；
具体实施方式
为使得本申请的目的、特征、优点能够更加的明显和易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而非全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参见图1至图8，本实施例提供的芯片封装结构，包括：基板1和塑封体3；其中，所述基板1上设置有开槽，所述开槽用于放置芯片2；所述塑封体3用于覆盖放置了芯片2后的所述基板1的上表面，所述塑封体3的上表面为一平面；和/或，所述塑封体3用于覆盖放置了芯片2后的所述基板1的下表面，所述塑封体3的下表面为一平面。
本实施例提供的芯片封装结构通过将芯片2放置基板1的开槽中以缩减芯片封装结构的厚度及封装体积；同时通过在放置了芯片2后基板1的表面增加塑封体3对芯片2进行塑封，既能够保证芯片封装结构的结构强度，还能够尽可能地降低芯片封装结构因厚度缩减后可能造成的翘曲，进此外通过将塑封体3的表面处理成平面，使得芯片模组具有良好的平整度，增加芯片模组的适配性。
具体地，芯片封装结构能够对芯片2起到固定、保护等作用。芯片2的固定一方面依赖基板1的固定，另一方面依赖塑封体3的固定。为了保证芯片封装结构的结构强度，要求基板1除了具有良好的加工性能外，还要求基板1具有良好的硬度。可选地，基板1的材质可以是亚克力、铁、铜、玻璃纤维，采用上述材质的基板1具有良好的硬度。
具体地，本实施例通过将芯片2放置在基板1的开槽中，以减小芯片封装结构的厚度及体积。需要说明的是，开槽的位置及开槽的结构形式具体不限，根据芯片2的具体结构形式而定。优选的，开槽的位置位于基板1的中心区域，且开槽为贯穿基板1的通槽，这样能够最大限度地将芯片2放置到基板1中，尽可能地减小了芯片封装结构的厚度及体积。但不限于此，在实际应用中，可以根据实际需要，将该开槽设置为部分贯通，部分不贯通，或者，设置为非贯通结构，本申请实施例对此不作限制。可选地，放置芯片2后，所述芯片2的上表面与所述基板1的上表面处于同一水平面；和/或，所述芯片2的下表面与所述基板1的下表面处于同一水平面。举例来说，芯片2的厚度可能大于、等于、小于基板1的厚度。在将芯片2组装到基板1的开槽中时，尽可能地使芯片2的某一表面与基板1的某一表面处于同一水平面，这样在将芯片2与基板1组装时，通过确定两者的某一表面处于同一水平面即可确定芯片2与基板1的组装符合设计要求，在一定程度上实现芯片2与基板1的快速组装，也能够方便后续的加工制造。进一步举例来说，本实施例中的基板的厚度在满足设定的结构强度的要求上，可以选择厚度在0.08毫米至0.5毫米范围内的基板，当将芯片放置到基板中后，可以控制芯片模组的厚度在0.24毫米左右，芯片模组的翘曲度控制在5至80微米范围内，当芯片模组运用到生物特征识别模组上时，还能控制生物特征识别模组的厚度0.45毫米左右，实现芯片模组同时满足薄形化和低翘曲度的要求。
需要说明的是，基板1与芯片2之间的连接形式具体不限。可选地，基板1通过粘合层与放置的所述芯片2粘合。举例来说，组装时，先将基板1与芯片2固定到工装上，并依据设计图纸调整基板1、芯片2的位置；调整完成后，基板1的开槽与芯片2存在一定的缝隙，对缝隙进行点胶水，当胶水固化后即形成所述粘合层,胶水可以是Under Fill胶、UV胶、环氧胶、热固化胶；或者，往缝隙中注入EMC(Epoxy Molding Compound,环氧树脂模塑料)，EMC经交联固化反应形成粘合层。本实施例通过使基板1与放置的所述芯片2粘合，实现芯片2更好地被固定，此外，由于芯片2的四周被粘合，在一定程度上也使得芯片封装结构的结构强度更好。
可见，通过在芯片封装结构上设置的塑封体3，能够保护芯片2、基板1，以及使得放置了芯片2后的芯片封装结构的结构强度更好。举例来说，在经芯片2组装到基板1的开槽中后，在基板1的上表面上注入EMC，EMC经交联固化反应后形成覆盖在基板1的上表面的塑封体3。当然，也可以在基板1的下表面上注入EMC，EMC经交联固化反应后形成覆盖在基板1的下表面的塑封体3。此外，也可以在基板1的上表面和下表面上都注入EMC，EMC经交联固化反应后形成覆盖在基板1的上表面和下表面的塑封体3。需要说明的是，塑封体不限于举例说明的为注入的EMC经交联固化反应形成的塑封体，还可以为任意适当的具有塑封功能的材质。进一步地，为了增加芯片封装结构的平整度，设置塑封体3时，尽量使塑封体3的表面形成一平面。具体地，所述塑封体3用于覆盖放置了芯片2后的所述基板1的上表面，所述塑封体3的上表面为一平面；和/或，所述塑封体3用于覆盖放置了芯片2后的所述基板1的下表面，所述塑封体3的下表面为一平面。
可选地，所述基板1还设置有与外围电路连接的第一电连接结构，所述第一电连接结构用于与所述芯片2上设置的第二电连接结构电连接。
举例来说，设置在基板1上的第一电连接结构可以是与外围电路连接的引脚阵列，可以是设置在基板1上的球栅阵列5，但并不以此为限。以球栅阵列5为例，相比引脚的形式，球栅阵列5(Ball Grid Array，BGA)有利于保证整个芯片模组的机械可靠性。举例来说，球栅阵列5为基板1的下方设置的焊盘。
具体地，本实施例中的芯片可以是普通工艺处理的芯片，也可以采用挖槽(Trench)工艺处理的芯片，也可以是采用硅通孔(TSV，Through Silicon Vias)工艺处理的芯片，具体不限。
举例来说，当芯片2为普通工艺处理的芯片2，第二电连接结构可以设置在芯片2的上表面和/或下表面，第二电连接结构可以为芯片焊盘(Die Pad)，这时第一电连接结构与第二电连接结构可以通过引线键合的方式连接，引线键合的具体实现方式可参见常规的实现方式，在此不再赘述。引线键合(Wire Bonding)是一种使用细金属线实现芯片与基板间的电气互连。可选地，采用金属线可以是金线、铝线、铜线中的任一种，但并不限于此。
举例来说，当采用挖槽(Trench)工艺处理的芯片2时，在芯片2上形成有沟槽21，第二电连接结构设置在沟槽21中，第二电连接结构可以为芯片焊盘(Die Pad)，这时第一电连接结构与第二电连接结构可以通过引线4键合的方式连接，引线4键合的具体实现方式可参见常规的实现方式，在此不再赘述。本实施例通过对芯片进行挖槽处理，能够进一步缩减芯片封装结构的厚度，挖槽处理后，即使采用引线键合的方式也不会增加芯片封装结构的厚度。
需要说明的是，沟槽21可以形成在芯片2的上部，也可以形成在芯片2的下部，沟槽21的条数可以是一条，也可以是多条。进一步地，当沟槽21形成在芯片2的上部时，设计沟槽21的底面距离芯片2的上表面为设定距离；当沟槽21形成在芯片2的下部时，设计沟槽21的底面距离芯片2的下表面为设定距离。设置设定距离是为了最大限度地缩减芯片封装结构的厚度，同时还能保证用来进行引线键合中的引线所受的应力不至于使引线的结构受损，进而影响芯片模组的电气性能。其中，设定距离可以由本领域技术人员根据实际情况适当设置，本申请实施例对此不作限制。
举例来说，当采用TSV工艺处理的芯片2时，硅通孔结构贯穿芯片2，硅通孔结构中填充了铜、钨、多晶硅等导电物质，该硅通孔结构为与基板1上的第一电连接结构电连接的第二电连接结构。采用TSV工艺处理的芯片2能够进一步地缩减芯片2封装结构的厚度以及芯片2模组的厚度。
需要说明的是，第一电连接结构与第二电连接结构可以直接电连接，也可以间接电连接。直接电连接是指第一电连接结构与第二电连接结构直接接触而电连接，间接电连接是指第一电连接结构与第二电连接结构通过中间导电结构而电连接。举例来说，当第一电连接结构为设置在基板1下的球栅阵列5，第二电连接结构可以为芯片焊盘(Die Pad)，这时第一电连接结构与第二电连接结构在空间上相距较远，无法实现电连接，这时可以在基板1上设置重布线层(RDL)实现第一电连接结构与第二电连接结构。同样地，当第一电连接结构为设置在基板1下的球栅阵列5，第二电连接结构为硅通孔结构时，这时第一电连接结构与第二电连接结构在空间上相距较远，无法实现电连接，这时可以在基板1上设置重布线层(RDL)实现第一电连接结构与第二电连接结构。设置重布线层(RDL)的具体实现方式可参见常规的实现方式，在此不再赘述。
下面对图1至图8所示的芯片封装结构分别进行详细说明。
图1和图2所示的芯片封装结构的主要特点是具有贯穿基板1的开槽、开槽用于放置芯片2，采用引线4键合的方式连接芯片2与基板1。其中，基板1上的第一电连接结构可以是引脚阵列、也可以是球栅阵列5(Ball Grid Array，BGA)，但并不以此为限；放置在基板1的开槽中的芯片2可以是普通工艺处理的芯片2，该芯片2的表面可以设置有芯片2焊盘(DiePad)，芯片2焊盘(Die Pad)为芯片2上的第二电连接结构；第一电连接结构与第二电连接结构可通过重布线层(RDL)连接。
具体地，图1所示的芯片封装结构中，具有贯穿基板1的开槽，开槽用于放置芯片2，塑封体3设置在基板1的上表面，采用引线键合的方式连接芯片2与基板1。其中，基板1上的第一电连接结构可以是引脚阵列(图中未示出)、芯片2可以是普通工艺处理的芯片2，芯片2的第二电连接结构为芯片2焊盘(Die Pad)(图中未示出)，通过引线键合的方式实现芯片2与基板1的电连接，根据实际情形的需要，还借助重布线层(RDL)实现芯片焊盘(Die Pad)与引脚阵列的电连接。当然，基板1上的第一电连接结构不限于引脚阵列，芯片2的第二电连接结构不限于芯片2焊盘。在组装该芯片封装结构时，先将基板1与芯片2固定到工装上，并依据设计图纸调整基板1、芯片2的位置；调整完成后，基板1的开槽与芯片2存在一定的缝隙，对缝隙进行点胶水，当胶水固化后即形成所述粘合层，胶水可以是Under Fill胶、UV胶、环氧胶、热固化胶；或者往缝隙中注入EMC(Epoxy Molding Compound,环氧树脂模塑料)，EMC经交联固化反应形成粘合层；接着连接金属线等引线4，引线4的一端与芯片2相连，引线4的另一端与基板1相连；最后，在基板1的上表面上注入EMC，EMC经交联固化反应后形成覆盖在基板1的上表面的塑封体3。需要说明的是，由于图1所示的塑封体3在基板1的上表面，组装该芯片2封装结构时，尽可能地使芯片2的下表面与基板1的下表面处于同一水平面，以提高整个芯片2模组的平整度，此外还能方便后续的工序安装。本实施例提供的芯片封装结构，通过将芯片2放置基板1的开槽中以缩减芯片封装结构的厚度及封装体积；同时通过在放置了芯片2后基板1的上表面增加塑封体3对芯片2进行塑封，既能够保证芯片封装结构的结构强度，还能够尽可能地降低芯片封装结构因厚度缩减后可能造成的翘曲，此外通过将塑封体3的表面处理成平面，使得芯片模组具有良好的平整度，增加芯片模组的适配性。
具体地，图2所示的芯片封装结构中，具有贯穿基板1的开槽，开槽用于放置芯片2，塑封体3设置在基板1的上表面和下表面，采用引线键合的方式连接芯片2与基板1。其中，基板1上的第一电连接结构可以是球栅阵列5(Ball Grid Array，BGA)、芯片2可以是普通工艺处理的芯片2，芯片2的第二电连接结构为芯片2焊盘(Die Pad)(图中未示出)，通过引线4键合的方式实现芯片2与基板1的电连接，根据实际情形的需要，还借助重布线层(RDL)实现芯片2焊盘(Die Pad)与引脚阵列的电连接。当然，基板1上的第一电连接结构不限于球栅阵列5(Ball Grid Array，BGA)，芯片2的第二电连接结构不限于芯片2焊盘。在组装该芯片封装结构时，先将基板1与芯片2固定到工装上，并依据设计图纸调整基板1、芯片2的位置；调整完成后，基板1的开槽与芯片2存在一定的缝隙，对缝隙进行点胶，当胶水固化后即形成所述粘合层，胶水可以是Under Fill胶、UV胶、环氧胶、热固化胶；或者，往缝隙中注入EMC(EpoxyMolding Compound,环氧树脂模塑料)，EMC经交联固化反应形成粘合层；接着连接金属线等引线4，引线4的一端与芯片2相连，引线4的另一端与基板1相连；最后，在基板1的上表面和下表面上注入EMC，EMC经交联固化反应后形成覆盖在基板1的上表面和下表面的塑封体3。在图1所示的芯片封装结构的基础上，图2所示的芯片封装结构通过覆盖在基板1的上表面和下表面的塑封体3，实现对芯片2和基板1的更好的防护，进而还能使得利用该芯片封装结构进行封装的芯片模组具有良好的耐污性能、耐划伤性能等；图2所示的芯片封装结构中的基板1上的第一电连接结构为球栅阵列5(Ball Grid Array，BGA)，有利于保证整个芯片模组的机械可靠性。
图3至图5所示的芯片封装结构的主要特点是具有贯穿基板1的开槽、开槽用于放置芯片2、采用引线4键合的方式连接芯片2与基板1。其中，基板1上的第一电连接结构可以是引脚阵列、也可以是球栅阵列5(Ball Grid Array，BGA)，但并不以此为限；放置在基板1的开槽中的芯片2是挖槽(Trench)工艺处理的芯片2，该芯片2经挖槽(Trench)工艺处理形成后形成一沟槽21可以设置有芯片2焊盘(Die Pad)，芯片2焊盘(Die Pad)为芯片2上的第二电连接结构；第一电连接结构与第二电连接结构可通过重布线层(RDL)连接。图3至图5所示的芯片封装结构通过对芯片2上设置沟槽21，并将芯片2的第一电连接结构设置在沟槽21中，相比图1至图2所示的芯片2封装结构，能够进一步地减薄芯片2封装结构的厚度及体积。
具体地，图3所示的芯片封装结构中，具有贯穿基板1的开槽、开槽用于放置芯片2、塑封体3设置在基板1的上表面，采用引线4键合的方式连接芯片2与基板1。其中，基板1上的第一电连接结构可以是引脚阵列(图中未示出)，芯片2为经挖槽(Trench)工艺处理的芯片2，芯片2的第二电连接结构为芯片2焊盘(Die Pad)(图中未示出)且设置在芯片2的沟槽21中；通过引线4键合的方式实现芯片2与基板1的电连接，根据实际情形的需要，还借助重布线层(RDL)实现芯片2焊盘(Die Pad)与引脚阵列的电连接。当然，基板1上的第一电连接结构不限于引脚阵列，芯片2的第二电连接结构不限于芯片2焊盘。在组装该芯片封装结构时，先将基板1与芯片2固定到工装上，并依据设计图纸调整基板1、芯片2的位置；调整完成后，基板1的开槽与芯片2存在一定的缝隙，对缝隙进行点胶水，当胶水固化后即形成所述粘合层，胶水可以是Under Fill胶、UV胶、环氧胶、热固化胶；或者，往缝隙中注入EMC(EpoxyMolding Compound,环氧树脂模塑料)，EMC经交联固化反应形成粘合层；接着连接金属线等引线4，引线4的一端与芯片2相连，引线4的另一端与基板1相连；最后，在基板1的上表面上注入EMC，EMC经交联固化反应后形成覆盖在基板1的上表面的塑封体3。需要说明的是，由于图3所示的塑封体3在基板1的上表面，组装该芯片封装结构时，尽可能地使芯片2的下表面与基板1的下表面处于同一水平面，以提高整个芯片模组的平整度，此外还能方便后续的工序安装。本实施例提供的芯片封装结构，通过对芯片2进行挖槽(Trench)工艺处理以将芯片2的第二电连接结构放置在沟槽21中以及将芯片2放置基板1的开槽中来缩减芯片封装结构的厚度及封装体积；同时通过在放置了芯片2后基板1的上表面增加塑封体3对芯片2进行塑封，既能够保证芯片封装结构的结构强度，还能够尽可能地降低芯片2封装结构因厚度缩减后可能造成的翘曲，此外通过将塑封体3的表面处理成平面，使得芯片模组具有良好的平整度，增加芯片模组的适配性。
具体地，图4所示的芯片封装结构中，具有贯穿基板1的开槽、开槽用于放置芯片2、塑封体3设置在基板1的下表面，采用引线键合的方式连接芯片2与基板1。其中，基板1上的第一电连接结构是球栅阵列5(Ball Grid Array，BGA)，芯片2为经挖槽(Trench)工艺处理的芯片2，芯片2的第二电连接结构为芯片焊盘(Die Pad)(图中未示出)且设置在芯片2的沟槽21中；通过引线4键合的方式实现芯片2与基板1的电连接，根据实际情形的需要，借助重布线层(RDL)实现芯片2焊盘(Die Pad)与球栅阵列5(Ball Grid Array，BGA)的电连接。当然，基板1上的第一电连接结构不限于球栅阵列5(Ball Grid Array，BGA)，芯片2的第二电连接结构不限于芯片2焊盘。在组装该芯片封装结构时，先将基板1与芯片2固定到工装上，并依据设计图纸调整基板1、芯片2的位置；调整完成后，基板1的开槽与芯片2存在一定的缝隙，对缝隙进行点胶水，当胶水固化后即形成粘合层，胶水可以是Under Fill胶、UV胶、环氧胶、热固化胶；或者，往缝隙中注入EMC(Epoxy Molding Compound,环氧树脂模塑料)，EMC经交联固化反应形成粘合层；接着连接金属线等引线4，引线4的一端与芯片2相连，引线4的另一端与基板1相连；最后，在基板1的下表面上注入EMC，EMC经交联固化反应后形成覆盖在基板1的下表面的塑封体3。需要说明的是，根据实际情况的需要，在基板1的上表面覆盖一层的厚度较小的塑封体3来填充沟槽21。本实施例提供的芯片封装结构，通过对芯片2进行挖槽(Trench)工艺处理以将芯片2的第二电连接结构放置在沟槽21中以及将芯片2放置基板1的开槽中来缩减芯片封装结构的厚度及封装体积；同时通过在放置了芯片2后基板1的下表面增加塑封体3对芯片2进行塑封，既能够保证芯片2封装结构的结构强度，还能够尽可能地降低芯片2封装结构因厚度缩减后可能造成的翘曲，此外通过将塑封体3的表面处理成平面，使得芯片模组具有良好的平整度，增加芯片模组的适配性。此外，图4所示的芯片封装结构中的基板1上的第一电连接结构为球栅阵列5(Ball Grid Array，BGA)，球栅阵列5有利于保证整个芯片模组的机械可靠性。
具体地，图5所示的芯片封装结构中，具有贯穿基板1的开槽、开槽用于放置芯片2、塑封体3设置在基板1的上表面和下表面上，采用引线键合的方式连接芯片2与基板1。其中，基板1上的第一电连接结构是球栅阵列5(Ball Grid Array，BGA)，芯片2为经挖槽(Trench)工艺处理的芯片2，芯片2的第二电连接结构为芯片2焊盘(Die Pad)(图中未示出)且设置在芯片2的沟槽21中；通过引线键合的方式实现芯片2与基板1的电连接，根据实际情形的需要，还借助重布线层(RDL)实现芯片2焊盘(Die Pad)与球栅阵列5(Ball Grid Array，BGA)的电连接。当然，基板1上的第一电连接结构不限于球栅阵列5(Ball Grid Array，BGA)，芯片2的第二电连接结构不限于芯片2焊盘。
在组装该芯片封装结构时，先将基板1与芯片2固定到工装上，并依据设计图纸调整基板1、芯片2的位置；调整完成后，基板1的开槽与芯片2存在一定的缝隙，对缝隙进行点胶水，当胶水固化后即形成所述粘合层，胶水可以是Under Fill胶、UV胶、环氧胶、热固化胶；或者，往缝隙中注入EMC(Epoxy Molding Compound,环氧树脂模塑料)，EMC经交联固化反应形成粘合层；接着连接金属线等引线4，引线4的一端与芯片2相连，引线4的另一端与基板1相连；最后，在基板1的上表面和下表面上注入EMC，EMC经交联固化反应后形成覆盖在基板1的上表面和下表面的塑封体3。在图3和4所示的芯片封装结构的基础上，图5所示的芯片封装结构通过覆盖在基板1的上表面和下表面的塑封体3，实现对芯片2和基板1的更好的防护，进而还能使得利用该芯片封装结构进行封装的芯片模组具有良好的耐污性能、耐划伤性能等；图5所示的芯片封装结构中的基板1上的第一电连接结构为球栅阵列5(Ball GridArray，BGA)，有利于保证整个芯片模组的机械可靠性。
图6至图8所示的芯片封装结构的主要特点是具有贯穿基板1的开槽、开槽用于放置芯片2。其中，基板1上的第一电连接结构可以是引脚阵列、也可以是球栅阵列5(BallGrid Array，BGA)，但并不以此为限；芯片2为采用TSV工艺处理的芯片2，硅通孔结构(图中未示出)贯穿芯片2，硅通孔结构为芯片2的第二电连接结构。第一电连接结构与第二电连接结构可通过重布线层(RDL)连接。图6至图8所示的芯片封装结构通过采用TSV工艺处理的芯片2，无需在芯片2上设置芯片焊盘(Die Pad)以及安装用于引线键合的引线4等，节约了安装空间，进一步地缩减芯片封装结构的厚度以及芯片2模组的厚度。
具体地，图6所示的芯片封装结构中，具有贯穿基板1的开槽、开槽用于放置芯片2、塑封体3设置在基板1的上表面。其中，基板1上的第一电连接结构是引脚阵列(图中未使出)，芯片2为采用TSV工艺处理的芯片2，硅通孔结构(图中未示出)贯穿芯片2，硅通孔结构为芯片2的第二电连接结构。根据实际情形的需要，借助重布线层(RDL)实现硅通孔结构与引脚阵列的电连接。当然，基板1上的第一电连接结构不限于引脚阵列。在组装该芯片封装结构时，先将基板1与芯片2固定到工装上，并依据设计图纸调整基板1、芯片2的位置；调整完成后，基板1的开槽与芯片2存在一定的缝隙，对缝隙进行点胶水，当胶水固化后即形成所述粘合层，胶水可以是Under Fill胶、UV胶、环氧胶、热固化胶、热固化胶；或者，往缝隙中注入EMC(Epoxy Molding Compound,环氧树脂模塑料)；之后，在基板1的上表面上注入EMC，EMC经交联固化反应后形成覆盖在基板1的上表面的塑封体3。需要说明的是，由于图6所示的塑封体3在基板1的上表面，组装该芯片封装结构时，尽可能地使芯片2的下表面与基板1的下表面处于同一水平面，以提高整个芯片模组的平整度，此外还能方便后续的工序安装。本实施例提供的芯片封装结构，通过采用TSV工艺处理的芯片2以及将芯片2放置基板1的开槽中来缩减芯片封装结构的厚度及封装体积；同时通过在放置了芯片2后基板1的上表面增加塑封体3对芯片2进行塑封，既能够保证芯片封装结构的结构强度，还能够尽可能地降低芯片封装结构因厚度缩减后可能造成的翘曲，此外通过将塑封体3的表面处理成平面，使得芯片模组具有良好的平整度，增加芯片模组的适配性。
具体地，图7所示的芯片封装结构中，具有贯穿基板1的开槽、开槽用于放置芯片2、塑封体3设置在基板1的下表面。其中，基板1上的第一电连接结构是球栅阵列5(Ball GridArray，BGA)、芯片2为采用TSV工艺处理的芯片2，硅通孔结构(图中未示出)贯穿芯片2，硅通孔结构为芯片2的第二电连接结构。根据实际情形的需要，借助重布线层(RDL)实现硅通孔结构与引脚阵列的电连接。当然，基板1上的第一电连接结构不限于球栅阵列5(Ball GridArray，BGA)。需要说明的是，可以根据实际需求在采用TSV工艺处理的芯片2的下方增设一锡球焊盘，该焊盘上设置有多个锡球，通过锡球焊盘上的锡球与硅通孔结构电连接，再借助重布线层(RDL)实现连接该锡球焊盘与基板上的球栅阵列5电连接。
在组装该芯片封装结构时，先将基板1与芯片2固定到工装上，并依据设计图纸调整基板1、芯片2的位置；调整完成后，基板1的开槽与芯片2存在一定的缝隙，对缝隙进行点胶水，当胶水固化后即形成所述粘合层，胶水可以是Under Fill胶、UV胶、环氧胶、热固化胶、热固化胶；或者，往缝隙中注入EMC(Epoxy Molding Compound,环氧树脂模塑料)；之后，在基板1的下表面上注入EMC，EMC经交联固化反应后形成覆盖在基板1的下表面的塑封体3。需要说明的是，由于图7所示的塑封体3在基板1的下表面，组装该芯片封装结构时，尽可能地使芯片2的上表面与基板1的上表面处于同一水平面，以提高整个芯片模组的平整度，此外还能方便后续的工序安装。本实施例提供的芯片封装结构，通过采用TSV工艺处理的芯片2以及将芯片2放置基板1的开槽中来缩减芯片封装结构的厚度及封装体积；同时通过在放置了芯片2后基板1的下表面增加塑封体3对芯片2进行塑封，既能够保证芯片封装结构的结构强度，还能够尽可能地降低芯片封装结构因厚度缩减后可能造成的翘曲，此外通过将塑封体3的表面处理成平面，使得芯片模组具有良好的平整度，增加芯片模组的适配性。此外，图7所示的芯片封装结构中的基板1上的第一电连接结构为球栅阵列5(Ball Grid Array，BGA)，有利于保证整个芯片模组的机械可靠性。
具体地，图8所示的芯片封装结构中，具有贯穿基板1的开槽、开槽用于放置芯片2、塑封体3设置在基板1的上表面和下表面。其中，基板1上的第一电连接结构是球栅阵列5(Ball Grid Array，BGA)、芯片2为采用TSV工艺处理的芯片2，硅通孔结构(图中未示出)贯穿芯片2，硅通孔结构为芯片2的第二电连接结构。根据实际情形的需要，借助重布线层(RDL)实现硅通孔结构与引脚阵列的电连接。当然，基板1上的第一电连接结构不限于球栅阵列5(Ball Grid Array，BGA)。在组装该芯片封装结构时，先将基板1与芯片2固定到工装上，并依据设计图纸调整基板1、芯片2的位置；调整完成后，基板1的开槽与芯片2存在一定的缝隙，对缝隙进行点胶水，当胶水固化后即形成所述粘合层，胶水可以是Under Fill胶、UV胶、环氧胶、热固化胶、热固化胶；或者，往缝隙中注入EMC(Epoxy Molding Compound,环氧树脂模塑料)；之后，在基板1的上表面和下表面上注入EMC，EMC经交联固化反应后形成覆盖在基板1的上表面和下表面的塑封体3。在图7所示的芯片封装结构的基础上，图8所示的芯片封装结构通过覆盖在基板1的上表面和下表面的塑封体3，实现对芯片2和基板1的更好的防护，进而还能使得利用该芯片封装结构进行封装的芯片模组具有良好的耐污性能、耐划伤性能等。
需要说明的是,设置在基板1下方的焊盘如球栅阵列5的数目根据芯片的实际情况设定,说明书附图中的焊盘的数目只是示例,不做具体限定。
本申请实施例还提供一种芯片模组，包括本申请实施例任一实施例所述的芯片封装结构，其中，所述芯片放置于所述芯片封装结构中的基板上的开槽中。需要说明的是，芯片封装结构的结构、功能以及能够实现的技术效果与前述实施例类似，在此不再累述。
本申请实施例提供的芯片模组，其中的芯片封装结构通过将芯片放置基板的开槽中以缩减芯片封装结构的厚度及封装体积；同时通过在放置了芯片后基板的表面增加塑封体对芯片进行塑封，既能够保证芯片封装结构的结构强度，还能够尽可能地降低芯片封装结构因厚度缩减后可能造成的翘曲，此外通过将塑封体的表面处理成平面，使得芯片模组具有良好的平整度，增加芯片模组的适配性。
本申请实施例还提供一种电子终端，包括本申请任一实施例所述的芯片模组。需要说明的是，芯片模组的结构、功能以及能够实现的技术效果与前述实施例类似，在此不再累述。
本申请实施例提供的电子终端，电子终端中的芯片模组包括芯片封装结构，其中的芯片封装结构通过将芯片放置基板的开槽中以缩减芯片封装结构的厚度及封装体积；同时通过在放置了芯片后基板的表面增加塑封体对芯片进行塑封，既能够保证芯片封装结构的结构强度，还能够尽可能地降低芯片封装结构因厚度缩减后可能造成的翘曲，此外通过将塑封体的表面处理成平面，使得芯片模组具有良好的平整度，增加芯片模组的适配性。
尽管已描述了本申请实施例的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请实施例范围的所有变更和修改。显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请实施例权利要求及其等同技术的范围之内，则本申请实施例也意图包含这些改动和变型在内。

Claims (10)

1.一种芯片封装结构，其特征在于，包括：基板和塑封体；
其中，所述基板上设置有开槽，所述开槽用于放置芯片；
所述塑封体用于覆盖放置了芯片后的所述基板的下表面，所述塑封体的下表面为一平面,
其中，所述基板进一步设置有球栅阵列，所述球栅阵列与所述芯片封装结构所在的芯片模组外的外围电路连接，所述球栅阵列与贯穿所述芯片的硅通孔结构电连接，并且所述球栅阵列与所述芯片接触，所述球栅阵列的下表面与所述塑封体的下表面处于同一水平面。
2.根据权利要求1所述的芯片封装结构，其特征在于，所述芯片的下表面与所述基板的下表面处于同一水平面。
3.根据权利要求1所述的芯片封装结构，其特征在于，所述球栅阵列与设置于所述芯片上的沟槽底部的硅通孔结构电连接。
4.根据权利要求1所述的芯片封装结构，其特征在于，所述球栅阵列与所述硅通孔结构通过引线键合的方式连接。
5.根据权利要求1所述的芯片封装结构，其特征在于，所述塑封体为注入的环氧树脂经交联固化反应形成的塑封体。
6.根据权利要求1所述的芯片封装结构，其特征在于，所述基板通过粘合层与放置的所述芯片粘合。
7.根据权利要求6所述的芯片封装结构，其特征在于，所述粘合层为注入的EMC经交联固化反应形成的粘合层。
8.根据权利要求1-7任一所述的芯片封装结构，其特征在于，所述基板的厚度在0.08毫米至5毫米之间。
9.一种芯片模组，其特征在于，包括：芯片和如权利要求1至8任一所述的芯片封装结构；
其中，所述芯片放置于所述芯片封装结构中的基板上的开槽中。
10.一种电子终端，其特征在于，包括权利要求9所述的芯片模组。
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