CN109065522A - Trim resistance and preparation method thereof - Google Patents
Trim resistance and preparation method thereof Download PDFInfo
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- CN109065522A CN109065522A CN201810863087.3A CN201810863087A CN109065522A CN 109065522 A CN109065522 A CN 109065522A CN 201810863087 A CN201810863087 A CN 201810863087A CN 109065522 A CN109065522 A CN 109065522A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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Abstract
The present invention provides one kind and trims resistance, it includes substrate, form oxide layer on substrate, the polysilicon layer that is formed in oxide layer and the dielectric layer for being formed in oxide layer upper surface, it is formed in the wire of dielectric layer upper surface, window is trimmed positioned at two upper side of wire on wire length direction, wire includes the first metal layer, second metal layer and third metal layer, trimming resistance further includes the upper surface fuse window corresponding with polysilicon layer positioned at second metal layer, it is formed in the passivation layer for trimming window two sides and is formed on dielectric layer groove corresponding with fuse window, passivation layer formation is in the upper surface of third metal layer and the dielectric layer, the view field of the fuse window is included in the view field of polysilicon layer on the direction perpendicular to substrate.The present invention also provides a kind of preparation method for trimming resistance, the influence for preventing wire fusing from splashing or flowing back to substrate, enhancing trims the reliability of resistance and trims efficiency, reduces manufacturing cost.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields more particularly to one kind to trim resistance and preparation method thereof.
Background technique
It trims resistance and is generally divided into three kinds of fuse-class, Zener diode class and film resistor laser trimming class classifications.Wherein
Fuse-class trims resistance since the technology of blowing is relatively easy to technological level and measuring accuracy requirement, is conducive to production control, technology
Also relative maturity and be widely adopted.Fuse-class trims resistance and is broadly divided into metal and two kinds of polycrystalline according to material.
Currently, what the test for trimming resistance generally used is all instantaneous large-current, according to the physical characteristic of conductor, work as electric current
Density very high (104A/cm2 or more) when will cause the gradually displacement of metallic atom, so that metal cavity and accumulation is occurred, it is this existing
As referred to as electromigration, the appearance of electromigration exacerbates the increase of current density, theoretical according to the thermal conductivity of conductor, the mistake of electric current flowing
Electronic impact metal ion can generate heat in journey, and the size of heat and current density is directly proportional, and the current density the big more collects
In, the heat of generation is bigger, and when heat reaches the fusing point of metal, metal fusing occurs and evaporates, circuit breaker after metal fusing,
To have the function that trim.Due to trimming resistance when trimming, wire, which is instanteously blown appearance and splashes or trickle to circuit, is led
Cause short circuit occur and the problem of trim unsuccessfully, so influence trim resistance trim efficiency and measuring accuracy.
Summary of the invention
In view of this, the present invention provide that a kind of raising trims efficiency and measuring accuracy trim resistance, to solve above-mentioned skill
Art problem, on the one hand, the present invention provides following technical scheme to realize.
One kind trimming resistance comprising substrate forms oxide layer over the substrate, is formed in the oxide layer
Polysilicon layer and it is formed in the dielectric layer of the oxide layer upper surface, the wire for being formed in the dielectric layer upper surface, in institute
State and trim window positioned at two upper side of wire on wire length direction, the wire include the first metal layer,
The second metal layer that is connected with the first metal layer upper surface and the interval for being formed in second metal layer upper surface setting
Third metal layer, it is described trim resistance further include positioned at the second metal layer upper surface it is corresponding with the polysilicon layer
Fuse window is formed in and described trim the passivation layer of window two sides and be formed on the dielectric layer corresponding with the fuse window
Groove, the passivation layer formation is institute in the upper surface of the third metal layer and the dielectric layer, the bottom of the groove
Polysilicon layer is stated, the view field of the fuse window is included in the polysilicon layer on the direction perpendicular to the substrate
In view field.
The present invention, which provides, a kind of to be trimmed having the beneficial effect that for resistance and forms polysilicon layer over the substrate for the metal
Silk is isolated with the oxide layer, the substrate is protected when resistance trims in described trim, the institute on perpendicular to the substrate direction
The projection for stating fuse window is included in the projection of the polysilicon layer, so that the fuse is directly vacantly in the polysilicon layer
Upper surface, so that the thermally conductive pathways of the wire Yu the substrate have been blocked, so that the wire is easier to be burnt completely
It is disconnected.The fusing point of the polysilicon layer is higher than the wire simultaneously, can prevent the wire from trickling in molten state
Or it splashes.When trimming window and the fuse window of resistance is trimmed described in the production, the oxide layer can prevent etching from damaging
Hurt the substrate, improve it is described trim resistance trim efficiency and measuring accuracy.
On the other hand, the present invention also provides a kind of manufacturing methods for trimming resistance comprising following processing step:
S401: a substrate is provided, forms oxide layer over the substrate；
S402: the deposit polycrystalline silicon layer in the oxide layer；
S403: dielectric layer is formed in the upper surface of the oxide layer and the polysilicon layer；
S404: for being formed simultaneously the first metal layer on the dielectric layer, being connected with the first metal layer upper surface
Two metal layers and with the third metal layer that is formed in the second metal layer upper surface；
S405: etching removal is located at a part at the wire both ends, and corresponding position is made to expose the dielectric layer,
The upper surface of the third metal layer and the dielectric layer forms passivation layer；
S406: the passivation layer for being located at two upper side of wire on the wire length direction is lithographically formed
Window is trimmed, while the third metal layer is removed in the corresponding position of window that trims；
S407: removing the corresponding part third metal layer in the polysilicon layer position and corresponds to second gold medal in this position
The top for belonging to layer forms fuse window, and the view field of the fuse window is included in described on perpendicular to the substrate direction
In the view field of polysilicon layer；
S408: isotropic etch is carried out to the fuse window, is formed in the dielectric layer and the fuse window pair
The bottom of the groove answered, the groove is the polysilicon layer, eventually forms and trims resistance.
The present invention forms oxide layer, in the oxygen by providing a kind of preparation method for trimming resistance over the substrate
Change deposit polycrystalline silicon layer on layer, forms dielectric layer in the oxide layer upper surface, the first gold medal is formed simultaneously on the dielectric layer
Belong to layer, the second metal layer being connected with the first metal layer upper surface and is formed in the second metal layer upper surface with interval
Third metal layer, passivation layer is formed on the wire, and carry out on the wire length direction be located at the metal
The passivation layer of two upper sides of silk, which is lithographically formed, trims window, and it is corresponding with the polysilicon layer to be formed in the wire upper surface
Fuse window, the view field of the fuse window is included in the projection of the polysilicon layer on perpendicular to the substrate direction
In region, isotropic etch is carried out to the fuse window, is formed on the dielectric layer corresponding with the fuse window
Groove.Wherein, window first is trimmed positioned at two upper side of wire on the wire length direction, then described more
The top of the corresponding second metal layer of crystal silicon layer forms fuse window, and the size of the fuse window trims window less than described,
Convenient for forming the wire met the requirements.The polysilicon layer is isolated by the wire with the oxide layer, prevents etching pair
The influence of the substrate.Simultaneously by increasing the method for a step isotropic etching passivation layer, by the wire lower surface
Dielectric layer removal, so that the wire is vacantly above the polysilicon layer, to block the wire and the lining
The thermally conductive pathways at bottom, so that the wire is easier to be blown completely.It effectively avoids burning timing generation in the resistance that trims
Heat the substrate is impacted, even if with the presence of the metal of solvent, can also prevent it is described trim resistance burn adjust after short circuit.
The resistance that trims can solve the disconnected problem of the wire infusibility, and the wire is avoided to burn the splashing during adjusting or return
Existing short circuit problem is flowed out, preparation process is simple, reduces preparation cost.
Detailed description of the invention
Fig. 1 is the structure top view that the present invention trims resistance；
Fig. 2 is the cross-sectional view along A-A ' that the present invention trims resistance in Fig. 1；
Fig. 3 is the cross-sectional view along B-B ' that the present invention trims resistance in Fig. 1；
Fig. 4 to Figure 12 is the preparation process figure that the present invention trims resistance；
Figure 13 is the cross-sectional view along B-B ' that the present invention trims resistance in Fig. 9；
Figure 14 is the cross-sectional view along B-B ' that the present invention trims resistance in Figure 10；
Figure 15 is the cross-sectional view along B-B ' that the present invention trims resistance in Figure 11；
Figure 16 is the cross-sectional view along B-B ' that the present invention trims resistance in Figure 12；
Figure 17 is the preparation method flow chart that the present invention trims resistance.
In figure: trimming resistance 1；Substrate 10；Oxide layer 20；Polysilicon layer 30；Dielectric layer 40；Wire 50；First metal
Layer 51；Second metal layer 52；Third metal layer 53；Passivation layer 60；Trim window 61；Fuse window 62；Groove 65；First photoetching
Glue-line 70；Second photoresist layer 80.
Specific embodiment
In order to be more clearly understood that the specific technical solution of the present invention, feature and advantage, with reference to the accompanying drawing and have
The present invention is further described in detail for body embodiment.
In the description of the present invention, it should be noted that term " on ", "lower", "left", "right", " transverse direction ", " longitudinal direction ",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention.But the present invention can be with
Much it is different from other way described herein to implement, those skilled in the art can be without prejudice to intension of the present invention the case where
Under do similar popularization, therefore the present invention is not limited to the specific embodiments disclosed below.
Refering to fig. 1, Fig. 2 and Fig. 3, the present invention provide one kind trim resistance 1 include substrate 10, be formed on the substrate 10
Oxide layer 20, the polysilicon layer 30 that is formed in the oxide layer 20 and the dielectric layer for being formed in 20 upper surface of oxide layer
40, it is formed in the wire 50 of 40 upper surface of dielectric layer, is located at the wire on 50 length direction of wire
50 liang of upper sides trim window 61, the wire 50 include the first metal layer 51, with 51 upper surface of the first metal layer
Connected second metal layer 52 and the spaced third metal layer 53 for being formed in 52 upper surface of second metal layer, it is described
Trim resistance 1 further include positioned at the second metal layer 52 upper surface fuse window 62 corresponding with the polysilicon layer 30,
It trims the passivation layer 60 of 61 two sides of window described in being formed in and is formed in corresponding with the fuse window 62 on the dielectric layer 40
Groove 65, the passivation layer 60 is formed in the upper surface of the third metal layer 53 and the dielectric layer 40, the groove 65
Bottom be the polysilicon layer 30, the view field of the fuse window 62 includes on the direction perpendicular to the substrate 10
In the view field of the polysilicon layer 30.
The present invention, which provides, a kind of to be trimmed having the beneficial effect that for resistance 1 and forms polysilicon layer 30 on the substrate 10 for institute
It states wire 50 to be isolated with the oxide layer 20, the substrate 10 is protected when resistance 1 trims in described trim, perpendicular to described
The projection of the fuse window 62 is included in the projection of the polysilicon layer 30 on 10 direction of substrate, to block the gold
Belong to the thermally conductive pathways of silk 50 and the substrate 10, so that the wire 50 is easier to be blown completely.The polysilicon simultaneously
The fusing point of layer 30 is higher than the wire 50, can prevent the wire 50 from occurring trickling or splash in molten state.It is making
When trimming window 61 and the fuse window 62 of resistance 1 is trimmed described in work, the oxide layer 20 can prevent etching injury institute
State substrate 10, improve it is described trim resistance 1 trim efficiency and measuring accuracy.
Referring again to Fig. 2 and Fig. 3, the wire 50 is strip, and the polysilicon layer 30 is bulk, perpendicular to institute
The view field for stating the fuse window 62 on 10 direction of substrate is included in the view field of the polysilicon layer 30, subsequent
Described when trimming resistance 1 and trimming, the polysilicon layer 30 plays the role of the protection substrate 10, and avoids the occurrence of short circuit.
Further, the projection of the polysilicon layer 30 is included in the oxide layer on perpendicular to 10 direction of substrate
In 20 projection.
The polysilicon layer 30 is formed in the oxide layer 20, the oxide layer 20 have by the substrate 10 with it is described
Wire 50 is isolated, it is described trim resistance 1 and trim when, the first metal layer 51 and the second gold medal positioned at 65 upper surface of groove
Belong to layer 52 to fuse, the first metal layer 51 splashes to 30 upper surface of polysilicon layer after being preferentially fused into liquid, to keep away
Exempt from that the substrate 10 of 30 lower surface of polysilicon layer is caused to damage, preventing the wire 50, fusing short circuit does not occur now completely
As trimming trimming for resistance 1 described in raising and efficiency and trimming measuring accuracy convenient for being subsequently formed the fuse window 62.
Further, the material of the first metal layer 51 is different from the material of the second metal layer 52, with described
The material of three metal layers 53 is identical.
The wire 50 includes three-layer metal layer, the material phase of the first metal layer 51 and the third metal layer 53
Together, and the resistivity of the first metal layer 51 and the third metal layer 53 is greater than the second metal layer 52, is preparing
Cheng Zhong, the first metal layer 51 and the third metal layer 53 have the work for preventing 52 surface of second metal layer to be oxidized
With convenient for forming the wire 50.During trimming, 52 layers of second metal preferential fusing easily reach described and trim
Resistance trims test, reduces preparation cost.
Refering to Fig. 4 to Figure 12 and Figure 17, the present invention also provides a kind of preparation methods for trimming resistance 1 comprising following system
Standby technique:
S401: providing a substrate 10, and oxide layer 20 is formed on the substrate 10；
Specifically, providing a substrate 10 refering to Fig. 4, oxide layer 20 is formed on the substrate 10.Wherein, the lining
Bottom 10 can be silicon substrate, germanium silicon substrate, III-group Ⅴ element compound substrate 10 or well known to a person skilled in the art other half
Conductor material substrate 10, the material in present embodiment using silicon as the substrate 10.More specifically, present embodiment
It could be formed with MOS field-effect material or silicon compound etc. in the substrate 10 of middle use, bipolar circuitry provided
The substrate 10 is usually the substrate 10 of P (111) crystal orientation.There are many technologies of 10 surface of substrate formation oxide layer 20:
Thermal oxide growth, thermal decomposition deposition, epitaxial growth are evaporated in vacuo, reactive sputtering and anodizing etc..Wherein thermally grown oxide
It is more universal in integrated circuit technology, it is easy to operate, and oxide layer is fine and close, can be used as diffusion mask layer, passes through photoetching
Localization or diffusion pattern etc. are easily formed, preferred thermally grown oxide is formed in the oxide layer on the substrate 10 in present embodiment
20。
Layer of oxide layer is grown on the substrate 10 can be used as the masking layer of preparation etching, and in preparation process
In, it also ensures that 10 surface of substrate is not influenced by surrounding atmosphere, the work of the substrate 10 is protected in subsequent preparation process
With trimming the driveability of resistance 1 described in raising.
S402: the deposit polycrystalline silicon layer 30 in the oxide layer 20；
Specifically, first depositing one layer of polysilicon layer 30 in the oxide layer 20, then to the polysilicon layer refering to Fig. 5
20 etchings, retain the polysilicon layer 30 of 20 middle section of oxide layer.In the present embodiment, the polysilicon layer 30
For one piece of undoped insulated polysilicon layer 30.
It is appreciated that in the present embodiment, forming the polysilicon layer 30, the polysilicon in the oxide layer 20
For layer 30 between the dielectric layer 40 and the oxide layer 20, the polysilicon layer 30 is undoped insulated polysilicon layer 30
Stability is high, it is subsequent it is described trim resistance 1 and trim in test process the substrate 10 is isolated with the wire 50, it is described
There is being fused into liquid trickling or splash to the polysilicon layer 30 in metal, 50 be blown, prevent short circuit and damage institute
Substrate 10 is stated, the reliability of resistance 1 is trimmed described in enhancing.
S403: dielectric layer 40 is formed in the upper surface of the oxide layer 20 and the polysilicon layer 30；
Specifically, it is material that the dielectric layer 40, which mainly selects silica, and silica is more typically isolated refering to Fig. 6
Performance is good, the growth course of the dielectric layer 40 are as follows: boron-phosphorosilicate glass (CVD BPSG) film chemically deposited replaces normal
Phosphorosilicate glass (PSG) film of rule makees reflux medium layer 40, can be reduced to reflux temperature within 1000 DEG C, reach 800 DEG C~950
Between DEG C, thus the extra impurity diffusion of those of high temperature initiation and various defects can be minimize, select boron phosphorus silicon glass
Glass has the characteristics of low lower reflux temperature, internal stress and good insulating, even if thicker film layer is in heat treatment process later
In it is also difficult cracked, corrosion rate is lower than phosphorosilicate glass, trims precision with trim resistance 1 described in guaranteeing.
It is appreciated that in embodiments, the dielectric layer 40 covers the polysilicon layer 30, it is convenient for subsequent preparation shape
It protects the substrate 10 from damage at the wire 50 on the dielectric layer 40, while in performing etching technique, improves
The preparation process efficiency for trimming resistance 1 also improves and subsequent described trim resistance 1 and trim efficiency and measuring accuracy.
S404: be formed simultaneously on the dielectric layer 40 the first metal layer 51, with the 51 upper surface phase of the first metal layer
Second metal layer 52 even and with the third metal layer 53 that is formed in 52 upper surface of second metal layer；
Specifically, using physical vapour deposition (PVD) on the dielectric layer 40 refering to Fig. 7, refers under vacuum conditions, use
Low-voltage, the arc-discharge technique of high current evaporate target using gas discharge and make to be evaporated substance and gas all to occur
Ionization, using the acceleration of electric field, makes to be evaporated substance and its reaction product is deposited on the dielectric layer 40.The metal
Metallic link materials needed for the material of silk 50 is generally used wiring, wiring metal are completed at the same time the shallow lake of fuse materials when depositing
Product is completed at the same time the wire 50 in wiring since wiring metal can be first layer metal, second layer metal etc. at many levels
Deposit, therefore the metal that uses of the wire 50 is eventually used for one layer of gold of wiring for the metal for being routed connection
Belong to.When the wire 50 is using polysilicon, material is silicon；When the wire 50 is using metal, material is aluminium
Or copper or aluminium alloy or aluminium copper.In the present embodiment, two kinds of metals are preferably selected to do the material of the wire 50,
The material of the first metal layer 51 and the third metal layer 53 is titanium nitride, and the material of the second metal layer 52 is aluminium,
Preparation cost is lower easy to operate and trim resistance 1 described in realizing trims test, improve described in trim the reliability of resistance 1,
Reduce preparation cost.
It is appreciated that in the present embodiment, the wire 50 includes three-layer metal, wherein the first metal layer 51 and the
Three metal layers 53 are titanium nitride, and second metal layer 52 is aluminium, and titanium nitride is not anti-with the metals such as iron, chromium, calcium and magnesium at high temperature
Answer, fusing point is high, hardness is big, chemical stability is good, with the small structural material of wetting of metal and electric conductivity with higher and surpass
The property led, therefore transient high-current is added when resistance 1 trims in described trim, the first metal layer preferentially melts, reality easy to operate
Resistance 1 is trimmed described in existing trims test.
S405: etching removal is located at a part at 50 both ends of wire, and corresponding position is made to expose the dielectric layer
40, passivation layer 60 is formed in the upper surface of the third metal layer 53 and the dielectric layer 40；
Specifically, a part at 50 both ends of wire is removed using dry etching, refering to Fig. 8 by the metal
Silk 50 is acted on oxidizing substance, in a kind of very thin, fine and close, covering performance of 50 Surface Creation of wire when effect
Passivating film that is good, being firmly adsorbed on 50 surface of wire.This tunic mutually exists at independent, usually gold oxide
The compound of category.It is played metal and the completely separated effect of corrosive medium, prevents metal from contacting with corrosive medium, to make
The wire 50 stopping dissolution substantially forms passive state and reaches etch-proof effect, improves the stability of the wire 50.
It is appreciated that the passivation layer 60 can be oxide layer or p-doped, the oxide layer of boron, it is also possible to silicon nitride
Deng as protective layer.Basic demand for the passivation layer 60 is that can prevent influence of the objectionable impurities to device surface for a long time,
Thermal expansion coefficient is matched with silicon substrate, and the growth temperature of film is low, and the component and the thickness uniformity of passivating film are good, and pinhold density is lower
And readily available gradual step after photoetching, to trim the stability of resistance 1 described in enhancing.
S406: light is carried out to the passivation layer 60 for being located at 50 liang of upper sides of wire on 50 length direction of wire
It carves to be formed and trims window 61, while 53 layers of the third metal are removed in the corresponding position of window 61 that trims；
Specifically, being formed and being passivated in the upper surface of the third metal layer 53 and the dielectric layer 40 refering to Fig. 9 and Figure 13
Layer 60, then be spaced coating photoresist to the passivation layer 60 and form the first photoresist layer 70, using passivation layer described in dry etching
60, window 61 is trimmed described in the second metal layer 52 and formation until exposing.In the present embodiment, window is trimmed described in formation
The detailed process of mouth 61 are as follows: etching barrier layer (not shown) is formed on the passivation layer 60, then the shape on etching barrier layer
At the first photoresist layer 70, later using have the mask plate for trimming 61 figure of window to first photoresist layer 70 into
Row exposure, then develop, it obtains with first photoresist layer 70 for trimming 50 figure of window.To trim window with described
The photoresist of 61 figures of mouth is exposure mask, and using lithographic methods such as reactive ion etching methods, etching forms institute on etching barrier layer
State the figure opening (not shown) for trimming window 61.Then to be with the etching barrier layer for trimming 61 figure of window opening
Exposure mask removes 60 region of the passivation layer for the barrier layer covering that is not etched using the methods of wet etching or dry etching, into
And window 61 is trimmed described in being formed in the passivation layer 60.Hereafter the methods of chemical cleaning removal photoresist layer and quarter can be used
Lose barrier layer.In above process, in order to guarantee exposure accuracy, anti-reflective can be also formed between photoresist layer and etching barrier layer
Penetrate layer.
It is appreciated that the etching removal part passivation layer 60 forms described when trimming window 61, etching process needs to protect
The material selection ratio with higher for demonstrate,proving material and the dielectric layer 40 that the passivation layer 60 uses, avoids the passivation layer 60
Over etching may carve the dielectric layer 40 described to the greatest extent and expose the substrate 10, avoid the later period trim described in wire 50 fuse
It splashes and the substrate 10 conducting, causes security risk caused by the damage of the substrate, corrosive liquid, be convenient for subsequent preparation work
Skill.
S407: removing the corresponding part third metal layer 53 in 30 position of polysilicon layer and corresponds to described in this position
The top of two metal layers 52 forms fuse window 62, the projected area of the fuse window 62 on perpendicular to 10 direction of substrate
Domain is included in the view field of the polysilicon layer 30；
Specifically, 0 and Figure 14, reservation photoresist coat photoresist the second light of formation to the window 61 that trims refering to fig. 1
Photoresist layer 80 is formed and the polycrystalline in the photoetching for trimming the symmetrical center of window 61 and carrying out the passivation layer 60
The corresponding fuse window 62 of silicon layer 30.In the present embodiment, it is preferred to use the method for dry etching etches the passivation layer 60,
Expose the second metal layer 52 and forms the fuse window 62.Form the fuse window, 62 detailed process are as follows: in institute
It states and forms etching barrier layer on passivation layer 60, then form photoresist on etching barrier layer, later using with the fuse
The mask plate of 62 figure of window is exposed photoresist layer, then develops, and obtains with the fuse graph window
Two photoresist layers 80.Using the photoresist with 62 figure of fuse window as exposure mask, etched using reactive ion etching method etc.
Method, etching forms the figure opening of the fuse window 62 on etching barrier layer.Then with the fuse window figure
The etching barrier layer of shape opening is exposure mask, using the methods of wet etching or dry etching, removes the barrier layer covering that is not etched
60 region of the passivation layer, and then the fuse window 62 is formed in the passivation layer 60.Hereafter chemical cleaning can be used
The methods of removal photoresist layer and etching barrier layer.In above process, in order to guarantee exposure accuracy, can also in photoresist layer and
Anti-reflecting layer is formed between etching barrier layer.
It is appreciated that in the present embodiment, forming the fuse window 41 using dry etching, wherein dry etching is easy
In control, the passivation layer 60 is performed etching and exposes the second metal layer 52, the size for forming the fuse window 62 is small
In the size of the fuse window, and form the etch period of the fuse window 62 and energy is less than to be formed and described trims window
61 preparation process, reduces preparation cost, and the size of the polysilicon layer 30 is greater than the fuse window 62, and each direction
It is 2um at least bigger than the fuse window 62, the technique for forming the groove 65 is prepared convenient for subsequent.
S408: isotropic etch is carried out to the fuse window 62, is formed on the dielectric layer 40 and the fuse
The bottom of the corresponding groove 65 of window 62, the groove 65 is the polysilicon layer 30, eventually forms and trims resistance 1.
Specifically, 1, Figure 12, Figure 15 and Figure 16, reservation photoresist carry out the fuse window 62 each to same refering to fig. 1
Property etching, etching can use chemical etching, can also be with using plasma dry etching, by corresponding Jie of the fuse window
40 over etching of matter layer exposes the polysilicon layer 30.In the present embodiment, using isotropic etching to the quarter of silicon and metal
It is slower to lose rate, this same wet etching of dry etching principle, but reactant is that plasma is different from wet etching, is avoided pair
The first metal layer 51, second metal layer 52 and the substrate 10 impact.It is described for forming the bottom of the groove 65
Polysilicon layer 30 removes all photoresists after the completion, carries out routing connecting wire in the window 61 that trims, is convenient for subsequent progress
It is described trim resistance 1 trim test.
It is appreciated that the bottom of the groove 65 is polysilicon layer 30, make the wire 50 vacantly in the polysilicon
30 top of layer, it is described trim resistance 1 and trim when, the wire 50 is blown splashing or trickling to the polysilicon layer 30
On, prevent from being connected with the substrate 10 generation short circuit, causes the problem of trimming unsuccessfully, further improves and described trims resistance 1
Trim efficiency and measuring accuracy.
It is appreciated that, in the case where current density is not high, the relationship of electric current and resistance is abided by according to the physical characteristic of conductor
From Ohm's law, but as current density very high (104A/cm2 or more), the transmission of mobile carrier will cause the wire
The gradually displacement of metallic atom in 50 makes the wire 50 cavity and accumulation generation electromigration occur.The wire 50
Material when being aluminium, when current density is close to 5E104A/cm2, electromigration will become obviously, due to the appearance of electromigration, to draw
It plays metallic atom and gradually removes script die locations, adjacent intercrystalline is made to form gap, subtract the effective cross section product of conducting wire
Small, current convergence to line remainder did not occurred the remaining conductor part of electron transfer originally so that current density increases
There is electromigration, gap occur more, until conducting wire is cut off.Theoretical, the process of electric current flowing according to the thermal conductivity of conductor
In heat can be generated due to electronic impact metal ion, and the size of heat and current density is directly proportional, current density it is more big more
It concentrates, the heat of generation is bigger, when heat reaches the fusing point of metal, the wire 50 is made fusing evaporation occur.
It is appreciated that according to the simulation conclusion of conductor, it is described trim resistance 1 and trim when, what is generally used is all moment
High current condition, the conducting trimmed during the trimming of resistance 1 with instantaneous large-current, occurring, electromigration conducting wire is extremely short
While occurring cavity and accumulation in time, also sharply increasing along with heat, temperature increase rapidly and reach the metal
The fusing point of silk 50, the bigger place of current density occur electromigration fastlyer and reach fusing point, and the electric current of the wire 50 turns again
Neighbouring unblown region is moved on to, then current density is increased sharply in unblown region, electromigration and temperature also and then occurs
Rapid raising, until 50 section of wire fuse, achieve the effect that trim test.
In addition, the trend and density of electric current are changed, and electric current is one by one according to the physical characteristic of conductor and simulation conclusion
The wire 50 that is delivered in of electron transmission, electric current gathers, in the highest current density of the wire 50.With two dimension
For simulation, if using aluminum material be 50 width and thickness of the wire represented as 1um, when by electric current be 10mA when, institute
50 two sides current density of wire is stated in 1E106A/cm2 hereinafter, the current density of the wire 50 has reached 5E106A/cm2
Left and right.When being 100mA by electric current, the 50 two sides current density of wire is in 9E106A/cm2 hereinafter, the wire
50 current density has reached 1.8E107A/cm2 or so.It can be seen that used metal is often the nitrogen of Multi-layer composite
Change titanium, the levels such as metallic aluminium are often combined, and the fusing point of certain refractory metals is even as high as 2000 DEG C or more.Described
During trimming the trimming of resistance 1, it often will appear aluminium and be blown, and such case that refractory metal still connects, or
Wire 50 described in the moment trimmed is blown, but the liquid aluminium of melt may flow back and 50 both ends of wire is caused to be weighed
It newly bridges and causes to trim failure.In the present embodiment, the resistivity of second metal 52 and fusing point are respectively less than described
The resistivity and fusing point of one metal layer 51, fusing, which preferentially occurs, in the second metal layer 52 becomes liquid, the second metal layer
51 occur trickling or splashing on the polysilicon layer 30, and the conduction and thermally conductive pathways with the substrate 10, Zhi Housuo has been isolated
Stating the first metal layer 51 and occurring fusing into liquid under the heat that the first metal layer 51 generates can also trickle or splash to institute
State polysilicon layer 30, due to the polysilicon layer 30 be undoped insulated polysilicon layer 30, be high resistance and thermal conductivity it is low
The characteristics of prevent the wire 30 fusing from generating heat influence the substrate 10 and other circuits, therefore, the fuse
The polysilicon layer 30 of 62 lower section of window can effectively prevent damage of the liquid metal splashing to the substrate 10, system twice
Preparation Method is simple, and the manufacturing cost of resistance 1 is trimmed described in reduction.
The present invention forms oxide layer 20, in institute by providing a kind of preparation method for trimming resistance 1 on the substrate 10
Deposit polycrystalline silicon layer 30 in oxide layer 20 is stated, dielectric layer 40 is formed in 30 upper surface of oxide layer, on the dielectric layer 40
It is formed simultaneously the first metal layer 51, the second metal layer 52 being connected with 51 upper surface of the first metal layer and is formed in interval
The third metal layer 53 of 52 upper surface of second metal layer forms passivation layer 60 on the wire 50, and described in progress
Passivation layer 60 on 50 length direction of wire positioned at 50 liang of upper sides of wire, which is lithographically formed, trims window 61, is formed in
50 upper surface of wire fuse window 62 corresponding with the polysilicon layer 30, the institute on perpendicular to 10 direction of substrate
The view field for stating fuse window 62 is included in the view field of the polysilicon layer 30, carries out respectively to the fuse window 62
Corrode to the same sex, is formed in groove 65 corresponding with the fuse window 62 on the dielectric layer 40.Wherein, first in the metal
Be located at 50 liang of upper sides of the wire on 50 length directions of silk trims window 61, then in the polysilicon layer 30 corresponding the
The top of two metal layers 52 forms fuse window 62, and the size of the fuse window 62 trims window 61 less than described, convenient for system
It is standby to form the wire 50 met the requirements.The polysilicon layer 30 is isolated by the wire 50 with the oxide layer 20, is prevented
Etch the influence to the substrate 10.Simultaneously by increasing the method for a step isotropic etching passivation layer 60, by the metal
The dielectric layer 40 of 50 lower surfaces of silk removes, so that the wire 50 is vacantly the polysilicon layer 30 above, thus blocking
The thermally conductive pathways of the wire 50 and the substrate 10, so that the wire 50 is easier to be blown completely.Effectively avoid
The substrate 10 is impacted in the heat for trimming the burning timing generation of resistance 1, even if also can with the presence of the metal of solvent
Prevent the resistance 1 that trims from burning short circuit after tune.The resistance 1 that trims can solve the disconnected problem of 50 infusibility of wire, keep away
Exempt from the short circuit problem of splashing or reflux appearance that the wire 50 is burnt during adjusting, preparation process is simple, reduces and is prepared into
Originally, resistance 1 is trimmed described in also improving trims efficiency and measuring accuracy.
The preferred embodiment of the present invention above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, several deformations can also be made, improves and substitutes, these belong to this hair
Bright protection scope.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. one kind trims resistance, it is characterised in that: it include substrate, formed oxide layer over the substrate, be formed in it is described
Polysilicon layer in oxide layer and the gold for being formed in the dielectric layer of the oxide layer upper surface, being formed in the dielectric layer upper surface
Belong to silk, positioned at two upper side of wire trim window on the wire length direction, the wire includes the
One metal layer, the second metal layer being connected with the first metal layer upper surface and it is formed in the second metal layer upper surface
Spaced third metal layer, the resistance that trims further includes upper surface and the polysilicon positioned at the second metal layer
The corresponding fuse window of layer is formed in and described trim the passivation layer of window two sides and be formed on the dielectric layer and the fuse
The corresponding groove of window, the passivation layer formation in the upper surface of the third metal layer and the dielectric layer, the groove
Bottom is the polysilicon layer, and the view field of the fuse window is included in described more on the direction perpendicular to the substrate
In the view field of crystal silicon layer.
2. according to claim 1 trim resistance, it is characterised in that: the polysilicon on perpendicular to the substrate direction
The view field of layer is included in the view field of the oxide layer.
3. according to claim 1 trim resistance, it is characterised in that: the material of the first metal layer and second gold medal
The material for belonging to layer is different, identical as the material of the third metal layer.
4. a kind of preparation method according to claim 1 for trimming resistance, which is characterized in that comprise the following steps that:
S401: a substrate is provided, forms oxide layer over the substrate；
S402: the deposit polycrystalline silicon layer in the oxide layer；
S403: dielectric layer is formed in the upper surface of the oxide layer and the polysilicon layer；
S404: the second gold medal for being formed simultaneously the first metal layer on the dielectric layer, being connected with the first metal layer upper surface
Belong to layer and with the third metal layer that is formed in the second metal layer upper surface；
S405: etching removal is located at a part at the wire both ends, so that corresponding position is exposed the dielectric layer, described
The upper surface of third metal layer and the dielectric layer forms passivation layer；
S406: the passivation layer for being located at two upper side of wire on the wire length direction be lithographically formed trimming
Window, while the third metal layer is removed in the corresponding position of window that trims；
S407: removing the corresponding part third metal layer in the polysilicon layer position and corresponds to the second metal layer in this position
Top formed fuse window, on perpendicular to the substrate direction view field of the fuse window be included in the polycrystalline
In the view field of silicon layer；
S408: isotropic etch is carried out to the fuse window, it is corresponding with the fuse window to be formed in the dielectric layer
The bottom of groove, the groove is the polysilicon layer, eventually forms and trims resistance.
5. the preparation method according to claim 4 for trimming resistance, it is characterised in that: in the step S402, first in institute
One layer of polysilicon layer of deposition in oxide layer is stated, then the polysilicon layer is etched and retains the part polysilicon layer.
6. the preparation method according to claim 4 for trimming resistance, it is characterised in that: the first metal layer and described the
The material of three metal layers is titanium nitride, and the material of the second metal layer is aluminium.
7. the preparation method according to claim 4 for trimming resistance, it is characterised in that: the step S406, first to described
The upper surface interval coating photoresist of passivation layer forms the first photoresist layer, then carries out the photoetching of the passivation layer, corresponding position
Expose the second metal layer.
8. the preparation method according to claim 4 for trimming resistance, it is characterised in that: the step S407 is repaired to described
It adjusts window coating photoresist to form the second photoresist layer, then carries out the photoetching of the corresponding passivation layer in the polysilicon layer position, it is right
Position is answered to expose the second metal layer.
9. the preparation method according to claim 4 for trimming resistance, it is characterised in that: in the step S408, remove institute
The dielectric layer for stating fuse window lower surface exposes the polysilicon layer.
10. the preparation method according to claim 4 for trimming resistance, it is characterised in that: the window that trims is perpendicular to institute
The view field's area for stating substrate is greater than the fuse window perpendicular to view field's area of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810863087.3A CN109065522A (en) | 2018-08-01 | 2018-08-01 | Trim resistance and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810863087.3A CN109065522A (en) | 2018-08-01 | 2018-08-01 | Trim resistance and preparation method thereof |
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| CN109065522A true CN109065522A (en) | 2018-12-21 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120351A (en) * | 2019-04-02 | 2019-08-13 | 福建省福联集成电路有限公司 | A kind of metal column production method and semiconductor devices |
| CN112687558A (en) * | 2020-12-05 | 2021-04-20 | 西安翔腾微电子科技有限公司 | Method for improving laser trimming polysilicon resistance precision |
-
2018
- 2018-08-01 CN CN201810863087.3A patent/CN109065522A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120351A (en) * | 2019-04-02 | 2019-08-13 | 福建省福联集成电路有限公司 | A kind of metal column production method and semiconductor devices |
| CN112687558A (en) * | 2020-12-05 | 2021-04-20 | 西安翔腾微电子科技有限公司 | Method for improving laser trimming polysilicon resistance precision |
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