CN110120351A - A kind of metal column production method and semiconductor devices - Google Patents
A kind of metal column production method and semiconductor devices Download PDFInfo
- Publication number
- CN110120351A CN110120351A CN201910259350.2A CN201910259350A CN110120351A CN 110120351 A CN110120351 A CN 110120351A CN 201910259350 A CN201910259350 A CN 201910259350A CN 110120351 A CN110120351 A CN 110120351A
- Authority
- CN
- China
- Prior art keywords
- metal column
- metal
- layer
- etch resistant
- layer photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 101
- 239000002184 metal Substances 0.000 title claims abstract description 101
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052802 copper Inorganic materials 0.000 claims abstract description 16
- 239000010949 copper Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 11
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 238000007747 plating Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000010415 tropism Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention discloses a kind of metal column production method and semiconductor devices, and wherein method includes the following steps: to make first layer photoresist in the semiconductor device surface with connection metal, and the connection metal is used to connect with metal column；Etch resistant buffer layer is made on first layer photoresist；Second layer photoresist is made on etch resistant buffer layer；The exposure development on second layer photoresist removes the second layer photoresist of metal column position to be produced；Remove the etch resistant buffer layer of metal column position to be produced；Metal column position to be produced is etched using anisotropic etching, removes the first layer photoresist of metal column position to be produced, exposes connection metal.This programme is blocked by etch resistant buffer layer, first layer photoresist is etched using anisotropic etching, it is vertical that first layer photoresist after etching may be implemented forms through-hole wall, it is vertical that metal column side wall is then formed in through-hole, guarantee that the spacing of each copper post is consistent, convenient for the subsequent progress for reducing copper post spacing technique.
Description
Technical field
The present invention relates to semiconductor fabrication techniques field more particularly to a kind of metal column production method and semiconductor devices.
Background technique
Semiconductor devices needs to be drawn metal layer with copper post, to realize external electrical connections.Existing copper post production is with dry
Film is placed directly against on wafer or to be coated with thick photoresist, then is aligned, and the mode of development obtains the copper post side wall profile to be made, and
Laggard row metal deposition, photoresist removal just form copper post.For blocked up photoresist in development, the profile formed can be not necessarily vertical
Directly, not can guarantee that copper post side wall is vertical in a manner of coating, alignment and development in this way, so as to cause formation copper post spacing not
One.
Summary of the invention
For this reason, it may be necessary to provide a kind of metal column production method and semiconductor devices, solving existing copper post side wall profile can not
Vertical problem.
To achieve the above object, a kind of metal column production method is inventor provided, is included the following steps:
There is the semiconductor device surface of connection metal to make first layer photoresist, the connection metal is used for and metal column
Connection；
Etch resistant buffer layer is made on first layer photoresist；
Second layer photoresist is made on etch resistant buffer layer；
The exposure development on second layer photoresist removes the second layer photoresist of metal column position to be produced；
Remove the etch resistant buffer layer of metal column position to be produced；
Metal column position to be produced is etched using anisotropic etching, removes the first of metal column position to be produced
Layer photoresist exposes connection metal；
Metal is plated in connection metal and first layer photoresist, is formed and the metal column that connect metal and connect.
Further, it after the etch resistant buffer layer that step removes metal column position to be produced, further comprises the steps of:
Remove second layer photoresist.
Further, the etch resistant buffer layer is formed to be deposited, in a manner of sputter or plating.
Further, the metal column is formed by way of being electroplated or being deposited.
Further, it further comprises the steps of: and forms solder on metal column.
It further, further include flowing back to solder.
Further, removal etch resistant buffer layer and first layer photoresist are further comprised the steps of:.
Further, the metal column is copper post.
Further, the etch resistant buffer layer is TiW, TiW-Au or nitride.
The present invention provides semiconductor devices, and the semiconductor devices is made for the above method.
It is different from the prior art, above-mentioned technical proposal is blocked by etch resistant buffer layer, uses anisotropic etching pair
First layer photoresist is etched, and the first layer photoresist formation through-hole wall after etching may be implemented is vertical, then the shape in through-hole
It is vertical at metal column side wall, guarantee that the spacing of each copper post is consistent, convenient for the subsequent progress for reducing copper post spacing technique.
Detailed description of the invention
Fig. 1 is the structural schematic diagram after the second layer photoresist for removing metal column position to be produced；
Fig. 2 is the structural schematic diagram for removing the etch resistant buffer layer of metal column position to be produced；
Fig. 3 is the structural schematic diagram after the first layer photoresist for removing metal column position to be produced；
Fig. 4 is the structural schematic diagram for having made metal column and solder；
Fig. 5 is the structural schematic diagram for eliminating the metal column after first layer photoresist；
Fig. 6 is the structural schematic diagram after solder reflux.
Description of symbols:
1, metal column；
2, metal is connected；
3, semiconductor devices；
PR1, first layer photoresist；
10, insulating layer；
4, etch resistant buffer layer；
PR2, second layer photoresist；
5, solder.
Specific embodiment
Technology contents, construction feature, the objects and the effects for detailed description technical solution, below in conjunction with specific reality
It applies example and attached drawing is cooperated to be explained in detail.
Fig. 1 to Fig. 6 is please referred to, the present embodiment provides a kind of metal column production methods, for making on the semiconductor device
Metal column 1, metal column realize the external electrical connection with semiconductor devices, can be copper post either other alloy columns.This hair
It is bright to include the following steps: that there is 3 surface of semiconductor devices of connection metal 2 to make first layer photoresist PR1, the connection metal
2 with metal column 1 for connecting.Wherein semiconductor devices can be gallium arsenide semiconductor device, and connection metal is in semiconductor device
The metal layer made on part, for being electrically connected, in order to realize the insulation between other structures, the general metallic perimeter that connects can be with
Insulating layer 10 is set, can be nitride, such as silicon nitride layer.
Etch resistant buffer layer 4 is then made on first layer photoresist；Etch resistant buffer layer can bear subsequent non-etc.
Isotropic etch, i.e., realize first layer photoresist etching when, etch resistant buffer layer however be etched.As the etch resistant buffer layer is
TiW (tungsten titanium), TiW-Au (tungsten titanium) or nitride (such as silicon nitride).Wherein TiW-Au is the metal of TiW and Au composition.Then
Second layer photoresist PR2 is made on etch resistant buffer layer；The exposure development on second layer photoresist removes metal column position to be produced
The second layer photoresist set, as shown in Figure 1.Metal column position, that is, metal column is in the projection perpendicular to semiconductor devices direction, in this way
The etch resistant buffer layer of metal column position can be exposed, the other positions of etch resistant buffer layer are still covered by second layer photoresist.With
And the etch resistant buffer layer of removal metal column position to be produced, as long as shown in Fig. 2, generally exposed etch resistant buffer layer is put
It is etched into etching solution, etching solution can only etch etch resistant buffer layer, without etching photoresist (i.e. photoresist), due to the
Two layers of photoresist block, then the etch resistant buffer layer of only metal column position can be etched.
Then metal column position to be produced is etched using anisotropic etching, removes metal column position to be produced
First layer photoresist exposes connection metal, as shown in Figure 3.Wherein, anisotropic etching is to make reaction gas raw using radio-frequency power supply
At reactivity high ion and electronics, physical bombardment and chemical reaction are carried out to semiconductor devices, needed with the removal of selectivity
The region to be removed.The substance being etched becomes escaping gas, detaches through air extractor.Ion and electronic action direction are only hung down
Directly in semiconductor device surface, etch buffer layers play the role of stopping ion and electronics, thus the first layer photoresist after etching
Inner wall be perpendicular to semiconductor devices.And isotropic etching is vertically oriented and is etched with horizontal direction with equal proportion,
Peviform pattern is formed, using wet etching as representative.The diatropism rate of etch of anisotropic etching is very slow or is 0, and energy is bigger,
Anisotropic etching directionality is stronger.
After anisotropic etching, cylindrical hole, and cylindrical side wall and semiconductor device can be formed on first layer photoresist
Part is vertical.Plate metal in connection metal and first layer photoresist, formed with the metal column that connect metal and connect, as shown in Figure 4.
Such metal column side wall is just bonded with by side wall completely, keeps plumbness.Metal column each in this way and other metal columns
Between spacing would not because of metal column deflection and become larger or become smaller, after prior art becomes smaller due to spacing, for reality
Show scheduled spacing it is necessary to increase metal intercolumniation.Spacing of the present invention will not become smaller, then can reduce in subsequent technique
The spacing of metal column can realize more metal column quantity in unit area.
In certain embodiments, it after the etch resistant buffer layer that step removes metal column position to be produced, further comprises the steps of:
Remove second layer photoresist.The exposed of etch resistant buffer layer may be implemented in this way, facilitate the tropisms removal first layer light such as subsequent removal
Resistance.
As shown in figure 5, further comprising the steps of: removal etch resistant buffer layer and first layer light to realize the exposed of metal column
Resistance, can carry out subsequent production technology in this way.
In above-mentioned all embodiments, the etch resistant buffer layer is formed to be deposited, in a manner of sputter or plating.And it is described
Metal column is formed by way of being electroplated or being deposited.
The production of metal column is to be electrically connected, then the invention also includes steps: forming solder 5 on metal column, leads to
It crosses solder metal column may be implemented and connect with other electric devices.Further, further include flowing back to solder, may be implemented
Such as the solder structure of Fig. 6.
The present invention provides semiconductor devices, and the semiconductor devices is made for the above method.As made from the above method
Semiconductor devices is blocked by etch resistant buffer layer, is etched using anisotropic etching to first layer photoresist, Ke Yishi
First layer photoresist formation through-hole wall after now etching is vertical, and then formation metal column side wall is vertical in through-hole, guarantees each
The spacing of copper post is consistent, convenient for the subsequent progress for reducing copper post spacing technique.
It should be noted that being not intended to limit although the various embodiments described above have been described herein
Scope of patent protection of the invention.Therefore, it based on innovative idea of the invention, change that embodiment described herein is carried out and is repaired
Change, or using equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it directly or indirectly will be with
Upper technical solution is used in other related technical areas, is included within scope of patent protection of the invention.
Claims (10)
1. a kind of metal column production method, which comprises the steps of:
First layer photoresist is made in the semiconductor device surface with connection metal, the connection metal is used to connect with metal column
It connects；
Etch resistant buffer layer is made on first layer photoresist；
Second layer photoresist is made on etch resistant buffer layer；
The exposure development on second layer photoresist removes the second layer photoresist of metal column position to be produced；
Remove the etch resistant buffer layer of metal column position to be produced；
Metal column position to be produced is etched using anisotropic etching, removes the first layer light of metal column position to be produced
Connection metal is exposed in resistance；
Metal is plated in connection metal and first layer photoresist, is formed and the metal column that connect metal and connect.
2. a kind of metal column production method according to claim 1, which is characterized in that remove metal column to be produced in step
After the etch resistant buffer layer of position, further comprise the steps of:
Remove second layer photoresist.
3. a kind of metal column production method according to claim 1, which is characterized in that the etch resistant buffer layer is to steam
The mode of plating, sputter or plating is formed.
4. a kind of metal column production method according to claim 1, which is characterized in that the metal column is by plating or steams
The mode of plating is formed.
5. a kind of metal column production method according to claim 1, which is characterized in that further comprise the steps of: on metal column
Form solder.
6. a kind of metal column production method according to claim 5, which is characterized in that further include flowing back to solder.
7. according to claim 1 to a kind of metal column production method described in 6, which is characterized in that it is anti-corrosion to further comprise the steps of: removal
Carve buffer layer and first layer photoresist.
8. according to claim 1 to a kind of metal column production method described in 6 any one, it is characterised in that: the metal column
For copper post.
9. according to claim 1 to a kind of metal column production method described in 6 any one, it is characterised in that: the etch resistant
Buffer layer is TiW, TiW-Au or nitride.
10. semiconductor devices, it is characterised in that: the semiconductor devices is claims 1 to 9 any one the method system
?.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910259350.2A CN110120351A (en) | 2019-04-02 | 2019-04-02 | A kind of metal column production method and semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910259350.2A CN110120351A (en) | 2019-04-02 | 2019-04-02 | A kind of metal column production method and semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110120351A true CN110120351A (en) | 2019-08-13 |
Family
ID=67520664
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910259350.2A Pending CN110120351A (en) | 2019-04-02 | 2019-04-02 | A kind of metal column production method and semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110120351A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1392024A (en) * | 2002-06-28 | 2003-01-22 | 威盛电子股份有限公司 | Forming method for high resolution welding lug |
| CN1503337A (en) * | 2002-11-21 | 2004-06-09 | 罗姆股份有限公司 | Semiconductor device production method and semiconductor device |
| CN105006437A (en) * | 2015-07-28 | 2015-10-28 | 江阴长电先进封装有限公司 | Manufacturing method of high-density convex block structure |
| CN109065522A (en) * | 2018-08-01 | 2018-12-21 | 深圳市南硕明泰科技有限公司 | Trim resistance and preparation method thereof |
-
2019
- 2019-04-02 CN CN201910259350.2A patent/CN110120351A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1392024A (en) * | 2002-06-28 | 2003-01-22 | 威盛电子股份有限公司 | Forming method for high resolution welding lug |
| CN1503337A (en) * | 2002-11-21 | 2004-06-09 | 罗姆股份有限公司 | Semiconductor device production method and semiconductor device |
| CN105006437A (en) * | 2015-07-28 | 2015-10-28 | 江阴长电先进封装有限公司 | Manufacturing method of high-density convex block structure |
| CN109065522A (en) * | 2018-08-01 | 2018-12-21 | 深圳市南硕明泰科技有限公司 | Trim resistance and preparation method thereof |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190813 |
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| RJ01 | Rejection of invention patent application after publication |