CN108962823B - 半导体制造方法及半导体装置 - Google Patents

半导体制造方法及半导体装置 Download PDF

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CN108962823B
CN108962823B CN201710357936.3A CN201710357936A CN108962823B CN 108962823 B CN108962823 B CN 108962823B CN 201710357936 A CN201710357936 A CN 201710357936A CN 108962823 B CN108962823 B CN 108962823B
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dummy gate
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semiconductor
isolation
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CN108962823A (zh
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谢欣云
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

本申请公开了一种半导体制造方法及半导体装置，涉及半导体技术领域。其中，半导体制造方法包括：提供衬底结构；以预定去除高度去除第二区域的一部分，以使得剩余的第二区域的上表面低于第一区域的上表面，其中，第一区域为隔离区被伪栅覆盖的部分，第二区域为隔离区位于伪栅两侧中的至少一侧的部分；外延源极和漏极；去除伪栅和伪栅下的电介质层，以形成沟槽；在沟槽中形成栅极结构。通过这样的方法，能够预先去除部分源极、漏极侧面的隔离层，使得栅极下方的隔离层高度与源极、漏极侧面的隔离层高度相当，克服了源极、漏极侧面的隔离层高度低于栅极下方的隔离层高度的问题，增加了有源区的体积，从而改善了器件的直流、交流电流性能。

Description

半导体制造方法及半导体装置
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体制造方法及半导体装置。
背景技术
在鳍式场效应晶体管(Fin Field Effect Transistor，FinFET)的制造工艺中，对于包括IO(Input/Output，输入输出)模块的设备，在去除核心设备区域的伪栅极氧化物时，由于会损失部分栅极下的隔离层，导致半导体鳍片在栅极下的部分漏出隔离层的高度高于半导体鳍片源、漏区高于隔离层的高度，使得有源区的体积较小，降低半导体器件的交流电流性能；同时，由于源极/漏极区域侧面的隔离层高于栅极下方的隔离层，直流电流性能贡献较小，导致PMOS器件的源漏极间的阻抗较大且无应力影响，降低FinFET的性能。
因此，有必要提出一种新的技术方案来改善器件的直流、交流电流性能。
发明内容
本申请的一个目的在于改善器件的直流、交流电流性能。
根据本申请的一方面，提供了一种半导体装置的制造方法，包括：提供衬底结构，衬底结构包括：衬底；在衬底上的半导体鳍片；在半导体鳍片的表面上的电介质层；在半导体鳍片侧面的隔离区，隔离区的上表面低于半导体鳍片的上表面；以及覆盖电介质层的一部分和隔离区的一部分的伪栅，其中，隔离区被伪栅覆盖的部分为第一区域，隔离区位于伪栅两侧中的至少一侧的部分为第二区域；以预定去除高度去除第二区域的一部分，以使得剩余的第二区域的上表面低于第一区域的上表面；外延源极和漏极；去除伪栅和伪栅下的电介质层，以形成沟槽；以及在沟槽中形成栅极结构。
可选地，预定去除高度与去除伪栅时第一区域损失的高度相当。
可选地，还包括：根据经验或仿真结果确定预定去除高度。
可选地，还包括：根据效果调整预定去除高度。
可选地，在外延源极和漏极之前，还包括：在伪栅的侧壁和第一区域位于剩余的第二区域以上的部分的侧壁上形成第一间隔物层。
可选地，外延源极和漏极包括：在形成第一间隔物层之后，去除伪栅两侧的半导体鳍片的一部分，以形成凹陷；在凹陷中外延生长半导体材料，以形成抬升的有源区。
可选地，还包括：在形成有源区后，沉积层间电介质层，层间电介质层使得伪栅露出。
可选地，栅极结构包括：在沟槽的底部上的栅极电介质层；在栅极电介质层上的栅极。
可选地，衬底结构还包括在伪栅上的硬掩模层。
通过这样的方法，能够预先去除部分源极、漏极侧面的隔离层，使得栅极下方的隔离层高度与源极、漏极侧面的隔离层高度相当，克服了源极、漏极侧面的隔离层高度低于栅极下方的隔离层高度的问题，增加了有源区的体积，从而改善器件的直流、交流电流性能。
根据本发明的另一个方面，提出一种半导体装置，包括：衬底；在衬底上的半导体鳍片；在半导体鳍片侧面的隔离区，隔离区的上表面低于半导体鳍片的上表面；栅极结构，覆盖半导体鳍片的一部分和隔离区的一部分，其中，隔离区被栅极结构覆盖的部分为第一区域，隔离区位于栅极结构两侧中的至少一侧的部分为第二区域，第一区域的上表面与第二区域的上表面高度相当。
可选地，还包括：第一间隔物层，位于栅极结构的侧壁和第一区域位于第二区域以上的部分的侧壁上。
可选地，第一间隔物层的材料包括硅的氮化物。
可选地，第一间隔物层的厚度为2-5nm。
可选地，还包括：在栅极结构两侧至少部分位于半导体鳍片中的有源区。
这样的半导体装置其栅极下方的隔离层高度与源极、漏极侧面的隔离层高度相当，克服了源极、漏极侧面的隔离层高度低于栅极下方的隔离层高度的问题，增加了有源区的体积，从而改善器件的直流、交流电流性能。
通过以下参照附图对本申请的示例性实施例的详细描述，本申请的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本申请的示例性实施例，并且连同说明书一起用于解释本申请的原理，在附图中：
图1是根据本申请一个实施例的半导体装置的制造方法的简化流程图。
图2是根据本申请一个实施例的半导体装置的制造方法的另一个实施例的简化流程图。
图3示出了根据本申请一个实施例的衬底结构的俯视图。
图4A-图10C示出了根据本申请一些实施例的半导体装置的制造方法的各个阶段的截面图。
具体实施方式
现在将参照附图来详细描述本申请的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本申请范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本申请及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
发明人针对器件的导电性能不佳的问题进行了深入研究，发现：当去除伪栅形成沟槽时，伪栅下的隔离区可能也会被去除一部分，这使得伪栅下方的隔离区的上表面低于伪栅两侧的间隔物层的最下部，如此，导致半导体鳍片在栅极下的部分漏出隔离层的高度高于半导体鳍片源、漏区高于隔离层的高度，使得有源区的体积较小，降低半导体器件的直流、交流导电性能。据此，发明人提出了如下解决方案。
图1是根据本申请一个实施例的半导体装置的制造方法的简化流程图。
在步骤101，提供衬底结构。该衬底结构可以包括：衬底；在衬底上的半导体鳍片；在半导体鳍片的表面上的电介质层；在半导体鳍片侧面的隔离区，隔离区的上表面低于半导体鳍片的上表面；以及覆盖电介质层的一部分和隔离区的一部分的伪栅。这里，隔离区被伪栅覆盖的部分为第一区域，隔离区位于伪栅两侧中的至少一侧的部分为第二区域。
在步骤102，以预定去除高度去除第二区域的一部分，以使得剩余的第二区域的上表面低于第一区域的上表面。在一个实施例中，预定去除高度与去除伪栅时第一区域损失的高度相当，从而保证在去除伪栅后，第一区域与第二区域的高度相当。在一个实施例中，可以根据经验或仿真确定预定去除高度。在另一个实施例中，可以根据具体效果调整预定去除高度，从而尽可能使在去除伪栅后第一区域与第二区域的高度趋于相同。
在步骤103，外延源、漏极以增加有源区的体积。
在步骤104，去除伪栅和伪栅下的电介质层，以形成沟槽。
在步骤105，在沟槽中形成栅极结构。
上述制造方法中，去除了第二区域的一部分，使得剩余的第二区域的上表面低于第一区域的上表面，在去除伪栅时，第一区域的损耗使得第一区域和第二区域的重新恢复相当的高度，从而避免半导体鳍片在栅极下的部分漏出隔离层的高度高于半导体鳍片源、漏极高于隔离层的高度，增加了有源区的体积，提高了半导体装置的交流、直流性能。
图2是根据本申请另一个实施例的半导体装置的制造方法的简化流程图。
在步骤201中，提供衬底结构。
在步骤202中，以预定去除高度去除第二区域的一部分，以使得剩余的第二区域的上表面低于第一区域的上表面。在一个实施例中，预定去除高度与去除伪栅时第一区域损失的高度相当，从而保证在去除伪栅后，第一区域与第二区域的高度相当。
在步骤203中，在伪栅的侧壁和第一区域位于剩余的第二区域以上的部分的侧壁上形成第一间隔物层。
在步骤204中，去除伪栅两侧的半导体鳍片的一部分，以形成凹陷。
在步骤205中，在凹陷中外延生长半导体材料，以形成抬升的有源区。
在步骤206中，在形成有源区后，沉积层间电介质层，层间电介质层使得伪栅露出。
在步骤207中，去除伪栅和伪栅下的电介质层，以形成沟槽。在这个过程中，第一区域会损失部分，第一区域损失的高度与第二区域的预定去除高度相当。
在步骤208中，在沟槽中形成栅极结构。
通过上述方法中，在源、漏极外延前预先去除了第二区域的一部分，使得剩余的第二区域的上表面低于第一区域的上表面，在去除伪栅时，第一区域的损耗使得第一区域和第二区域的重新恢复相当的高度，从而避免半导体鳍片在栅极下的部分漏出隔离层的高度高于半导体鳍片源、漏极高于隔离层的高度，增加了有源区的体积，提高了半导体装置的交流、直流性能。
下面结合图3、图4A-图10C对根据本申请一些实施例的半导体装置的制造方法进行详细说明。需要理解的是，虽然下面的各步骤是按照工艺流程的顺序进行的描述，但是，某些步骤在一个实施例中可能并不是必须的步骤，而是优选或是可选的步骤。
图3示出了根据本申请一个实施例的衬底结构的俯视图。图NA是沿着图2所示的线A-A’截取的截面图，图NB是沿着图2所示的线B-B’截取的截面图，图NC是沿着图2所示的线C-C’截取的截面图。这里，N为3-10。除非特别指出，否则本文中的图NA、图NB和图NC均适用上面的解释。
首先，参见图4A、4B和4C，提供衬底结构。衬底结构可以包括衬底301、在衬底301上的半导体鳍片302以及在半导体鳍片302的表面上的电介质层303。
衬底301例如可以是硅衬底、锗衬底等元素半导体衬底，或者可以是砷化镓等化合物半导体衬底等。半导体鳍片302的材料可以是与衬底301的材料相同的半导体材料，也可以是与衬底301的材料不同的半导体材料。电介质层303例如可以是硅的氧化物等，例如二氧化硅。
衬底结构还可以包括在半导体鳍片302侧面的隔离区304以及覆盖电介质层303的一部分和隔离区304的一部分的伪栅305。伪栅305上可以有硬掩模层306。
参见图4A，隔离区304被伪栅305覆盖的部分为第一区域314，隔离区304位于伪栅305两侧中的至少一侧的部分为第二区域324。这里，第二区域324可以是隔离区304位于伪栅305两侧中的一侧的部分，也可以是隔离区304位于伪栅305两侧的部分。图4A示出的是第二区域324是隔离区304位于伪栅305两侧的部分的情况。
参见图4C，隔离区304(这里示出的是第二区域324)的上表面低于半导体鳍片302的上表面。
接下来，如图5A、5B和5C所示，去除第二区域324的一部分，以使得剩余的第二区域324的上表面低于第一区域314的上表面。该步骤使得第一区域314的上表面和剩余的第二区域324的上表面之间具有一定距离，该距离与接下来在去除伪栅极时伪栅极下的第一区域314损失的高度相当。
接下来，在一个实施例中，可以在图5A、5B和5C所示的结构上沉积第一间隔物层602。优选地，在沉积第一间隔物层602之前，先沉积第二间隔物层601。在一个实施例中，第一间隔物层602的材料可以包括硅的氮化物，第二间隔物层601的材料可以包括硅的氧化物。例如，可以通过原子层沉积的方式来形成第一间隔物层602和第二间隔物层601。第一间隔物层602的厚度可以为约2nm-5nm左右，例如2nm、3nm、5nm等；第二间隔物层601的厚度可以为约2nm-5nm左右，例如2nm、3nm、5nm等。
然后，如图6A、6B和6C所示，对第一间隔物层602进行选择性刻蚀，保留伪栅305的侧壁以及第一区域314位于剩余的第二区域324以上的部分的侧壁上的第一间隔物层602，从而在伪栅305的侧壁和第一区域314位于剩余的第二区域324以上的部分的侧壁上形成第一间隔物层602。
之后，优选地，可以对伪栅305两侧的半导体鳍片302的一部分进行漏极轻掺杂(LDD)。
之后，继续参见图6B和图6C，在形成第一间隔物层602之后，还可以去除伪栅305两侧的半导体鳍片302的一部分，以形成凹陷601。
接下来，如图7A、7B和7C所示，可以在凹陷601中外延生长半导体材料，以形成抬升的有源区701。这里，抬升的有源区701包括抬升的源区或漏区。
需要说明的是，衬底301上的半导体鳍片302可以包括用于NMOS器件的半导体鳍片和用于PMOS器件的半导体鳍片。在这种情况下，可以分别形成用于NMOS器件和PMOS器件的抬升的有源区701。
例如，可以先去除伪栅305两侧的用于NMOS器件的半导体鳍片的一部分，以形成凹陷601，然后在凹陷601中外延生长半导体材料，例如Si，以形成用于NMOS器件的抬升的有源区701；之后去除伪栅305两侧的用于PMOS器件的半导体鳍片的一部分，以形成凹陷601，然后在凹陷601中外延生长半导体材料，例如SiGe，以形成用于PMOS器件的抬升的有源区701。或者，也可以先按照上述方式先形成用于PMOS器件的抬升的有源区701，再形成用于NMOS器件的抬升的有源区701。
之后，如图8A、8B和8C所示，形成层间电介质层802，层间电介质层802使得伪栅305露出。例如，可以先沉积层间电介质层802，然后对沉积的层间电介质层802进行平坦化，从而露出伪栅305。优选地，在形成层间电介质层802之前，还可以在有源区701上形成接触蚀刻停止层(CESL)801。需要指出的是，在伪栅305上具有硬掩模层306的情况下，平坦化工艺还可以去除硬掩模层306。
之后，如图9A、9B和9C所示，去除伪栅305和伪栅305下的电介质层303，以形成沟槽901。在去除伪栅305时，伪栅305下的第一区域314也会被去除一部分，第一区域314被去除的高度与第二区域324在外延生长有源区之前去除的高度相当，从而如图9A所示，第一区域314与第二区域324的高度相当。另外，在形成有第二间隔物层601的情况下，伪栅305两侧的第二间隔物层601也会被去除。
之后，如图10A、10B和10C所示，在沟槽901中形成栅极结构1001。在一个实施例中，栅极结构1001可以包括在沟槽901的底部上的栅极电介质层1011以及在栅极电介质层1011上的栅极1021。此外，在沟槽901的侧壁上也可以形成栅极电介质层1011。在一个实施例中，栅极电介质层1011可以是高k电介质层，栅极1021可以是金属栅极。优选地，栅极结构1001还可以包括在沟槽901的底部的界面层1031，栅极电介质层1011形成在界面层1031上。应理解，这里的界面层1031可以通过热氧化的方式形成，故只在半导体鳍片302的表面示出了界面层1031。
本申请还提供了一种半导体装置，其可以利用但不限于利用上面给出的制造方法来制造。
在一个实施例中，参见图10A、10B和10C，半导体装置可以包括衬底301、在衬底301上的半导体鳍片302以及在半导体鳍片302侧面的隔离区304，隔离区304的上表面低于半导体鳍片302的上表面。
半导体装置还可以包括栅极结构1001。栅极结构1001覆盖半导体鳍片302的一部分和隔离区304的一部分。这里，隔离区304被栅极结构1001覆盖的部分为第一区域314，隔离区314位于栅极结构1001两侧中的至少一侧的部分为第二区域324，第一区域314的上表面与第二区域324的上表面高度相当。在一个实施例中，栅极结构1001可以包括栅极电介质层1011以及在栅极电介质层1011上的栅极1021。栅极电介质层1011在半导体鳍片302的一部分和隔离区304上。
半导体装置还可以包括第一间隔物层602。第一间隔物层602位于栅极结构1001的侧壁和第一区域314位于第二区域324以上的部分的侧壁上。优选地，第一间隔物层602的材料包括硅的氮化物。优选地，第一间隔物层602的厚度为2-5nm。
在一个实施例中，半导体装置还可以包括在栅极结构1001两侧至少部分位于半导体鳍片302中的有源区701，例如源区或漏区。
至此，已经详细描述了根据本申请实施例的半导体装置及其制造方法。为了避免遮蔽本申请的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本申请的精神和范围。

Claims (13)

1.一种半导体装置的制造方法，包括：
提供衬底结构，所述衬底结构包括：
衬底；
在所述衬底上的半导体鳍片；
在所述半导体鳍片的表面上的电介质层；
在所述半导体鳍片侧面的隔离区，所述隔离区的上表面低于所述半导体鳍片的上表面；以及
覆盖所述电介质层的一部分和所述隔离区的一部分的伪栅，其中，所述隔离区被所述伪栅覆盖的部分为第一区域，所述隔离区位于所述伪栅两侧中的至少一侧的部分为第二区域；
以预定去除高度去除所述第二区域的一部分，以使得剩余的第二区域的上表面低于所述第一区域的上表面，所述预定去除高度与去除所述伪栅时所述第一区域损失的高度相当；
外延源极和漏极；
去除所述伪栅和所述伪栅下的电介质层，以形成沟槽；以及
在所述沟槽中形成栅极结构。
2.根据权利要求1所述的方法，还包括：
根据经验或仿真结果确定所述预定去除高度。
3.根据权利要求1或2所述的方法，还包括：
根据效果调整所述预定去除高度。
4.根据权利要求1所述的方法，在所述外延源极和漏极之前，还包括：在所述伪栅的侧壁和所述第一区域位于剩余的第二区域以上的部分的侧壁上形成第一间隔物层。
5.根据权利要求4所述的方法，所述外延源极和漏极包括：
在形成所述第一间隔物层之后，去除所述伪栅两侧的半导体鳍片的一部分，以形成凹陷；
在所述凹陷中外延生长半导体材料，以形成抬升的有源区。
6.根据权利要求5所述的方法，还包括：
在形成所述有源区后，沉积层间电介质层，所述层间电介质层使得所述伪栅露出。
7.根据权利要求1所述的方法，所述栅极结构包括：
在所述沟槽的底部上的栅极电介质层；
在所述栅极电介质层上的栅极。
8.根据权利要求7所述的方法，所述衬底结构还包括在所述伪栅上的硬掩模层。
9.一种半导体装置，包括：
衬底；
在所述衬底上的半导体鳍片；
在所述半导体鳍片侧面的隔离区，所述隔离区的上表面低于所述半导体鳍片的上表面；和
栅极结构，覆盖所述半导体鳍片的一部分和所述隔离区的一部分；
其中，半导体装置为根据权利要求1～8任意一项所述的方法生成。
10.根据权利要求9所述的装置，还包括：
第一间隔物层，位于所述栅极结构的侧壁。
11.根据权利要求10所述的装置，所述第一间隔物层的材料包括硅的氮化物。
12.根据权利要求10所述的装置，所述第一间隔物层的厚度为2-5nm。
13.根据权利要求9所述的装置，还包括：
在所述栅极结构两侧至少部分位于所述半导体鳍片中的有源区。
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