CN108933131B - Interface protection device and manufacturing method thereof - Google Patents
Interface protection device and manufacturing method thereof Download PDFInfo
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- CN108933131B CN108933131B CN201810788960.7A CN201810788960A CN108933131B CN 108933131 B CN108933131 B CN 108933131B CN 201810788960 A CN201810788960 A CN 201810788960A CN 108933131 B CN108933131 B CN 108933131B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Abstract
The present invention relates to an interface protection device and a method of manufacturing the same, the interface protection device comprising: the integrated circuit comprises a substrate of a first conductivity type, a first epitaxial layer of the first conductivity type, a first buried layer of a second conductivity type, a second buried layer of the first conductivity type and a second epitaxial layer of the second conductivity type, wherein the substrate and the first buried layer form a first TVS diode, the second buried layer and the second epitaxial layer form a second TVS diode, isolation grooves are formed in two sides of each TVS diode, the first TVS diode is used for protecting an interface data line and an ID line, and the second TVS diode is used for protecting an interface power line.
Description
Technical Field
The present invention relates to the field of semiconductor device design and manufacture, and more particularly, to an interface protection device and a method of manufacturing the same.
Background
There is a need in the field of electronics to apply to a variety of interfaces, such as: serial port, parallel port and USB (Universal Serial Bus) interface, etc., the USB interface is a developed interface, and the speed of the developed interface is much faster than that of the Serial port and the parallel port, wherein the USB2.0 interface is the most common USB interface version, and the USB2.0 interface generally has 4 lines, including: 1 VBUS (Voltage Bus), 1 GND (Ground), 2D lines (DATA, DATA line) for transmitting DATA, 5 lines are respectively arranged in the Micro/mini USB interface in the D +, D-, USB2.0 interfaces, and 1 ID (IDentity) line for identifying different cable endpoints is additionally arranged. Since the interface is frequently used in an electrical environment, the interface has a high possibility of encountering surge voltage and ESD (Electro-Static discharge), and if the interface is not protected, a subsequent Circuit IC (Integrated Circuit) of the interface is easily damaged and failed. Therefore, a protection device is usually added to the interface to prevent the latter stage of circuit IC from being damaged by overvoltage. The protection method for the interface is mainly to add a TVS (transient voltage Suppressor) protection device.
Because the working voltage of the D line in the interface is lower, the working voltage of VBUS is higher, and the working voltage of the traditional single TVS protective device can only be one at present, the protective requirements of various different voltages of the interface can not be met. Technical personnel generally select a plurality of protective devices with various specifications to design the circuit board to solve the problem, which leads to the increase of the area of the circuit board and is not favorable for the development trend of continuous miniaturization of smart phones and tablet computers.
Disclosure of Invention
The invention provides an interface protection device, which can simultaneously protect power lines and data lines with different working voltages in an interface, simplify the design of a circuit board and reduce the area of the circuit board.
In one aspect, the present invention provides an interface protection device, comprising:
a substrate of a first conductivity type, the substrate having a first surface and a second surface;
a first epitaxial layer of a first conductivity type grown on a first surface of the substrate;
a first buried layer of a second conductivity type and a second buried layer of a first conductivity type formed on the first epitaxial layer, the first buried layer of the second conductivity type and the epitaxial layer of the first conductivity type forming a first TVS diode;
a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, the second epitaxial layer and the second buried layer forming a second TVS diode;
and the isolation groove is formed between the first TVS diode and the second TVS diode, penetrates through the first epitaxial layer and the second epitaxial layer and extends to the substrate of the first conductivity type.
In another aspect, the present invention provides a method for manufacturing an interface protection device, including:
providing a substrate of a first conductivity type, the substrate comprising a first surface and a second surface;
epitaxially forming a first epitaxial layer of a first conductivity type over a first surface of the substrate;
forming a first buried layer of a second conductivity type and a second buried layer of a first conductivity type on a first epitaxial layer of the first conductivity type, wherein the first buried layer and the first epitaxial layer form a first TVS diode;
epitaxially growing a second epitaxial layer of a second conductivity type on the first epitaxial layer of the first conductivity type again, wherein the second epitaxial layer and the second buried layer form a second TVS diode;
and forming an isolation groove between the first TVS diode and the second TVS diode, wherein the isolation groove penetrates through the first epitaxial layer and the second epitaxial layer and extends to the substrate with the first conductivity type.
According to the technical scheme, the TVS protection device with the equivalent circuit formed by connecting the TVS diodes in parallel enables different voltage protection requirements to be met by only one device, and has the excellent characteristic of wide protection voltage range.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention.
FIG. 1 is a schematic diagram of an interface protection device according to some embodiments of the invention;
FIG. 2 is a circuit block diagram of an interface protection device provided by some embodiments of the invention;
fig. 3 is a schematic flow chart illustrating a process for manufacturing an interface protection device according to some embodiments of the present invention.
Description of reference numerals:
1: a substrate of a first conductivity type; 2: a first epitaxial layer of a first conductivity type; 3: a first buried layer of a second conductivity type; 4: a second buried layer of the first conductivity type; 5: a second epitaxial layer of a second conductivity type; 6: an isolation trench; 7: a first well region of a first conductivity type; 8: a second well region of a second conductivity type; 9: a first conductive region of a first conductivity type; 10: a second conductive region of a second conductivity type; 11: a back metal; 12: a front metal; 31: IO 1; 32: VCC; 33: IO 2; 34: IO 3; 41: GND; 51: a USB2.0 port; 52: an interface protection device; 53: a USB drive circuit; 54: the IC is charged.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, steps, and do not preclude the presence or addition of one or more other features, steps, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It is further noted that the terms "upper," "lower," "inner," "outer," and the like are used in an orientation or positional relationship that is based on the orientation or positional relationship shown in the drawings, or that is conventionally used in the practice of the invention, merely to facilitate the description and simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be considered limiting of the invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
The technical scheme of the embodiment of the invention can be applied to a computer interface, and the interface comprises: serial port, parallel port, USB interface, etc. for convenience of the following description, we choose to use USB2.0 interface as the specific implementation object to describe the technical solution of the present invention in detail.
The technical scheme of the invention relates to the design and manufacture of semiconductor devices, wherein a semiconductor refers to a material with controllable conductivity and variable conductivity range from an insulator to a conductor, common semiconductor materials comprise silicon, germanium, gallium arsenide and the like, and silicon is the most influential of various semiconductor materials and is the most widely applied one. The semiconductor is divided into an intrinsic semiconductor, a P-type semiconductor and an N-type semiconductor, the semiconductor without impurities and without lattice defects is called an intrinsic semiconductor, trivalent elements (such as boron, indium, gallium and the like) are doped into a pure silicon crystal to replace the bits of silicon atoms in the crystal lattice to form a P-type semiconductor, pentavalent elements (such as phosphorus, arsenic and the like) are doped into a pure silicon crystal to replace the positions of the silicon atoms in the crystal lattice to form an N-type semiconductor, the conductivity types of the P-type semiconductor and the N-type semiconductor are different, in the embodiment of the invention, the first conductivity type is P-type, the second conductivity type is N-type, in the embodiment of the invention, if not specifically stated, the preferred doped ions of each conductivity type can be replaced by ions with the same conductivity type, and the description is omitted below.
Some embodiments of the present invention provide an interface protection device, please refer to fig. 1, the interface protection device includes: a substrate 1 of a first conductivity type, the substrate 1 having a first surface and a second surface; a first epitaxial layer 2 of a first conductivity type grown on a first surface of said substrate 1; a first buried layer 3 of a second conductivity type and a second buried layer 4 of a first conductivity type formed on the first epitaxial layer 2, the first buried layer 3 of the second conductivity type and the epitaxial layer 2 of the first conductivity type forming a first TVS diode; a second epitaxial layer 5 of a second conductivity type grown on the first epitaxial layer 2, the second epitaxial layer 5 and the second buried layer 4 forming a second TVS diode; and the isolation groove 6 is formed between the first TVS diode and the second TVS diode, penetrates through the first epitaxial layer 2 and the second epitaxial layer 5, and extends to the substrate 1 of the first conductivity type.
It can be understood that, in the technical scheme of the invention, a plurality of TVS diodes are designed on one interface protection device, the first TVS diode is used for protecting the interface data line and the I D line, and the second TVS diode is used for protecting the interface power line, so that all lines in the interface can be protected by only one device, the original protection devices with various specifications and in large quantity are replaced, the integration level of the device is greatly improved, and the miniaturization of the device is facilitated.
Specifically, referring to fig. 1, the material of the substrate 1 may be a silicon substrate 1, a germanium substrate 1, or the like, in this embodiment, the material of the substrate 1 is preferably the silicon substrate 1, and silicon is the most common, cheap, and stable-performance semiconductor material. In the embodiment of the present invention, the first conductivity type is P-type, and the preferred doping ions of the substrate 1 are boron ions, which have smaller atomic weight and can be implanted deeper at the same energy, and in other embodiments, may also be other trivalent ions such as indium and gallium.
Specifically, referring to fig. 1, the first epitaxial layer 2 is formed by homoepitaxy with a relatively simple process, that is, the material of the first epitaxial layer 2 is the same as the material of the substrate 1, when the material of the substrate 1 is silicon, the material of the first epitaxial layer 2 is also silicon, the difficulty of the homoepitaxy process is low, the process control is easier, in other embodiments, the first epitaxial layer 2 may also be formed by heteroepitaxy, and the material of the first epitaxial layer 2 may also be a semiconductor material such as germanium, selenium, and the like. More specifically, the epitaxial growth method may be a vapor phase epitaxial growth method, a liquid phase epitaxial growth method, a vacuum evaporation growth method, a high frequency sputtering growth method, a molecular beam epitaxial growth method, or the like, and is preferably a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method), which is a process of reacting a gaseous reaction material on a surface of a solid substrate and depositing a solid thin layer or a thin film, and is a relatively mature epitaxial growth method of a transistor, in which silicon and a doping element are sprayed on the substrate 1, and which has good uniformity, good repeatability, and excellent step coverage.
Specifically, referring to fig. 1, the thickness and concentration of the first epitaxial layer 2 are closely related to the clamping voltage of the first TVS diode, and preferably, the thickness of the first epitaxial layer 2 is 7 ± 0.5 μm, the resistivity is 0.3-3ohm CM, the thickness of the first epitaxial layer 2 is thin, and the on-resistance is low, so that the first TVS diode has the excellent characteristics of low clamping voltage.
Specifically, referring to fig. 1-2, the first buried layer 3 and the second buried layer 4 are formed by photolithography implantation on the first epitaxial layer 2, and the implantation dose of the second buried layer 4 determines the breakdown voltage of the second TVS diode, preferablyOptionally, the first buried layer 3 is implanted with antimony, and because the buried layer cannot be too deep, the element with large atomic weight and high solid solubility is selected, the implantation energy is 80-120 KeV (kiloelectron volt), and the implantation dose is 1E 15-5E 15CM-2To obtain a suitable junction depth of the buried layer, the second buried layer 4 is implanted with boron at an implantation energy of 60-80 KeV and an implantation dose of 5E 14-8E 14CM-2Therefore, the second TVS diode has a high breakdown Voltage, and since the VCC terminal 32(Voltage to current Converter) is connected in series with the second TVS diode having a breakdown Voltage greater than the operating Voltage of the subsequent charging IC 54, the subsequent circuit can be protected.
Specifically, referring to fig. 1, the second epitaxial layer 5 is formed by epitaxial growth again on the first epitaxial layer 2, preferably, the second epitaxial layer 5 has a thickness of 5 ± 0.5 μm, a resistivity of 0.02 to 0.2ohm CM, and a growth temperature of 1150 to 1180 ℃.
Specifically, referring to fig. 1-2, the isolation trench 6 is formed at two sides of each TVS diode, penetrates through the first epitaxial layer 2 and the second epitaxial layer 5, and extends to the substrate 1, preferably, the depth of the isolation trench 6 is 14 to 16 μm, the width of the trench is 1 to 1.5 μm, the isolation trench 6 is filled with silicon dioxide, the isolation trench 6 separates each TVS diode into different lines, more specifically, each TVS diode is led out through the front metal 12, the first TVS diode corresponds to IO131(Input/Output ), IO233, IO334, the second TVS diode corresponds to VCC 32, preferably, the thickness of the front metal 12 is 2 to 4 μm, and the back metal 11 is formed on the second surface of the substrate 1 and serves as the ground terminal GND 41.
As shown in fig. 2, in this embodiment, when the interface protection device 52 is used, the IO1, the IO2, and the IO3 are respectively connected to the D +, D-, and USB ID lines of the USB2.0 port 51, and are respectively connected to the D +, D-, and USB ID lines of the USB driving circuit 53, so as to protect the data terminal, the VCC is connected to the VBUS line of the USB2.0 port 51, the power supply or charging IC 54 line is protected, and the GND is connected to the ground, so that the purpose that one protection device can protect all lines of the interface is achieved, and the interface protection device has an excellent characteristic of wide protection voltage range.
Further, as shown in FIG. 1,forming a first well region 7 of the first conductivity type and a second well region 8 of the second conductivity type in the second epitaxial layer 5, preferably, the second well region 8 is implanted with phosphorus, and since the second well region 8 needs a certain depth, phosphorus with faster diffusion is used, the implantation energy is 80-100 keV, and the implantation dose is 2E 12-5E 12CM-2The implantation element of the first well region 7 is boron, the implantation energy is 60-80 KeV, and the implantation dose is 1E 12-3E 12CM-2The junction depth of the first well region 7 and the second well region 8 is 2.5 ± 0.3 μm, the first well region 7 and the second epitaxial layer 5 form a first P-N diode, the first P-N diode is located above the first TVS diode, because the first well region 7 has a small doping dose, a low concentration, and a low concentration of the second epitaxial layer 5, the first P-N diode has a wider depletion layer, and therefore, the capacitance is extremely low, and after the first P-N diode is connected in series with the first TVS diode, the capacitance of the whole line can be reduced, so that data is not easy to lose during transmission, the first well region 7 and the second well region 8 are formed with a first semiconductor region 9 and a second semiconductor region 10 which have the same conductivity type as the first well region 7 and the second well region 8, preferably, the second semiconductor region 10 is implanted with arsenic, and because the second semiconductor region 10 is mainly used as ohmic contact, the arsenic implantation can obtain better surface characteristics, the implantation energy is 80-120 KeV, the implantation dosage is 1E 15-5E 15CM-2, the impurity implanted in the first semiconductor region is boron difluoride, the implantation energy is 60-80 KeV, and the implantation dosage is 4.5E15CM-2。
Further, referring to fig. 1 and fig. 2, a second P-N diode formed by the second epitaxial layer 5 and the first epitaxial layer 2 may be further included between the TVS diodes, the second P-N diode is connected in parallel with the first TVS diode and the first P-N diode, the isolation trench 6 is also formed on both sides of the second P-N diode, the conductivity type of the well region above the second P-N diode is the same as the conductivity type of the first epitaxial layer 5, the breakdown voltage of the second P-N diode is very high and is much higher than the sum of the voltages of the first P-N diode and the first TVS diode, so that when the surge voltage is not high, only one side of the first P-N diode and the first TVS diode is turned on to work to discharge the surge voltage and the surge current, when the surge voltage is high, the second P-N diode can break down, and the depletion layer is wider, so that the capacitance is lower, the surge voltage and surge current protection effects are achieved, and meanwhile, the influence on a data transmission signal is small.
The interface protection device provided by the invention has the main advantages that: (1) VBUS, D +, D-and ID with different working voltages in the interface can be protected simultaneously, namely, different voltage protection requirements can be met by only one device. (2) When the invention protects VBUS, the invention has excellent high-power characteristic with wide protection voltage range. (3) The invention has the characteristics of low capacitance and low clamping voltage when protecting D + and D-, and can effectively prevent packet loss and other abnormalities during data transmission.
Fig. 3 is a schematic view illustrating a manufacturing process of an interface protection device according to some embodiments of the present invention.
As shown in fig. 3, the method of an embodiment of the present invention may include the following steps S101-S109.
S101: a substrate of a first conductivity type is provided.
Specifically, referring to fig. 1-2, the substrate 1 serves as a carrier of the semiconductor device, and mainly serves as a support. The material of the substrate 1 may be a silicon substrate, a germanium-silicon substrate, or the like, and in this embodiment, the material of the substrate 1 is preferably a silicon substrate, and silicon is the most common, inexpensive, and stable-performance semiconductor material. The first conductivity type is P-type, in an embodiment of the present invention, the doped ions of the substrate 1 are boron ions, the atomic weight of the boron ions is small, and the boron ions can be implanted deeper under the same energy, in other embodiments, the boron ions can also be other trivalent ions such as indium, gallium, and the like, the substrate 1 includes a first surface and a second surface, each semiconductor layer is formed on the first surface, a back metal 11 is formed on the second surface, and is used as a ground line end GND 41 of the device, the back metal 11 is formed by an evaporation process, more specifically, the plated metal material can be gold, silver, copper, zinc, chromium, aluminum, and the like, and the plated metal material is aluminum in this embodiment.
S103: a first epitaxial layer of a first conductivity type is epitaxially formed over the first surface of the substrate.
Specifically, referring to fig. 1, the first epitaxial layer 2 is formed by homoepitaxy with a simple process, that is, the material of the first epitaxial layer 2 is the same as that of the substrate 1, and when the material of the substrate 1 is silicon, the material of the first epitaxial layer 2 is also silicon. In other embodiments, the first epitaxial layer 2 may also be formed by heteroepitaxy, and the material of the first epitaxial layer 2 may also be a semiconductor material such as germanium, selenium, or the like. More specifically, the epitaxial growth method may be a vapor phase epitaxial growth method, a liquid phase epitaxial growth method, a vacuum evaporation growth method, a high frequency sputtering growth method, a molecular beam epitaxial growth method, or the like, and is preferably a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method), which is a process of reacting a gaseous reaction material on a surface of a solid substrate and depositing a solid thin layer or a thin film, and is a relatively mature epitaxial growth method of a transistor, in which silicon and a doping element are sprayed on the substrate 1, and which has good uniformity, good repeatability, and excellent step coverage.
S105: and forming a first buried layer of a second conductivity type and a second buried layer of the first conductivity type on the first epitaxial layer of the first conductivity type.
Specifically, referring to fig. 1, the first buried layer 3 and the second buried layer 4 are formed by performing photolithography implantation on the first epitaxial layer 2, and preferably, the implanted element of the first buried layer 3 is antimony, and ions with large atomic weight and high solid solubility are selected, so that the buried layer has a junction depth that is not too deep, the implantation energy is 80 to 120KeV, and the implantation dose is 1E15 to 5E15CM-2The second buried layer 4 is implanted with boron with an implantation energy of 60-80 KeV and an implantation dose of 5E 14-8E 14CM-2, the first buried layer 3 and the first epitaxial layer 2 form a first TVS diode, the first TVS diode is a TVS device and has an overvoltage protection effect, and the plurality of first TVS diodes are connected in parallel, so that the device can simultaneously protect a charging line and a data line in an interface and has the excellent characteristic of wide protection voltage range, more specifically, the thickness and concentration of the first epitaxial layer 2 are closely related to the clamping voltage of the first TVS diodePreferably, the first epitaxial layer 2 has a thickness of 7 ± 0.5 μm, a resistivity of 0.3 to 3ohm CM, and the first epitaxial layer 2 has a small thickness and a low on-resistance, so that the first TVS diode has excellent characteristics of a low clamping voltage.
S107: and epitaxially growing a second epitaxial layer of a second conductivity type again on the first epitaxial layer of the first conductivity type.
Specifically, referring to fig. 1-2, the second epitaxial layer 5 and the second buried layer 4 form a second TVS diode, the implantation dose of the second buried layer 4 determines the breakdown voltage of the second TVS diode, and since the VCC terminal 32 is connected in series with a second TVS diode having a breakdown voltage greater than the operating voltage of the subsequent charging IC 54, the subsequent circuit can be protected.
S109: and forming an isolation groove between the first TVS diode and the second TVS diode, wherein the isolation groove penetrates through the first epitaxial layer and the second epitaxial layer and extends to the substrate with the first conductivity type.
Specifically, referring to fig. 1, the isolation trench 6 is formed on two sides of each TVS diode by deep trench etching, penetrates through the first epitaxial layer 2 and the second epitaxial layer 5, and extends to the substrate 1, the etching method includes plasma etching, reactive ion etching, electron cyclotron resonance etching, inductively coupled plasma etching, etc., in this embodiment, the isolation trench 6 is filled with silicon dioxide by mature physical vapor deposition, and in other embodiments, the filling is also protected by the present invention by other methods, preferably, the isolation trench 6 has a trench depth of 14 to 16 μm and a trench width of 1 to 1.5 μm, the isolation trench 6 separates each TVS diode into different lines, more specifically, each TVS diode is led out by the front metal 12, the front metal is formed by a sputtering process, more specifically, the bombarding particles used are generally inert gas ions with positive charges, the most used is argon ion, and the thickness of the front metal 12 is preferably 2-4 μm.
Further, referring to fig. 1, a first well region 7 of the first conductivity type and a second well region 8 of the second conductivity type are formed in the second epitaxial layer 5, and the well regions are formed by a drive-in diffusion process, specifically, the drive-in process includes a temperature-raising stage,A propulsion phase and a cooling phase, more particularly comprising the steps of: A. the temperature of the well pushing process is increased, and the annealing time is shortened; B. calculating the program time of the high-temperature well-pushing process; C. carrying out test piece verification on the high-temperature trap process; D. c, detecting the test piece, judging whether the product parameters of the device meet the process requirements, if not, adjusting the process parameters and returning to the step C; E. performing a product grouping test on the device; F. obtaining a grouping test result, judging whether the product parameters and the yield meet the process requirements, if not, adjusting the process parameters and returning to the step E; G. the devices are put into batch production according to a high-temperature drive-in process, preferably, the injection element of the second well region 8 is phosphorus, and a certain depth can be obtained due to faster phosphorus diffusion, the injection energy is 80-100 KeV, and the injection dosage is 2E 12-5E 12CM-2The implantation element of the first well region 7 is boron, the implantation energy is 60-80 KeV, and the implantation dose is 1E 12-3E 12CM-2The well pushing process temperature is 1000-1050 ℃, the well pushing time is 50-75 minutes, the final junction depth of the first well region 7 and the second well region 8 is 2.5 +/-0.3 μm, the first well region 7 and the second epitaxial layer 5 form a first P-N diode, the first P-N diode is positioned on the first TVS diode, the first P-N diode has a wider depletion layer, so the capacitance is extremely low, after the first P-N diode is connected with the first TVS diode in series, the capacitance of the whole line can be reduced, the data is not easy to lose during transmission, the first well region 7 and the second well region 8 are formed with a first semiconductor region 9 and a second semiconductor region 10 which have the same conductivity type as the first well region 7 and the second well region 8, preferably, the second semiconductor region 10 is injected with arsenic as an element, so that better ohmic contact characteristics are obtained on the surface, implant energy 100KeV, implant dose 5E15CM-2The implantation impurity of the first semiconductor region is boron difluoride, the implantation energy is 60-80 KeV, and the implantation dosage is 4.5E15CM-2。
Further, referring to fig. 1, a second P-N diode formed by the second epitaxial layer 5 and the first epitaxial layer 2 may be further included between the TVS diodes, the second P-N diode is connected in parallel with the first TVS diode and the first P-N diode, the isolation trench 6 is also formed on both sides of the second P-N diode, the conductivity type of the well region above the second P-N diode is the same as the conductivity type of the first epitaxial layer 5, the breakdown voltage of the second P-N diode is very high and is much higher than the sum of the voltages of the first P-N diode and the first TVS diode, so that it is used to protect the interface, when the surge voltage is not high, only one side of the first P-N diode and the first TVS diode is conducted to operate, and surge voltage and surge current are discharged, when the surge voltage is high, the second P-N diode can break down, and the depletion layer is wider, so that the capacitance is lower, the surge voltage and surge current protection effects are achieved, and meanwhile, the influence on a data transmission signal is small.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. An interface protection device comprising:
a substrate of a first conductivity type, the substrate having a first surface and a second surface;
a first epitaxial layer of a first conductivity type grown on a first surface of the substrate;
a first buried layer of a second conductivity type and a second buried layer of a first conductivity type formed on the first epitaxial layer, the first buried layer of the second conductivity type and the epitaxial layer of the first conductivity type forming a first TVS diode;
a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, the second epitaxial layer and the second buried layer forming a second TVS diode;
the isolation groove is formed between the first TVS diode and the second TVS diode, penetrates through the first epitaxial layer and the second epitaxial layer and extends to the substrate of the first conductivity type;
the second epitaxial layer is provided with a first well region of a first conductivity type and a second well region of a second conductivity type, the first well region and the second epitaxial layer form a first P-N diode, the first P-N diode is positioned above the first TVS diode, and the first well region and the second well region are provided with a first semiconductor region and a second semiconductor region which have the same conductivity type as the first well region and the second well region; the second epitaxial layer and the first epitaxial layer form a second P-N diode, the second P-N diode is connected with the first TVS diode in parallel, and the isolation groove is also formed between the first P-N diode and the second P-N diode.
2. The interface protection device of claim 1, wherein said second P-N diode is above a second well region and a second semiconductor region of the same conductivity type as said second epitaxial layer.
3. The interface protection device of claim 1, wherein said isolation trench is a silicon dioxide isolation trench, and wherein the trench depth of said isolation trench is greater than the sum of the thicknesses of said first epitaxial layer and said second epitaxial layer.
4. A method of manufacturing an interface protection device, for manufacturing an interface protection device according to any one of claims 1 to 3, comprising:
providing a substrate of a first conductivity type, the substrate comprising a first surface and a second surface;
epitaxially forming a first epitaxial layer of a first conductivity type over a first surface of the substrate;
forming a first buried layer of a second conductivity type and a second buried layer of a first conductivity type on the first epitaxial layer of the first conductivity type, wherein the second buried layer and the first epitaxial layer form a first TVS diode;
epitaxially growing a second epitaxial layer of a second conductivity type on the first epitaxial layer of the first conductivity type again, wherein the second epitaxial layer and the second buried layer form a second TVS diode;
and forming an isolation groove between the first TVS diode and the second TVS diode, wherein the isolation groove penetrates through the first epitaxial layer and the second epitaxial layer and extends to the substrate with the first conductivity type.
5. The method as claimed in claim 4, wherein a first well region of the first conductivity type and a second well region of the second conductivity type are formed in the second epitaxial layer, a first semiconductor region and a second semiconductor region of the same conductivity type as the first well region and the second well region are correspondingly formed in the first well region and the second well region, respectively, the first well region and the second epitaxial layer form a first P-N diode, and the first P-N diode is located above the first TVS diode.
6. The method as claimed in claim 4 or 5, wherein the first epitaxial layer and the second epitaxial layer form a second P-N diode between the first buried layer and the second buried layer, the second P-N diode is provided with a well region and a semiconductor region of the same conductivity type as the second epitaxial layer, and each second P-N diode is also provided with an isolation trench.
7. The method of claim 4, wherein the step of forming the interface protection device further comprises the steps of: the isolation groove is filled with silicon dioxide through physical vapor deposition, and the groove depth of the isolation groove is larger than the sum of the thicknesses of the first epitaxial layer and the second epitaxial layer.
8. The method of claim 5, wherein the step of forming the interface protection device further comprises the steps of: the first well region and the second well region are formed through a push-in diffusion process, the temperature of the push-in diffusion process is 1000-1050 ℃, the push-in time is 50-75 minutes, and the junction depth of the second well region and the first well region is finally 2.5 +/-0.3 microns.
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