CN108933109A - 成角度的裸芯的半导体器件 - Google Patents

成角度的裸芯的半导体器件 Download PDF

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Publication number
CN108933109A
CN108933109A CN201710391000.2A CN201710391000A CN108933109A CN 108933109 A CN108933109 A CN 108933109A CN 201710391000 A CN201710391000 A CN 201710391000A CN 108933109 A CN108933109 A CN 108933109A
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Prior art keywords
semiconductor
bare chip
naked core
semiconductor bare
semiconductor devices
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CN201710391000.2A
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CN108933109B (zh
Inventor
邱进添
H.塔基亚
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SanDisk Information Technology Shanghai Co Ltd
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SanDisk Information Technology Shanghai Co Ltd
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Priority to CN201710391000.2A priority Critical patent/CN108933109B/zh
Priority to US15/623,598 priority patent/US10490529B2/en
Priority to KR1020180030302A priority patent/KR102033851B1/ko
Publication of CN108933109A publication Critical patent/CN108933109A/zh
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Abstract

公开了以一定角度安装在诸如印刷电路板的信号载体介质上的半导体器件。半导体器件包含以阶梯式偏移的配置堆叠的一叠半导体裸芯。然后裸芯堆叠体可以被包封在模塑体料中。然后模塑料可以通过沿着两个相对边缘的倾斜切割而分割。然后倾斜的边缘可以钻孔，以暴露在每个半导体裸芯上的电接触。然后倾斜的边缘可以被定位抵靠在具有焊料或者其它导电凸块的印刷电路板上，以便导电凸块与钻孔中的半导体裸芯电接触接合。然后该器件可以被加热回流并将电接触连接至导电凸块。

Description

成角度的裸芯的半导体器件
背景技术
便携式消费电子产品需求的强劲增长推动了对大容量存储设备的需求。非易失性半导体存储器器件，例如闪存存储卡，广泛用于满足对数字信息存储和交换的日益增长的需求。其便携性、多功能性和坚固耐用的设计，连同其高可靠性和大容量，使得这种存储器器件非常适用于各种各样的电子设备，包括，例如，数码相机、数字音乐播放器、视频游戏机、掌上电脑和蜂窝电话。
虽然已知有许多不同的封装配置，闪存存储卡限定通常被制造为系统级封装(SiP)或多芯片模块(MCM)，在这种情形中，多个裸芯被安装并互连于小面积的基板上。基板可以通常包含坚硬的电介质基底，该基底具有在一侧或双侧被蚀刻的导电层。在裸芯和(多个)导电层之间形成电连接，并且(多个)导电层提供电引线结构用以将裸芯连接至主机设备。一旦裸芯与基板之间的电连接建立，然后组装体典型地被包封在提供保护性封装体的模塑料中。
众所周知，将半导体裸芯上下叠置，以便最有效地使用封装足印。为了提供到半导体裸芯上接合垫的路径，裸芯以要么在相邻裸芯之间使用间隔层彼此完全重叠的方式，要么以阶梯式偏移的方式被堆叠。在阶梯式偏移的配置中，裸芯堆叠在另一个裸芯的顶部，以便使较低的裸芯的裸芯接合垫被暴露。这允许在每个级别的半导体裸芯的裸芯接合垫上形成引线键合体。
随着半导体裸芯变得更薄，并且为了增加半导体封装体中的存储器容量，半导体封装体中堆叠的裸芯数目持续增加。但是，这可以导致从上部的裸芯向下至基板的长的接合线。长的接合线容易被损坏或与其它的引线键合体电性短路，而且比更短的引线键合体具有更低的信噪比。此外，封装体中半导体裸芯数目的变大可以不利地影响良率。
发明内容
总之，本技术的示例涉及一种半导体器件，包括：多个半导体裸芯，该多个半导体裸芯一起安装成阶梯式、偏移的堆叠体，该多个半导体裸芯中的每个半导体裸芯包括多个电接触；和包封多个半导体裸芯的模塑料，该模塑料具有第一主表面和前缘，该前缘与主表面形成非垂直角度，并且多个电接触暴露在前缘处。
在其它示例中，本技术涉及一种半导体器件，包括：多个半导体裸芯，该多个半导体裸芯一起安装成阶梯式、偏移的堆叠体，该多个半导体裸芯中的每个半导体裸芯包括多个裸芯接合垫；形成在多个裸芯接合垫上的多个导电凸块；和包封多个半导体裸芯的模塑料，该模塑料具有第一主表面和前缘，该前缘与主表面形成非垂直角度，并且多个导电凸块暴露在前缘处。
在另一个示例中，本技术涉及一种半导体组装体，包括：单个信号载体介质；和半导体器件，该半导体器件包括：多个半导体裸芯，该多个半导体裸芯一起安装成阶梯式、偏移的堆叠体，该多个半导体裸芯中的每个半导体裸芯包含多个电接触；和包封多个半导体裸芯的模塑料，该模塑料具有第一主表面和前缘，该前缘与主表面形成非垂直角度，并且多个电接触暴露在前缘处，其中半导体器件的前缘被邻近于信号载体介质安装，以在一定角度将半导体器件安装至信号载体介质，所述角度由前缘对于模塑料的第一主表面所形成的角度来限定。
在另一个示例中，本技术涉及一种形成半导体器件的方法，包括(a)在多个半导体裸芯上形成电接触；(b)以阶梯式、偏移的配置堆叠多个半导体裸芯；(c)在保护涂层中包封半导体裸芯的堆叠体；(d)以与涂层的其他表面为非垂直的角度来切割保护涂层的边缘；以及(e)在保护涂层的非垂直角度的边缘上暴露多个电接触。
在另一个示例中，本技术涉及一种半导体器件，包括：多个半导体裸芯，该多个半导体裸芯一起安装成阶梯式、偏移的堆叠体，该多个半导体裸芯中的每个半导体裸芯包含电接触装置，用于将电压传递到多个半导体裸芯，并且从多个半导体裸芯传递电压；包封装置，用于包封多个半导体裸芯，该包封装置包括以一定角度使半导体器件能够固定至信号载体装置的成角度装置；和用于通过包封装置使电压能够从电接触装置传递至信号载体装置的装置。
附图说明
图1是根据本技术的实施例，形成半导体裸芯的流程图。
图2是半导体晶片的前视图，示出了晶片的第一主表面。
图3是来自晶片的单个半导体裸芯的透视图。
图4是堆叠在载体上的一组半导体裸芯的侧视图。
图5是堆叠在载体上并且包括导电凸块的一组半导体裸芯的侧视图，该导电凸块形成在半导体裸芯的裸芯接合垫上。
图6是堆叠在载体上并且包括导电凸块的一组半导体裸芯的透视图，该导电凸块形成在半导体裸芯的裸芯接合垫上。
图7是半导体器件的侧视图，该半导体器件包封在保护性涂层(诸如模塑料)中。
图8是根据本技术的实施例用成角度的前缘和后缘分割的包封的半导体器件的侧视图。
图9是根据本技术的实施例的包封的半导体器件的侧视图，该半导体器件具有在成角度的前缘中钻出的孔，以暴露半导体裸芯上的电接触。
图10是根据本技术的实施例的完整半导体器件的侧视图。
图11是根据本技术的实施例的半导体器件的侧视图，该半导体器件被安装在信号载体介质上。
图12是根据本技术的实施例的完整半导体组装体的侧视图。
图13是根据本技术的实施例的完整半导体组装体的侧视图，该半导体组装体还包括底部填充层。
图14是根据本技术的实施例的完整半导体组装体的侧视图，该半导体组装体还包括外部包封体。
具体实施方式
本技术将通过参考实施例中的附图进行描述，本技术涉及一种半导体器件，该半导体器件以一定角度安装在诸如印刷电路板(PCB)的介质上。半导体器件包括以阶梯式偏移配置堆叠的一叠半导体裸芯。然后，裸芯堆叠体可以被包封在一块模塑料中。然后，模塑料可以通过沿着两个相对边缘的倾斜切割进行分割。然后，其中一个倾斜的边缘可以被钻孔，以暴露在每个半导体裸芯上的电接触。然后，被钻孔的倾斜的边缘可以被定位在具有焊料或者其它导电凸块的印刷电路板上，以便导电凸块与钻孔中的半导体裸芯电接触接合。然后，器件可以被加热回流并且将电接触连接至导电凸块。
本技术提供了若干优点。直接将半导体裸芯导电凸块粘贴至PCB板的方法提供了相对于引线键合的半导体器件更为改进的电连接和增加的良率。此外，与半导体裸芯在其边缘处垂直堆叠的实施例相比，在PCB上提供成角度连接的裸芯堆叠体减少了裸芯堆叠体的高度。
可以理解的是，本技术可以以许多不同的形式实现，并且不应被解释为限于在此阐述的实施例。当然，提供这些实施例，为的是使本公开彻底且全面，并且将该技术充分地传达给本领域技术人员。的确，该技术旨在涵盖这些实施例的替代、修改和等同物，其包含在由所附权利要求所限定的技术的范围和精神内。此外，在本技术的以下具体描述中，大量特定的细节被提出，以便提供对本技术彻底的理解。但是，对本领域技术人员显而易见的是，本技术在没有这些特定的细节时是可以实现的。
本文所用的术语“顶部的”和“底部的”，“上部的”和“下部的”以及“垂直的”和“水平的”和它们的各种形式，只作示例和说明的目的，并不意味着限定本技术的描述，因为提及的项目可以在位置和方向上交换。并且，这里所用的术语“大体上”和/或“大约”的意思是，指定的尺寸或参数在给定应用的可接受制造公差内是可以变化的。在一个实施例中，可接受制造公差为±.25％。
本技术的实施例将参考图1的流程图和图2-14的视图进行说明。首先参考图1的流程图，半导体晶片100开始可以为晶片材料的晶锭，该晶锭可以在步骤200中形成。在一个示例中，形成晶片100的晶锭可以是根据切克劳斯基(Czochralski，CZ)或浮动区(floatingzone，FZ)工艺而生长的单晶硅。但是，在其它实施例中，晶片100可以由其他材料或通过其他工艺形成。
在步骤204中，半导体晶片100可以从晶锭中切割，并且在第一主表面102(图2)和与表面102相对的第二主表面104都进行抛光，以提供光滑的表面。在步骤206中，第一主表面102可以经历不同处理步骤，用以把晶片100分成相应的半导体裸芯106，并且在第一主表面102上和第一主表面102中形成相应的半导体裸芯106的集成电路。这些各种处理步骤可以包含金属化步骤，该步骤沉积金属接触，用于给集成电路传递信号和从集成电路传递信号。电接触可以包含暴露在第一主表面102上的裸芯接合垫108(其中一个裸芯接合垫在图2和图3中进行编号)。接合垫108的数目被简化示出，并且每个裸芯106可以包含比示出的更多的裸芯接合垫。
在实施例中，每个裸芯接合垫108可以具有接近70微米的长度和宽度，然而在其它实施例中，长度和宽度可以相互等比例或不等比例地改变。在实施例中，裸芯接合垫108可以由铝或其合金形成，但是在其它实施例中，接合垫108可以由其他材料形成。在实施例中，集成电路可以作为非易失性NAND闪存半导体裸芯，然而可以预期其它类型的集成电路。
裸芯接合垫108可以从边缘110向内隔开，例如15微米的距离。在其它实施例中，裸芯接合垫108可以完全地延伸至边缘110处。裸芯接合垫108可以通过穿过裸芯接合垫108的切割将半导体裸芯106切片、并在边缘110处将裸芯接合垫的端部留下而在边缘处形成。在其它实施例中，裸芯接合垫108可以使用再分布层延伸至边缘110处，该再分布层形成从裸芯接合垫108延伸至边缘110的电迹线。
在步骤210中，晶片可以在晶片100的第二主表面104上经过减薄工艺，用以使晶片从例如775微米减薄至大约25至100微米的范围。可以理解的是，在其它实施例中，晶片110在减薄步骤后，可以比该范围更薄或者更厚。在步骤214中，一层裸芯贴附膜(DAF)可以被施加到晶片100的第二主表面104。作为一个示例，DAF层可以是来自总部位于日本的NittoDenko公司的EM760L2-P。
DAF层可以具有3至30微米的厚度，然而在其它实施例中，DAF层可以比3至30微米更薄或更厚。如下所述，一块堆叠的半导体裸芯(通过DAF层的厚度相互隔开)可以以一定角度安装在PCB上，以便每个裸芯上的裸芯接合垫与PCB上提供的焊球对齐。DAF层的厚度限定了堆叠的半导体裸芯之间的间隔，并且可以提供DAF的厚度，以确保每个裸芯间的间隔与PCB上每排焊球的间隔相匹配。
接下来在步骤216中，可以从晶片100将半导体裸芯106切片。在一个实施例中，晶片100可以使用隐形激光工艺被切片。晶片110可以被支撑在卡盘或者其他支撑表面(未示出)上，其中第一主表面102上的集成电路面向支撑表面并且第二主表面104背对支撑面。然后，激光可以发射脉冲激光束，该激光束具有通过晶片100的第二主表面传输的波长，例如在红外或远红外波段上。使用光学系统(例如包括一个或多个准直透镜)可以将脉冲激光束聚焦为晶片表面104下方的点。当激光束在焦点处达到功率密度峰值时，晶片吸收能量，并且在晶片表面下方产生精确定位孔。
激光可以沿着晶片100的切割线移动，并且在若干点处激活，以便在晶片的中间深度处(位于晶片的第一和第二主表面102、104之间)形成若干位置紧密的精确定位孔。精确定位孔的行和列限定了从晶片100中切割出的每个半导体裸芯106的最终形状。激光可以形成位于单个深度的单层精确定位孔，或位于多个深度的多层(二层或更多层)精确定位孔。精确定位孔可以在晶片中产生裂缝，该裂缝向第一和第二主表面102、104扩展，以完成将晶片切片。在其它实施例中，晶片100可以通过除了隐形激光之外的技术被切割。这些另外的切割技术包含刀片切割和水射流切割。
图3示出了完整的被切成片的半导体裸芯106，该半导体裸芯106包括与边缘110相邻的裸芯接合垫108。此外，为了易于理解，示出了裸芯接合垫108的数目，并且裸芯106可以包含比所示的更多的裸芯接合垫108。多个晶片100可以根据上述的步骤200-216进行制作。此后，如图4所示，在步骤218中，取放机器人可以从相同晶片或不同晶片中取出半导体裸芯106，并且以阶梯式、偏移的配置在载体114上堆叠半导体裸芯。包括裸芯接合垫108的边缘110可以沿着裸芯堆叠体116的公共侧面对齐。载体114可以由各种坚硬的、平面的材料形成，并且如下所述，不会形成成品半导体器件的一部分。
图4示出了在裸芯堆叠体116中的裸芯106-0、106-1、…、106-n。在裸芯堆叠体116中的半导体裸芯的数目可以在实施例中有所不同，包括例如2、4、8、16、32、64或128块半导体裸芯。在其它实施例中，可以在裸芯堆叠体116中有更多或其它数目的半导体裸芯。裸芯堆叠体116中的裸芯106可以通过在相应的裸芯106的表面104上的DAF层，相互粘合并且粘合至载体114。
根据本技术的方面，在步骤220中，导电凸块120可以粘贴至裸芯106的每个裸芯接合垫108，如图5和图6所示。导电凸块120可以通过不同的技术在裸芯接合垫108上形成，但是在一个示例中，导电凸块可以例如通过柱状凸块形成，在这种情形中，通过本来用于形成引线键合体的引线键合体劈刀(未示出)形成并沉积该凸块。在该实施例中，第一导电凸块可以在引线键合体劈刀中的线的尖端，通过电子火焰熄灭(EFO)形成熔融球而被沉积。然后，可以使用升高温度和超声波振荡将熔融球压到接触垫109上，并且将熔融球留下形成导电凸块120。在一个实施例中，可以使用超声频率120KHz，在20g的压力、145℃的温度下持续约12毫秒的条件下形成导电凸块120。该参数只是作为示例，并且在其它实施例中，每个参数可以不同。一旦导电凸块120被粘贴，引线键合体劈刀可以离开以断开引线并就地留下导电凸块120。
在实施例中，导电凸块120可以具有约30至70微米的直径，并且更特别地约为50微米，然而在其它实施例中，导电凸块120的直径可以大于或小于该值。在一个实施例中，导电凸块可以具有介于20至35微米的高度，并且更特别地约为25微米，然而在其他实施例中，导电凸块120的高度可以高于或低于该值。
导电凸块120可以由金或金的合金形成，然而在其它实施例中，其可以由其他金属形成，例如铜或焊料。在以上实施例中，导电凸块在裸芯从晶片上切割并堆叠后，于裸芯接合垫108上形成。在其它实施例中，导电凸块120可以在半导体裸芯106形成过程的柱状凸块形成工艺中，当裸芯仍然是半导体晶片100的一部分时，形成于裸芯接合垫上。在其它实施例中，导电凸块120可以在半导体裸芯堆叠成裸芯堆叠体116前，形成在单独的半导体裸芯上(图3)。
一旦导电凸块120在裸芯堆叠体116中的裸芯接合垫108上形成，裸芯堆叠体116可以在步骤222中被包封在模塑料中，如图7所示。裸芯堆叠体116可以放置于模具壳(未示出)中，该模具壳包括上部和下部的模具板。融化的模塑料130可以随后在例如压缩成型工艺中被注入模具壳中，以在保护性外壳中包封裸芯堆叠体116。模塑料130可以包含，例如固体环氧树脂、苯酚树脂、熔融二氧化硅、结晶二氧化硅、炭黑和/或金属氢氧化物。该模塑料可从，例如，总部均设于日本的Sumitomo公司和Kyocera公司获得。也可以考虑来自其他制造商的其他模塑料。根据其他已知工艺，包括薄膜自由流动(flow free thin，FFT)成型、转移成型或注射成型技术，可以应用模塑料。
为了获得规模经济，若干裸芯堆叠体116可以在载体114上同时地一起包封。在步骤226中，相应的包封的裸芯堆叠体相互被分割(切割)，以形成单独的包封的裸芯堆叠体，本文称为半导体器件140。根据本技术的方面，一个或者多个半导体器件140可以以一定角度安装在PCB上，如下所述。为了允许成角度的连接，使用成角度的或陡峭的切割，使相应的半导体器件140彼此分割。该特征在图8中示出。
模塑料130具有上表面130a，该上表面130a通常是水平的，并平行于载体114的上表面。根据本技术的方面，通过穿过模塑料倾斜切断可以分割相应的半导体器件140，该切割角度通常跟随半导体器件140中的裸芯106的阶梯式偏移的角度。在实施例中，该角度可以在30°和60°之间，并且更具体的约为45°。但是，可以理解的是，在其它实施例中，角度可以以一些其他小于30°和大于60°的非垂直角度形成。这样的角度可以在大于0°且小于90°的范围内。
第一成角度的切割限定了相邻导电凸块120的成角度的边缘，本文称为半导体器件140的前缘142。第二成角度的切割，大致或准确地平行于第一成角度的切割，限定与半导体裸芯106中不包括导电凸块120的端部相邻的成角度的边缘。该成角度的边缘本文称为半导体器件140的后缘144。限定后缘144的第二切割还可以限定第二半导体器件140(如图8虚线所示)的前缘。
该切割可以通过各种切割方法进行，包括，例如锯切、水射流切割、激光切割、水引导激光切割、干介质切割和金刚石涂层引线切割。在前缘142、后缘144间延伸的半导体器件140的两个边缘可以垂直于模塑料130的上表面130a。因此，半导体器件140可以具有六个表面，顶部表面、底部表面和两个边缘中的每个都彼此垂直并一起形成正方形或矩形。最后两个表面是倾斜的前缘和后缘142、144。
在步骤230中，半导体器件140在前缘144处穿过模塑料130钻孔，以暴露每个导电凸块，如图9所示。钻孔形成的孔148水平地穿过单个半导体裸芯106的裸芯接合垫，而且垂直地沿着半导体裸芯的堆叠体。孔可以通过钻孔、激光或其它成孔方法形成。在一个这样的其它实施例中，孔可以在光刻工艺中被蚀刻。在其它实施例中，可以想到的是，在包封步骤222过程中使用的上部的模具板包含在导电凸块顶部排列的指状物，当上部和下部的模具板放在一起时，指状物防止在指状物占据的空间中形成模塑料。因此，在包封步骤222后，孔148已经形成。在这样的实施例中，孔148可以可选地被喷气或其他方式清洁，以确保导电凸块在孔148的基底处暴露。
孔的直径足够大，以允许PCB(下文中解释)上的焊料凸块与导电凸块120直接接触。在一个实施例中，每个孔可以为25微米至50微米，但是该尺寸是作为示例的，并且在其它实施例中，可以变得高于或低于这个范围。可以想到的是，孔148被金属填充，最初以熔融的形式并且固化至B阶段，以便金属与前缘142的表面平齐。在一个示例中，这样的金属可以是焊料。
在步骤234中，相应的半导体器件140从载体114中移除，如图10所示。在步骤236中，一个或多个半导体器件140可以被陡峭地安装在PCB150上。特别地，半导体器件可以被旋转或定位，使得前缘142与PCB 150平行或相邻，如图11所示。PCB 150可以，例如，为高密度互连(HDI)PCB。在其他实施例中，可以使用其他信号载体介质，如其他PCB和各种基板。
PCB 150可以包含焊球152的图案。焊球的图案布置在若干排上(如图11的页面)。在实施例中，焊球152至少与在待安装于PCB 150上的一个或多个半导体器件140上的导电凸块一样多。焊球152还被布置成图案，以便与安装于PCB上的每个半导体器件140的前缘142上的孔148紧密配合。这些位置可以基于要被安装在PCB 150上的一个或多个半导体器件140的(多个)前缘上的导电凸块120和孔148的已知位置而决定。
使用各种技术，包含例如柱状凸块形成，焊球152可以以期望的图案被施加到PCB150。PCB 150可以进一步地包含电导体154，用于传递信号和其他电压至焊球152或从焊球152传递信号和其他电压。尽管焊球在图11中示出，可以理解的是，在其它实施例中，焊膏或其他导电接触可以用于取代焊球。焊球或其他导电接触可以充分在PCB 150的表面的上方延伸，以适应孔148，并与导电凸块120直接接触。
半导体器件140可以定位于PCB 150上，以便焊球152与导电凸块120直接接触。此后，在步骤240中，半导体器件140和PCB 150可以被加热回流导电凸块120和焊料152，以固化导电凸块和焊球至C阶段，并且在半导体器件140和PCB 150之间，形成安全的物理和电连接。工艺可以重复，以在PCB 150上安装附加的半导体器件，如图11所示。或者，在被包含的所有半导体器件在PCB 150上被定位后，可以进行回流工艺。
随着焊球和和导电凸块融化、彼此回流然后硬化，表面粘附力和毛细作用将确保在焊球152和导电凸块120之间的良好接触。但是，在其它实施例中，支架臂(未示出)可以在箭头A的方向，对半导体器件140运用轻的力量，以在回流过程中支撑器件140，并且将焊球152推向导电凸块120。
已完成的半导体组装体160如图12所示。组装体160示出了包含经由导电凸块120和焊球152粘贴至PCB150的一对半导体器件140。但是，已完成的半导体组装体160可以包含单个半导体组装体160，或者多于两个的半导体组装体160。在示例中，已完成的半导体组装体可以包含3、4、5、6、7、8或者更多的半导体器件140。
正如已经提到的，如图12所示的半导体组装体160的制造可以在步骤240的回流工艺之后完成。但是，在如图13所示的其它实施例中，环氧基树脂或其他树脂、聚合物或保护层156可以在PCB 150和半导体器件140之间的空间中应用于已连接的导电凸块/焊球。在底部填充的步骤244中，保护层156可以被注入(多个)半导体器件140和PCB150之间的空间中。保护层150可以在液态时被施加，然后硬化成为固态层。底部填充步骤保护了在每个导电凸块/焊球结合点处的电连接，并且进一步将半导体器件140固定在PCB150上。各种聚合物可以用作保护层156，但是在实施例中，其可以为来自Henkel公司的Hysol环氧树脂，该公司在美国加利福尼亚设有办事处。
代替保护层156，半导体组装体160可以在步骤240中，经历其它包封工艺，以在模塑料170中包封整个半导体组装体160。这样的实施例如图14所示。这样的包封步骤可以采用在最初包封步骤222中所使用的相同方法。
尽管未示出，附加的部件可以被安装于PCB150上。这样的附加的部件可以包括，例如，ASIC或其他控制器裸芯、DRAM或者其他随机存取存储器，或其他部件。PCB 150可以进一步包含无源元件，例如电阻器、电容器、电感器。
在半导体组装体160的制造后，在步骤248中，半导体组装体160可以进行最后阶段的测试。一个这样的测试可以是坠落试验，在这种情形中组装体160从高处落下，然后测试操作。另一个这样的测试可以是热循环测试，其中组装体160在高温(例如85℃或125℃)至低温(-40℃)之间循环多达1000次，然后测试操作。可以进行其他测试。裸芯106和/或半导体器件140可以在制造工艺中的更早阶段被测试，在组装成半导体组装体160之前和/或后，以及在回流前和/或在回流后。如果半导体裸芯被识别为有缺陷和无功能性的，通过半导体组装体160的系统级编程，该裸芯可以从半导体组装体160的操作中排除。
在上述实施例中，半导体器件140被包封，并且在安装至PCB 150之前，钻出孔148。在其它实施例中，可以想到的是，不具有模塑料130的半导体器件140(即刚堆叠的半导体裸芯106和导电凸块120)可以被安装至PCB 150。这样的实施例可以如上所述被制造，包含底部填充保护层156或者模塑料170(在该实施例中国，只应用了模塑料)。
在上述实施例中，半导体器件140包含在裸芯接合垫108上的导电凸块120，该导电凸块通过孔148暴露，以允许其与焊球152的直接连接。在其它实施例中，可以想到的是导电凸块120是可省略的。在这样的实施例中，会在模塑料130中形成孔148，以暴露在裸芯106上的裸芯接合垫108。在这样的实施例中，半导体器件140可以如上所述地安装至PCB 150上，但是在该实施例中，焊球152从PCB 150延伸至与裸芯接合垫108直接接触。如本文所使用的，半导体裸芯上的电接触可以指裸芯接合垫108和/或导电凸块120。
成角度的裸芯的半导体组装体160可以包括电子部件，该电子部件可以在主机设备中实现。根据本技术的成角度的裸芯的半导体组装体160提供了若干优点。例如，其以类似于传统的水平倒装芯片的方式贴附到PCB 150上的焊球(152)阵列。但是，在传统的水平倒装芯片能够将单个裸芯粘贴到焊球阵列的情形中，成角度的裸芯的半导体组装体160能够粘贴整块成角度的半导体裸芯。
此外，成角度的裸芯的半导体组装体160可以在不使用引线键合体的情况下，直接耦合到PCB。引线键合体增加了额外的费用及处理步骤。此外，键合到裸芯堆叠体中裸芯的引线限制了堆叠体中可提供的裸芯数目，因为随着堆叠体中的裸芯数量的增加，如噪声、电短路和寄生RLC的性能问题增加。在本技术中，组装体160中的每个裸芯直接粘贴于PCB，并且在不增加任何上述的性能问题的情况下，裸芯可以添加至块中。
此外，成角度的裸芯的半导体组装体160以最小的总体形状系数，提供了大量裸芯。在组装体中使半导体裸芯106成角度允许多个裸芯直接连接到PCB，同时减小关键高度尺寸。此外，阶梯式半导体裸芯106与半导体器件140的前缘142、后缘144所形成的角度可以依赖于制造需求而变化。在例如高度没有长度重要的情形中，裸芯和边缘142、144的角度可以增加，导致在组装体160中更高但是更短的半导体器件140。
为了说明和描述的目的，本技术的前面的详细描述已经呈现。其并不旨在将本技术详尽或限制于所公开的精确形式。根据上述教导的许多修改和变化是可以的。选择所描述的实施例是为了最好地解释本技术的原理及其实际应用，从而确保其他本领域的技术人员最好地利用各种实施例中的技术和适用于预期的特定用途的各种修改。本技术的范围由所附的权利要求限定。

Claims (29)

1.一种半导体器件，包括：
多个半导体裸芯，所述多个半导体裸芯一起安装成阶梯式、偏移的堆叠体，所述多个半导体裸芯中的每个半导体裸芯包括多个电接触；以及
模塑料，所述模塑料包封多个半导体裸芯，所述模塑料具有第一主表面和前缘，所述前缘与所述主表面形成非垂直的角度，并且所述多个电接触暴露在所述前缘处。
2.根据权利要求1所述的半导体器件，其中所述电接触包括裸芯接合垫，所述裸芯接合垫限定在多个所述半导体裸芯的表面中或表面上。
3.根据权利要求1所述的半导体器件，其中所述电接触包括形成在裸芯接合垫上的导电凸块，所述裸芯接合垫限定在所述多个半导体裸芯的表面中或表面上。
4.根据权利要求1所述的半导体器件，其中所述模塑料包含在所述模塑料中形成的孔，并且所述孔暴露出所述电接触。
5.根据权利要求1所述的半导体器件，其中所述半导体器件配置为；以大于0°且小于90°的角度安装至信号载体介质，所述角度由所述前缘对所述模塑料的所述第一主表面所形成的角度来限定。
6.根据权利要求1所述的半导体器件，其中所述前缘与所述第一主表面形成介于30°与60°之间的角度。
7.根据权利要求1所述的半导体器件，其中所述前缘与所述第一主表面形成45°的角度。
8.根据权利要求1所述的半导体器件，其中所述半导体裸芯包括非易失性存储器裸芯。
9.一种半导体器件，包括：
多个半导体裸芯，所述多个半导体裸芯一起安装成阶梯式、偏移的堆叠体，所述多个半导体裸芯中的每个半导体裸芯包含多个裸芯接合垫；
多个导电凸块，其在所述多个裸芯接合垫上形成；以及
模塑料，所述模塑料包封多个半导体裸芯，所述模塑料具有第一主表面和前缘，所述前缘与所述主表面形成非垂直的角度，并且所述多个导电凸块暴露在所述前缘处。
10.根据权利要求9所述的半导体器件，其中所述模塑料包含在所述模塑料中形成的孔，并且所述孔暴露出所述多个导电凸块。
11.根据权利要求10所述的半导体器件，其中在所述模塑料形成后，所述多个孔形成在所述模塑料中。
12.根据权利要求9所述的半导体器件，其中所述半导体器件配置为以大于0°并且小于90°的角度安装至信号载体介质，所述角度由所述前缘对所述模塑料的所述第一主表面所形成的角度来限定。
13.一种半导体组装体，包括：
信号载体介质；和
半导体器件，所述半导体器件包括：
多个半导体裸芯，所述多个半导体裸芯一起安装成阶梯式、偏移的堆叠体，所述多个半导体裸芯中的每个半导体裸芯包括多个电接触，以及
模塑料，所述模塑料包封所述多个半导体裸芯，所述模塑料具有第一主表面和前缘，所述前缘与所述主表面形成非垂直的角度，并且所述多个电接触暴露在所述前缘处，
其中所述半导体器件的所述前缘被相邻于所述信号载体介质安装，以在一定角度将所述半导体器件安装至所述信号载体介质，所述角度由所述前缘对所述模塑料的所述第一主表面所形成的角度来限定。
14.根据权利要求13所述的半导体组装体，其中所述信号载体介质包括印刷电路板。
15.根据权利要求13所述的半导体组装体，其中所述信号载体介质包括延伸至所述信号载体介质的表面上方的多个电性导电接触，所述电性导电接触与所述多个半导体裸芯紧密配合。
16.根据权利要求15所述的半导体组装体，其中所述电性导电接触包括焊球。
17.根据权利要求15所述的半导体组装体，其中所述电接触包括裸芯接合垫，所述裸芯接合垫限定在所述多个半导体裸芯的表面中或表面上。
18.根据权利要求15所述的半导体组装体，其中所述电接触包括在裸芯接合垫上形成的导电凸块，所述裸芯接合垫限定在所述多个半导体裸芯的表面中或表面上。
19.根据权利要求15所述的半导体组装体，其中所述电性导电接触被容纳在形成于模塑料中的孔内。
20.根据权利要求15所述的半导体组装体，其中所述半导体裸芯包括非易失性存储器裸芯。
21.根据权利要求13所述的半导体组装体，其中所述半导体器件以介于30°至60°之间的角度安装至所述信号载体介质。
22.根据权利要求13所述的半导体组装体，其中所述半导体器件以45°的角度安装至所述信号载体介质。
23.一种形成半导体器件的方法，包括以下步骤：
(a)在多个半导体裸芯上形成电接触；
(b)以阶梯式、偏移的配置来堆叠所述多个半导体裸芯；
(c)将所述半导体裸芯的堆叠体包封于保护涂层内；
(d)以相对所述涂层的其他表面为非垂直的角度切割所述保护涂层的边缘；以及
(e)在所述保护涂层的所述非垂直边缘处暴露所述多个电接触。
24.根据权利要求23所述的方法，其中在多个半导体裸芯上形成电接触的所述步骤(a)包括在所述多个电接触上形成裸芯接合垫的步骤。
25.根据权利要求23所述的方法，其中在多个半导体裸芯上形成电接触的所述步骤(a)包括在所述多个电接触的裸芯接合垫上形成导电凸块的步骤。
26.根据权利要求23所述的方法，其中在所述多个电接触的裸芯接合垫上形成导电凸块的所述步骤在堆叠所述多个半导体裸芯的所述步骤(b)之后进行。
27.根据权利要求23所述的方法，其中在所述保护涂层的所述非垂直边缘处暴露所述多个电接触的所述步骤(e)包括钻孔、激光和蚀刻入保护涂层中的一个步骤。
28.根据权利要求23所述的方法，其中在所述保护涂层的所述非垂直边缘处暴露所述多个电接触的所述步骤(e)包括在将所述半导体裸芯的堆叠体包封于保护涂层中的所述步骤(c)期间，在所述保护涂层中形成开口。
29.一种半导体器件，包括：
多个半导体裸芯，所述多个半导体裸芯一起安装成阶梯式、偏移的堆叠体，所述多个半导体裸芯中的每个半导体裸芯包括电接触装置，用于将电压传递到所述多个半导体裸芯，并且从所述多个半导体裸芯传递电压；
包封装置，用于包封所述多个半导体裸芯，所述包封装置包括使所述半导体器件能够以一定角度固定于信号载体装置的成角度装置；以及
用于使所述电压能够通过所述包封装置从所述电接触装置传递至所述信号载体装置的装置。
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