CN108874731A - Multi-chip lamina arithmetic unit, ideal money dig mine machine and computer server - Google Patents
Multi-chip lamina arithmetic unit, ideal money dig mine machine and computer server Download PDFInfo
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- CN108874731A CN108874731A CN201810853973.8A CN201810853973A CN108874731A CN 108874731 A CN108874731 A CN 108874731A CN 201810853973 A CN201810853973 A CN 201810853973A CN 108874731 A CN108874731 A CN 108874731A
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- chip
- pin
- lamina
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q40/00—Finance; Insurance; Tax strategies; Processing of corporate or income taxes
- G06Q40/04—Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
Abstract
A kind of multi-chip lamina arithmetic unit virtual digs mine machine and computer server, the multi-chip lamina arithmetic unit include：Multiple chips are arranged on single layer pcb board；Each chip includes that at least one mode select signal pin for controlling the function of chip pin switches over chip pin between at least two functions.At least one mode select signal pin is arranged to each chip in technical solution of the present invention, the function of chip pin can be made to be changed according to the difference of model selection, it is attached adjacent or similar chip nearby, the problems such as avoiding signal interference caused by cabling intersection, circuit extension, facilitate the connection between multiple chips, the difficulty of pcb board interconnection can be reduced, and reduces the cost of plate grade.
Description
Technical field
The present invention relates to integrated circuit fields, and in particular to a kind of multi-chip lamina arithmetic unit and its implementation,
Ideal money digs mine machine and computer server.
Background technique
In the operation board that one is made of multi-chip, interconnecting signal is numerous between each chip, is often routed to plate grade
Very big pressure is brought, the area that may result in pcb board increases or needs more numbers of plies to meet wiring requirements.Opposite
In long-pending and cost sensitivity system, it will limit the size and the plank number of plies of pcb board, very big difficulty carried out to wiring tape.
In the prior art, the PIN foot position of single chip is fixed, and when multicore sheet grade interconnects, is limited to plank
Width, the difficulty that the mutual joint conference of signal of communication becomes, for single layer pcb board, if there is intersecting between signal, plate grade signal
Cabling can become extremely difficult, and be easy to produce interference between each other.
Summary of the invention
To solve the above problems, the object of the present invention is to provide a kind of multi-chip lamina arithmetic unit and its realization sides
Method, ideal money dig mine machine and computer server, and the scheme that can be changed using chip pin input and output mode facilitates multiple cores
Connection between piece can reduce the difficulty of pcb board interconnection, and reduce the cost of plate grade.
To solve the above problems, the first aspect of the present invention provides a kind of multi-chip lamina arithmetic unit, including：It is more
A chip is arranged on single layer pcb board；
Each chip includes that at least one mode select signal pin for controlling the function of chip pin draws chip
Foot switches between at least two functions.
In some embodiments, when mode select signal changes, the function of the chip-side pin with it is another
The function of side pin is interchangeable.
In some embodiments, when mode select signal changes, the function of the chip-side pin with it is another
The function of side pin is interchangeable the function including part or all of pin and is interchangeable.
In some embodiments, when mode select signal changes, the input pin of the chip two sides becomes defeated
Pin out, output pin become input pin, i.e. the input of pin, outbound course is converted.
In some embodiments, the multiple chip includes N*M chip, is arranged in N row, M on the single layer pcb board
Column, wherein N, M are positive integer；The multiple serpentine-like signal of communication of chip is connected in series, i.e. communication above and below the chip at both ends
The signal of communication of signal connection, intermediate chip or so interconnects；The power supply signal of the multiple chip is according to each column
Chip is connected in series up and down.
The second aspect of the present invention provides a kind of implementation method of multi-chip lamina arithmetic unit, including：
The multi-chip lamina arithmetic unit includes N*M chip, and N row, M column are arranged on the single layer pcb board,
Wherein N, M are positive integer；
Each chip includes that at least one mode select signal pin for controlling the function of chip pin draws chip
Foot switches between at least two functions；
It is interconnected between adjacent chips.
In some embodiments, when mode select signal changes, the function of the chip-side pin with it is another
The function of side pin is interchangeable.
In some embodiments, when mode select signal changes, the function of the chip-side pin with it is another
The function of side pin is interchangeable the function including part or all of pin and is interchangeable.
In some embodiments, when mode select signal changes, the input pin of the chip two sides becomes defeated
Pin out, output pin become input pin, i.e. the input of pin, outbound course is converted.
In some embodiments, the serpentine-like signal of communication of the multiple chip is connected in series, i.e., above and below the chip at both ends
The signal of communication of signal of communication connection, intermediate chip or so interconnects；The power supply signal of the multiple chip according to
Each column chip is connected in series up and down.
The third aspect of the present invention provides a kind of ideal money digging mine machine, including foregoing multi-chip lamina fortune
Calculate device.
The fourth aspect of the present invention provides a kind of computer server, including foregoing multi-chip lamina operation
Device.
In conclusion the present invention provides a kind of multi-chip lamina arithmetic units and its implementation, ideal money to dig
Mine machine and computer server, the pcb board include：Multiple chips are arranged on single layer pcb board；Each chip includes at least
One mode select signal pin carries out chip pin between at least two functions for controlling the function of chip pin
Switching.At least one mode select signal pin is arranged to each chip in technical solution of the present invention, chip pin can be made
Function changes according to the difference of model selection, is attached adjacent or similar chip nearby, avoids cabling intersection, line
The problems such as signal interference caused by road extends, facilitate the connection between multiple chips, the difficulty of pcb board interconnection can be reduced, with
And reduce the cost of plate grade.
Detailed description of the invention
Fig. 1 is multi-chip lamina arithmetic unit attachment structure schematic diagram in the prior art；
Fig. 2 is multi-chip multi-layer PCB board attachment structure schematic diagram；
Fig. 3 is multi-chip lamina arithmetic unit attachment structure schematic diagram in the specific embodiment of the invention.
Specific embodiment
In order to make the objectives, technical solutions and advantages of the present invention clearer, With reference to embodiment and join
According to attached drawing, the present invention is described in more detail.It should be understood that these descriptions are merely illustrative, and it is not intended to limit this hair
Bright range.In addition, in the following description, descriptions of well-known structures and technologies are omitted, to avoid this is unnecessarily obscured
The concept of invention.
In the prior art, there is a kind of data processing equipment based on multi-chip lamina arithmetic unit, as shown in Figure 1,
Including the first chip 110 and the second chip 120 with different encapsulation, which has the first power end and second source end；
A plurality of metal foil F1~Fm+1 is laid on pcb board, a plurality of metal foil is by first power end and the second source end
Between voltage division be at least two voltage layers, and a plurality of metal foil divides to form electricity in the first surface of pcb board
Press at least two power supply areas successively to successively decrease；Pcb board is laid with signal routing, signal routing pcb board first surface by
The reciprocal loopback of layer is connected at least two power supply area；The kernel of first chip 110 and the second chip 120 power supply packaging pin is same
To arrangement, kernel power supply packaging pin is successively connected by a plurality of metal foil；The signal communication packaging pin of first chip 110
It powers compared to the arranged direction of kernel power supply packaging pin and the signal communication packaging pin of the second chip 120 compared to kernel
The arranged direction of packaging pin on the contrary, i.e. the first chip 110 signal communication packaging pin Sin [n:1] and Sout [n:1] with the
The signal communication packaging pin Sin [n of two chips 120:1] and Sout [n:1] contrary, and the first chip 110 and the second core
Piece 120 alternates setting.The signal communication packaging pin of first chip 110 and second chip 120 passes through described
Signal routing is successively connected.The chip layout method of above-mentioned pcb board can be arranged on single layer pcb board, and using less
To avoid with metal foil Fi+1 wiring interference occurs for wiring.But to reach said effect, it is defeated to need to be arranged simultaneously two kinds of inputs
The reversed chip of signal pins out increases the quantity and cost of manufacture of PCB chip in this way.
To solve the above problems, the present invention attempts the production demand for meeting multi-chip single layer PCB using identical chip.
The PIN foot position of single chip is fixed, and in the interconnection of multicore sheet grade, is limited to the width of plank, signal of communication it is mutual
The difficulty that joint conference becomes, for single layer pcb board, if there is intersecting between signal, plate grade signal lead can become extremely difficult.
As shown in Fig. 2, 4*3 chip CHIP-0, CHIP-1 ... CHIP-11 has been arranged on single layer pcb board, 1- is respectively represented
12 chips.It is assumed that chip is entirely identical, only different in the position where plate grade, communication PIN foot definition on pcb board
It is as follows：
On the left of chip：Pin 1：S0_UP is input signal；Pin 2：S1_UP is output signal；Pin 3：S2_UP is defeated
Enter signal；Pin 4：VDD_IO_UP is left side I O power supply；Pin 5：GP_IO_UP；Pin 6：VSS_UP is leftwards power supply.
On the right side of chip：Pin 7：S0_DN is output signal, pin 8：S1_DN is input signal, pin 9：S2_DN is defeated
Signal out；Pin 10：VDD_IO_DN is right side I O power supply；Pin 11：GP_IO_DN；Pin 12：VSS_DN is for right side electric
Source.
Wherein, the superior and the subordinate's chip by wiring 13 is powered power supply series connection in same row, and the chip of every a line supplies
Piezoelectric voltage is identical.If plate grade needs the signal of communication by 12 such chips to be cascaded, common signal connection type
As shown in Figure 2：The signal of CHIP-2 will walk farther away line and CHIP-3 and interconnect, the signal of CHIP-5 also to walk farther away line with
CHIP-6 interconnection, plate grade cabling intersect with power supply wiring 13, and multi-layer PCB board is needed just to be able to achieve.If CHIP-3 also has
Signal and CHIP-0 are interconnected, that also can only just can be with plate grade cost necessarily will increase with multi-layer PCB board.Therefore, the prior art
In, due to the pin function of chip be it is fixed, cause cabling relatively difficult, interfering with each other etc. between route easy to form is asked
Topic.
Further to solve the above problems, at least one mode select signal pin is arranged in present invention proposition on chip,
So that under different mode selection cases, the function of the PIN foot of chip be it is variable, such setting will be such that the interconnection of plate grade becomes
It is simple and easy.
The first aspect of the present invention provides a kind of multi-chip lamina arithmetic unit, including：Multiple chips are arranged in list
On layer pcb board.Specifically, the multiple chip includes N*M chip, N row, M column are arranged on the single layer pcb board,
Middle N, M are positive integer；Each chip includes that at least one mode select signal pin makes for controlling the function of chip pin
Chip pin switches between at least two functions.
In some embodiments, when mode select signal changes, the function of the chip-side pin with it is another
The function of side pin is interchangeable.
In some embodiments, when mode select signal changes, the function of the chip-side pin with it is another
The function of side pin is interchangeable the function including part or all of pin and is interchangeable.
In some embodiments, when mode select signal changes, the input pin of the chip two sides becomes defeated
Pin out, output pin become input pin, i.e., input, outbound course are converted.
In some embodiments, the serpentine-like series connection of the multiple chip, the i.e. chip at both ends are mutually connected two-by-two up and down
It connects, intermediate chip or so connection.
Another aspect provides a kind of implementation methods of multi-chip lamina arithmetic unit, according to above-mentioned PCB
The setting of plate carries out connection, specifically, by increasing a mode select signal：MODE uses it to control chip PIN foot
Definition and input and output direction, convenient for plate grade interconnection when adjust as needed some chip PIN foot definition.
It is illustrated below with a specific embodiment.As shown in Figure 3：4*3 have been arranged on single layer pcb board
Chip CHIP-0, CHIP-1 ... CHIP-11, respectively represents 1-12 chips.It is assumed that on pcb board chip be entirely it is identical,
Only different in the position where plate grade, communication PIN foot is defined as follows：
On the left of chip：Pin 1：S0_UP is input signal；Pin 2：S1_UP is output signal；Pin 3：S2_UP is defeated
Enter signal；Pin 4：VDD_IO_UP is left side I O power supply；Pin 5：MODE_UP is mode control signal；Pin 6：VSS_UP is
Leftwards power supply.
On the right side of chip：Pin 7：S0_DN is output signal, pin 8：S1_DN is input signal, pin 9：S2_DN is defeated
Signal out；Pin 10：VDD_IO_DN is right side I O power supply；Pin 11：MODE_DN is mode control signal；Pin 12：VSS_
DN for right side power supply.
Be arranged on every chips at least one mode select signal pin MODE (above-mentioned pin 5 and pin 11 can including
Portion is connected to a mode select signal and uses；Or the pin in pin 5MODE_UP control left side, pin 11MODE_DN control
Make the pin on right side)：
When MODE is selected as 0：Pin function is not as it appears from the above, change；
When MODE is 1：The function of pin 1-6 is corresponding with the function of pin 7-12 on the right side of chip mutual respectively on the left of chip
It changes.
Above-mentioned is the case where function of left and right sides pin is all interchangeable.
In some embodiments, only the function of the input and output pin of chip is interchangeable, the function of other pins is not
Become：
When MODE is selected as 0：
On the left of chip：Pin 1：S0_UP is input signal；Pin 2：S1_UP is output signal；Pin 3：S2_UP is defeated
Enter signal；
On the right side of chip：Pin 7：S0_DN is output signal, pin 8：S1_DN is input signal, pin 9：S3_DN is defeated
Signal out.
When MODE is selected as 1：
On the left of chip：Pin 1：S0_UP is output signal；Pin 2：S1_UP is input signal；Pin 3：S2_UP is defeated
Signal out；
On the right side of chip：Pin 7：S0_DN is input signal, pin 8：S1_DN is output signal, pin 9：S3_DN is defeated
Enter signal.
The definition of chip PIN foot is controlled by MODE signal, CHIP-2 need not be interconnected with remote CHIP-3 again, and can be with
It is interconnected nearby with CHIP-5, CHIP-3 can be interconnected with CHIP-6 nearby, have signal and CHIP-0 to interconnect CHIP-3, also complete
It is complete unaffected.As it can be seen that the multiple chip can choose the serpentine-like series connection of signal of communication, i.e., above and below the chip at both ends
Signal of communication interconnects two-by-two, the signal of communication connection of intermediate chip or so；The power supply signal of the multiple chip
It is connected in series up and down according to each column chip.It is not necessarily to according to first in the both ends chip and the last one chip of the order of connection
It is vertically connected with the signal of communication of other chips.
The third aspect of the present invention provides a kind of ideal money digging mine machine, including foregoing multi-chip lamina fortune
Calculate device.
The fourth aspect of the present invention provides a kind of computer server, including foregoing multi-chip lamina operation
Device.
In this way, can arbitrarily change the input and output direction of chip PIN foot by MODE signal, single chip is only needed, without
It is that every kind of chip provides two opposite chips of pin as shown in figure 1, so that it may so that system is easily realized interconnection on single layer pcb board,
One can reduce the difficulty of pcb board interconnection, and two, which carry out lamina, can also reduce the cost of plate grade.
In conclusion the present invention provides a kind of multi-chip lamina arithmetic units and its implementation, ideal money to dig
Mine machine and computer server, the pcb board include：Multiple chips are arranged on single layer pcb board；Each chip includes at least
One mode select signal pin carries out chip pin between at least two functions for controlling the function of chip pin
Switching.At least one mode select signal pin is arranged to each chip in technical solution of the present invention, chip pin can be made
Function changes according to the difference of model selection, is attached adjacent or similar chip nearby, avoids cabling intersection, line
The problems such as signal interference caused by road extends, facilitate the connection between multiple chips, the difficulty of pcb board interconnection can be reduced, with
And reduce the cost of plate grade.
It should be understood that above-mentioned specific embodiment of the invention is used only for exemplary illustration or explains of the invention
Principle, but not to limit the present invention.Therefore, that is done without departing from the spirit and scope of the present invention is any
Modification, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.In addition, appended claims purport of the present invention
Covering the whole variations fallen into attached claim scope and boundary or this range and the equivalent form on boundary and is repairing
Change example.
Claims (12)
1. a kind of multi-chip lamina arithmetic unit, which is characterized in that including：Multiple chips are arranged on single layer pcb board；
Each chip includes that at least one mode select signal pin for controlling the function of chip pin makes chip pin exist
It is switched between at least two functions.
2. multi-chip lamina arithmetic unit according to claim 1, which is characterized in that when mode select signal becomes
When change, the function of the chip-side pin and the function of other side pin are interchangeable.
3. multi-chip lamina arithmetic unit according to claim 2, which is characterized in that when mode select signal becomes
When change, the function of the chip-side pin and the function of other side pin are interchangeable the function including part or all of pin
It is interchangeable.
4. multi-chip lamina arithmetic unit according to claim 3, which is characterized in that when mode select signal becomes
When change, the input pin of the chip two sides becomes output pin, and output pin becomes input pin, i.e. the input of pin, defeated
Direction is converted out.
5. multi-chip lamina arithmetic unit according to claim 1-4, which is characterized in that the multiple chip
Including N*M chip, N row, M column are arranged on the single layer pcb board, wherein N, M are positive integer；The multiple chip is in snake
Shape signal of communication is connected in series, i.e., the signal of communication above and below the chip at both ends interconnects two-by-two, intermediate chip or so leads to
Believe that signal interconnects；The power supply signal of the multiple chip is connected in series up and down according to each column chip.
6. a kind of implementation method of multi-chip lamina arithmetic unit, which is characterized in that including：
The multi-chip lamina arithmetic unit includes N*M chip, and N row, M column are arranged on the single layer pcb board, wherein
N, M is positive integer；
Each chip includes that at least one mode select signal pin for controlling the function of chip pin makes chip pin exist
It is switched between at least two functions；
It is interconnected between adjacent chips.
7. the implementation method of multi-chip lamina arithmetic unit according to claim 6, which is characterized in that work as model selection
When signal changes, the function of the chip-side pin and the function of other side pin are interchangeable.
8. the implementation method of multi-chip lamina arithmetic unit according to claim 7, which is characterized in that work as model selection
When signal changes, the function of the chip-side pin and the function of other side pin are interchangeable including part or all of
The function of pin is interchangeable.
9. the implementation method of multi-chip lamina arithmetic unit according to claim 8, which is characterized in that work as model selection
When signal changes, the input pin of the chip two sides becomes output pin, and output pin becomes input pin, i.e. pin
Input, outbound course converted.
10. according to the implementation method of the described in any item multi-chip lamina arithmetic units of claim 6-9, which is characterized in that
The multiple serpentine-like signal of communication of chip is connected in series, i.e., the signal of communication connection above and below the chip at both ends, intermediate chip
The signal of communication of left and right interconnects；The power supply signal of the multiple chip is connected in series up and down according to each column chip.
11. a kind of ideal money digs mine machine, which is characterized in that including multi-chip single layer as described in any one in claim 1-5
Plate arithmetic unit.
12. a kind of computer server, which is characterized in that including multi-chip lamina as described in any one in claim 1-5
Arithmetic unit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010647996.0A CN111797053A (en) | 2018-07-30 | 2018-07-30 | Multi-chip arithmetic device, virtual currency mining machine and computer server |
| CN201810853973.8A CN108874731A (en) | 2018-07-30 | 2018-07-30 | Multi-chip lamina arithmetic unit, ideal money dig mine machine and computer server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810853973.8A CN108874731A (en) | 2018-07-30 | 2018-07-30 | Multi-chip lamina arithmetic unit, ideal money dig mine machine and computer server |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010647996.0A Division CN111797053A (en) | 2018-07-30 | 2018-07-30 | Multi-chip arithmetic device, virtual currency mining machine and computer server |
Publications (1)
| Publication Number | Publication Date |
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| CN108874731A true CN108874731A (en) | 2018-11-23 |
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| CN201810853973.8A Pending CN108874731A (en) | 2018-07-30 | 2018-07-30 | Multi-chip lamina arithmetic unit, ideal money dig mine machine and computer server |
| CN202010647996.0A Pending CN111797053A (en) | 2018-07-30 | 2018-07-30 | Multi-chip arithmetic device, virtual currency mining machine and computer server |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010647996.0A Pending CN111797053A (en) | 2018-07-30 | 2018-07-30 | Multi-chip arithmetic device, virtual currency mining machine and computer server |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109992081A (en) * | 2019-04-04 | 2019-07-09 | 杭州嘉楠耘智信息科技有限公司 | Computing device and computer server |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112286123A (en) * | 2020-12-24 | 2021-01-29 | 武汉精测电子集团股份有限公司 | Bidirectional GPIO control method, signal generator and test equipment |
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| CN1198028A (en) * | 1997-04-30 | 1998-11-04 | 三菱电机株式会社 | Semiconductor device |
| JP2000188720A (en) * | 1998-12-21 | 2000-07-04 | Toshiba Corp | Driver for solid-state image pickup element |
| CN105045364A (en) * | 2015-07-21 | 2015-11-11 | 北京比特大陆科技有限公司 | Serial power supply circuit, virtual digital coin mining machine and computer server |
| US20160328338A1 (en) * | 2015-05-08 | 2016-11-10 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Signal switching circuit and jbod system having the signal switching circuit |
| CN207531168U (en) * | 2017-12-05 | 2018-06-22 | 深圳比特微电子科技有限公司 | Data processing equipment and ideal money dig ore deposit machine and computer server |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3623762B2 (en) * | 2001-08-20 | 2005-02-23 | エルピーダメモリ株式会社 | Semiconductor device |
| CN108040418A (en) * | 2017-12-05 | 2018-05-15 | 深圳比特微电子科技有限公司 | Data processing equipment and ideal money dig ore deposit machine and computer server |
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- 2018-07-30 CN CN201810853973.8A patent/CN108874731A/en active Pending
- 2018-07-30 CN CN202010647996.0A patent/CN111797053A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1198028A (en) * | 1997-04-30 | 1998-11-04 | 三菱电机株式会社 | Semiconductor device |
| JP2000188720A (en) * | 1998-12-21 | 2000-07-04 | Toshiba Corp | Driver for solid-state image pickup element |
| US20160328338A1 (en) * | 2015-05-08 | 2016-11-10 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Signal switching circuit and jbod system having the signal switching circuit |
| CN105045364A (en) * | 2015-07-21 | 2015-11-11 | 北京比特大陆科技有限公司 | Serial power supply circuit, virtual digital coin mining machine and computer server |
| CN207531168U (en) * | 2017-12-05 | 2018-06-22 | 深圳比特微电子科技有限公司 | Data processing equipment and ideal money dig ore deposit machine and computer server |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109992081A (en) * | 2019-04-04 | 2019-07-09 | 杭州嘉楠耘智信息科技有限公司 | Computing device and computer server |
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| CN111797053A (en) | 2020-10-20 |
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