JPH0357245A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To effectively utilize a chip area by a method wherein, when several kinds of power-supply trunk lines are arranged and installed inside a predetermined power-supply trunk line region, kinds of the power-supply trunk lines and widths of the power-supply trunk lines are decided according to a user's specifications. CONSTITUTION:A semiconductor chip 1 is partitioned into an inside region 2 and an outside region, an input/output buffer 3 is arranged in the outside region; a power-supply trunk line region which is connected to an I/O cell is formed in a position traversing the buffer; outside pads 4 are formed at an edge of the chip 1. A ground trunk line for output use of a TTL I/O cell is not arranged and installed in a formation region of power-supply trunk lines; a ground trunk line 5, a power-supply trunk line 6 of the cell, a Vcc power- supply trunk line 7 and a Vee power-supply trunk line 8 are arranged and installed there. A trunk-line width of the trunk line 5 is set at two times or higher of individual trunk-line widths; kinds of trunk lines and individual widths of the power-supply trunk lines 5, 6, 7, 8 are decided respectively according to a user's specifications. Thereby, a wasteful interconnection region is eliminated and a chip area can be utilized effectively.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applied to a method of manufacturing a semiconductor device comprising a plurality of I/O cells and several types of power main lines connected to these I/O cells. 6 [Prior Art] Gate array For semi-custom type semiconductor devices such as, after performing master processes such as gate forming process, diffusion layer forming process, and insulating film forming process, contact hole forming process, wiring layer forming process, etc. are performed according to user specifications. A semiconductor device is obtained by performing a slicing process such as a through hole forming process. In the above slicing process,
In addition to the process of forming wiring into wiring channels in internal areas,
There is a process of arranging several types of power main lines in the external area. FIG. 4 is a diagram showing an example of a technique for arranging a power main line in this external area.

In the figure, reference numeral 1 indicates a semiconductor chip, 2 indicates an internal region formed in the semiconductor chip 1, and 3 indicated by a broken line indicates a large number of cells arranged in an array (horizontal direction in Fig. 4). The human output buffer, which is shaped by
(including 4a, 4b, and 4c) each indicate a large number of external pads provided along the edge of the semiconductor chip 1, and the external pads 4 and the above-mentioned I/O cells correspond to each other in a 1:1 ratio. It is located.

For the master chip configured in this way, the above I/
The process of arranging the power main line connected to the O cell will be described below.

The formation area of the power supply main line connected to the ■/○ cells is predetermined, and in a gate array type semiconductor device, the area is determined to be approximately at a position crossing above the input/output buffer 3. The number of power supply main lines and their widths are also determined in advance, so that the power supply main lines can be arranged without much regard to user specifications. When a power supply main line is formed by patterning using the resist mask, it becomes as shown in FIG. 4, and a fixed number of power supply main lines and a fixed width are obtained.

The semiconductor device in FIG. 4 is a semiconductor device with a mixed ECL/TTL interface, and code O is an ECLI/TTL interface
The ground main line for the output of the O cell, 11 is TTLI/○
The ground main lines for the output of the cells are shown respectively, and 6
indicates, for example, a power supply main line of a driver system I/O cell. As mentioned above, the ground trunk 10 for the output of the ECLI/O cell, and the ground trunk H for the output of the TTLI/○ cell.
The main line widths of L1 and driver system I/O cell power supply main g6 are the same, and between main lines 10 and 1l,
The distances between them are also the same. Here, in FIG. 4, only the three power supply main lines 10 and 11.6L are not shown to avoid complicating the diagram, but in reality, other power supply lines such as Vc c, Vee, and Vss A trunk line is also installed. After arranging the power supply trunks 1i10, 11, 6, etc. in this way, connect the power supply trunks 10, 11.6 to the ECL ground power supply pad 4a. TTL ground power supply pad 4b. Wiring layers 20, 21, and 22 shown by hatching for connection to the driver power supply pad 4C are formed, and the semiconductor device shown in FIG. 4 is obtained.

[Problems to be Solved by the Invention] However, the above method for manufacturing a semiconductor device has the following problems.

In other words, if the TTLI/O cell is not used according to user specifications, the ground main line l1 for the output of the TTL I/O cell will be completely wasted.
There is a problem that the chip area cannot be used effectively.

In addition, if the number of TTLI/O cells and ECLI/O cells used is unbalanced due to user specifications, for example, the width of the main line is fixed as described above, so the optimal There is a problem that it is not possible to change the main line width, for example, if it is an output ground main line, the inductance of the output ground main line that is used more often will not change, but the current consumption will increase. There is a problem in that the noise of the output ground main line becomes large, and the increase in noise limits the number of I/O cells that can be switched simultaneously. Here, depending on user specifications, for example, if only one of the ECL I/O cells and TTLI/O cells is used, the ground trunk line for the output of the unused one is also set as the ground trunk line of the used one, while the ECLI/ O cell and TTL
When both I/O cells are used, use each as a ground trunk line with the determined trunk line width as before,
This eliminates wasted ground lines when only one of the CLI/O cells and TTLI/O cells is used, allowing effective use of the chip area, and also provides a large number of ground power supply pads to improve the use of I/O cells. If there is an imbalance in the number of ground power pads,
○ Connect the output ground main line of the cell that is used more often to reduce noise, and by this noise reduction, the I/O
Although it is possible to increase the number of O cells that can be switched simultaneously, the problem is that if only one of the ECLI/○ cells and TTLI/O cells is used, the area between the power main lines will still be wasted. There is a point, ■/
If the number of cells used is uneven, there is a problem that even if a large number of grounding power supply pads are provided, the number is limited and it cannot be expected to be very effective.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that is equipped with a power supply main line that is optimal for user specifications and that makes effective use of chip area.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, when arranging the several types of power supply lines within a predetermined power supply line area of a semiconductor device that includes a plurality of ■/○ cells and several types of power supply lines connected to these I/O cells, , the type of power supply main line and the width of this power supply main line are determined according to user specifications.

[Operation] According to the above-mentioned means, when several types of power supply main lines are arranged within a predetermined power supply main area, the type of power supply main line and the width of this power supply main line are determined according to user specifications. Therefore, power supply trunks that are not required can be laid out without being laid out, while those that are needed can be laid out with the required trunk width, and the wiring can be This can be done within a predetermined FL source trunk area without wasting area at all, thereby achieving the above-mentioned purpose of providing a power supply trunk that is optimal to the user's specifications and effectively utilizing the chip area. That will happen.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the main parts of a semiconductor device obtained by applying an embodiment of the method for manufacturing a semiconductor device according to the present invention.

The semiconductor device of this embodiment is a semi-custom type semiconductor device configured with a gate array. In this semiconductor device, a semiconductor chip 1 is divided into an internal region 2 and an external region. is a large number of ■ indicated by dashed lines.
/○ An input/output buffer 3 formed by arranging cells in an array (in the left-right direction in the construction drawing) is arranged, and a position crossing above this buffer 3 is connected to an I/O cell. This area is defined as a formation area for a power supply main line, and a large number of external pads 4 are provided along the edge of the semiconductor chip 1 in one-to-one correspondence with the I/O cells.

In this embodiment, the ground main line for the output of the TTLI/O cell described in the prior art is not arranged in the region where the power supply main line is formed, but the ground main line for the output of the ECLI/O cell is not provided. Main line 5, driver system work/○ cell power supply main line 6, Vcc [source main line 7, V e e power supply main line 8, etc. are installed, and driver system I/O cell power supply main line 6
, the VCC power supply trunk line 7, and the Vee power supply trunk line 8 are said to have the same width, but the width of the trunk a of the ground trunk line 5 for the output of the ECLI/O cell is more than twice the width of each of the above-mentioned trunk lines. There is. Types of the above power supply trunks and this power supply trunk RIA5, 6
, 7, and 8 are determined according to user specifications (details will be described later).

Next, a manufacturing process for a semiconductor device having the above structure will be briefly described.

The master chip, which has been subjected to master processes such as a gate formation process, a diffusion layer formation process, and an amorphous film formation process, is sent to a slicing process. In this slicing process, contact hole forming process, wiring layer forming process, through hole forming process, etc. are performed according to user specifications, but at this time, several types of power supply main lines are arranged in the external area mentioned above. The process is carried out.

In this step, the type of power main line and the width of this power main line are determined according to user specifications.

In the user specifications in this example, ECLI/○
A large number of cells are used, but no TTLI/O cells are used. Therefore, there is no need to provide a ground trunk for the output of the TTLI/O cell, which was provided in the prior art, and the ground trunk, t25, and other required power supply trunks for the output of the ECLI/O cell are not required. , that is, the width of the main power supply line m of the driver system I/O cell power supply main line 6, VCC power supply main line 7, Vee power supply main line 8, etc. is determined.

In this embodiment, the widths of the other required power supply main lines 6, 7, and 8 are the same because there is no problem from a functional point of view, and for the same reason as in the prior art, they are the same. However, the ground trunk line 5 for the output of the ECLI/○ cells has a wide trunk line width because the number of ECLI/O cells used is large and an increase in noise is expected.

As shown in FIG. 2, the ground trunk for the output of this ECLI/O cell [5] is located at the lower end of the ground trunk for the output of the ECLI/O cell used in the prior art, 110 in the diagram. This is done by completely filling the area from the top of the ground line 11 for the output of the TTLI/○ cell to the upper end in the figure with aluminum or the like using a resist mask.

In this way, in this embodiment, depending on the user specifications, the power supply main line for the output ground main line of the TTLI/O cell that is not required is connected to llI[! However, for the ground trunk line 5 for the output of the ECLI/O cell and other power supply trunk lines 6, 7, and 8, which are required,
Since the power trunk lines 5, 6, and 7.8 are provided with the required trunk IIA@, it is possible to arrange the power trunk line that is most suitable for the user's specifications.

Moreover, in the arrangement of the ground trunk line 5 for the output of the ECLI/O cell, the ground trunk line 10
and 1l can also be used as the ground main line 5 for the output of the ECLI/○ cell, eliminating the wasted installation area that previously occurred and making it possible to effectively utilize the chip area. It has become.

In addition, in this embodiment, as mentioned above, the E
Although the number of CLI/O cells is large and noise is expected to increase,
The width of the ground trunk 15 for the output of the ECLI/○ cells is widened to reduce noise, making it possible to increase the number of simultaneous switching of the ■/○ cells. ing.

After the above-mentioned power supply trunk arrangement process is completed, the power supply trunk 1g5.6 etc. is connected to the power supply pads 4a and 4 for ECL ground.
(a) Wiring lines M20, 20.22 shown by hatching for connection to the driver power supply pad 4C are formed, and a semiconductor device in an An state different from the power main line shown in FIG. 2 is obtained.

Note that in this embodiment, the EC is wider than the conventional one:
The ground main line 5 for the output of the LI/O cell is connected as a conventional TTL ground power supply pad 4b + JECL ground power supply pad 4a in addition to the conventionally used ECL ground power supply pad 4a, so that the ECLI/
○ Further efforts have been made to reduce noise in the ground trunk LA5 for cell output.

FIG. 3 shows the main parts of a semiconductor device obtained by applying another embodiment of the method for manufacturing a semiconductor device according to the present invention. The difference between the semiconductor device of this embodiment and the previous embodiment 9 is that the user specifications include ECLI/○ cell and TTLI/
Since both O cells are used, there are . Ground trunk $i5a for output of ECLr/O cell and ground trunk 1 for output of TTLI/O cell
The point is that both the iA5b and the iA5b are installed together,
Moreover, in this embodiment, the number of cells used for both the ECLI/○ cells is uneven (in this embodiment,
The main difference is that the width of the ground trunk line for the output of the cell that is used more often is wider. In this embodiment, the trunk line width of the output ground trunk lines 5a and 5b is determined according to the ratio of the numbers of ECLI/O cells and TTLI/O cells, and
For example, if the ratio of the number of TLI/O cells is 5:2, the width of the ground trunk lines 5a and 5b is also 5:2.
It is determined to be 2.

In this way, also in this embodiment, the required power supply mains IIA 5a, 5b, 6, 7 .
Regarding 8, the power supply main lines 5a, 5b, 6, and 7.8 are arranged with the required main line width, so that it is possible to arrange the power supply main line that is most suitable for the user's specifications. ing.

Moreover, in this embodiment, as mentioned above, the trunk line width of the ground trunk lines 5a and 5b is equal to that of the ECL'I/O cell and TTL.
The width of the main line is determined according to the ratio of the number of I/O cells, that is, the width of the main line that is used more often is widened according to that ratio, and the width of the main line that is used less is made wider according to that ratio. Since it is narrow, it is possible to reduce noise that increases in proportion to the number of cells used, and therefore it is possible to increase the number of I/O cells that can be switched simultaneously.

Furthermore, the power supply mains tiA5a, 5b, 6, 7.8 are arranged within the predetermined power supply mainline area (positions that cross above the input/output buffer 3) without wasting any area. This makes it possible to effectively utilize the chip area. In addition, the ground trunk for the output of the above ECLI/○ cell! ! 5a is particularly susceptible to noise generation due to large fluctuations in the current value of the emitter follower transistor, so the main line width should be determined with this in mind.
It is also possible to make the output ground main line width of the ECLI/O cells somewhat wider, which is determined from the ratio of the number of I/O cells.

According to the method of manufacturing a semiconductor device in each of the above embodiments, the following main effects can be obtained.

That is, when arranging several types of Ml source trunk lines within a predetermined power trunk area (positions that cross above the input/output buffer 3), the type of power trunk line and the width of this power trunk line are determined according to user specifications. I decided to do this, so
Power supply trunks that are not required can be laid out without being laid out, while required power supply trunks can be laid out with the required width, and the layout can be determined in advance. This function allows the power supply to be carried out without wasting any area within the main power line area (the area M that crosses above the traffic buffer 3), which is ideal for the user's specifications. It becomes possible to provide a source trunk line, and moreover, it becomes possible to effectively utilize the chip area.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the above embodiment, only an example of application to a semiconductor device constituted by a gate array is described, but this embodiment is applicable to all semi-custom type semiconductor devices.

In the above embodiment, the power supply main line, the type and width of which is determined according to the user specifications, is connected to the ground main line 15a for the output of the ECLI/O cell from the standpoint of noise reduction. T
Although only the ground trunk 1i5b is used for the output of the TLI/O cell, the present invention can be similarly applied to other power supply trunks.

Furthermore, in the above embodiment, the trunk line position and trunk line width determined by the prior art are utilized as much as possible, that is, the power supply trunk vA6 of the driver system I/O cell,
vCC power main line7. The main line position and main line width of the Veeffi source main line 8, etc. are the same as those of the conventional technology, and the ground main line 5 for the output of the ECLI/O cell is also the same as that of the EC:LI/O cell used in the conventional technology. TTLI/O from the lower end in the diagram of the output ground main line 10
The position of the main line in the prior art is utilized by filling the entire ground line 11 for cell output up to the upper end in the diagram with aluminum etc. using a resist mask, but the position of the main line and the width of the main line are There is no need to be bound by the conventional technology at all, and the position and width of the main line may be determined in any way as long as it is within a predetermined area of the power supply main line.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in a semiconductor device including a plurality of cells/cells and several types of power supply lines connected to these cells/cells, when arranging the several types of power supply lines within a predetermined power line area, Since the type of power supply main line and the width of this power supply main line are determined according to the user specifications, power supply main lines that are not required are not installed, while necessary power supply main lines are not installed. Trunk H. required for the power supply trunk line. It is possible to arrange the power supply with @, and the arrangement can be done within a predetermined power main line area without wasting any area.

As a result, it is possible to provide a power supply line that is optimal to the user's specifications, and it is also possible to effectively utilize the chip area.

[Brief explanation of drawings]

FIG. 1 is a plan view of the main parts of a semiconductor device obtained by applying an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a diagram for explaining the process of forming a power main line in the same embodiment. , FIG. 3 is a plan view of the main parts of a semiconductor device obtained by applying another embodiment of the semiconductor device manufacturing method according to the present invention, and FIG. 4 is a plan view of the main part of a semiconductor device obtained by applying the semiconductor device manufacturing method according to the prior art. FIG. 3 ----Multiple I/O cells, 5.5a, 5b, 6,
7, 8...Power main line.

Claims (1)

[Claims] 1. A semiconductor device comprising a plurality of I/O cells and several types of power main lines connected to these I/O cells,
A semiconductor device characterized in that, in arranging the several types of power supply main lines within a predetermined power supply main line area, the type of the power supply main line and the width of this power supply main line are determined according to user specifications. Production method. 2. A patent claim characterized in that the type of the power main line and the width of the power main line are determined according to the type of I/O cells used and the ratio of the number of I/O cells of the type. The manufacturing method according to item 1. 3. The manufacturing method according to claim 1 or 2, wherein the power main line whose type and width are determined according to the user specifications is an output ground main line.