CN108831840A - Paper base wiring method again between a kind of disk - Google Patents
Paper base wiring method again between a kind of disk Download PDFInfo
- Publication number
- CN108831840A CN108831840A CN201810503374.3A CN201810503374A CN108831840A CN 108831840 A CN108831840 A CN 108831840A CN 201810503374 A CN201810503374 A CN 201810503374A CN 108831840 A CN108831840 A CN 108831840A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- paper
- paper base
- wiring method
- metal pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
Abstract
The invention discloses a kind of wiring methods again of paper base between disk.1) dielectric layer deposited on silicon wafer, in dielectric layer upper opening；2) dielectric layer opening plating metal pad；3) it is smeared on paper with water solubility pencil and forms pattern, then mounted on the dielectric layer with metal pad；4) dielectric layer deposited, and photoetching aperture again；5) paper base sacrificial layer is destroyed using micro-wave oven, and fills conductive filler 6) implantation soldered ball.The present invention, as sacrificial layer, and using nanometer silver paste as conductive filler, is avoided the micro Process means of the valuableness such as conventional splash-proofing sputtering metal layer, reduces processing cost using paper.
Description
Technical field
The invention belongs to microelectromechanical systems, paper base wiring method again between specially a kind of disk.
Background technique
Be routed again be wafer level packaging critical process step.Usually, IC chip and external electrical connection are to use
The mode of metal lead wire bonding connect the i/o (input port, output port) on chip with package carrier and encapsulated pin
Come what is realized.In this mode, the I/O in IC chip is typically distributed on periphery.But with IC chip characteristic size
Reduce the expansion of sum aggregate on a large scale, the spacing between pin constantly reduces, quantity constantly increases.When the reduction of I/O spacing, lead key
Conjunction technology is just no longer applicable in, it is necessary to seek new technological approaches.In order to solve this problem, wafer level packaging is used and is routed again
Technology.
Redistribution technology refers on IC, and each chip is pressed to the area I/O Zhao Huang of circumferential distribution, passes through wiring layer again
(Redistribution Layer, RDL) is transformed into the handful area in array distribution area or other desired distribution figure and most end form
At the technology of solder bump.However, the process is more complicated (such as needs to use metal sputtering work for existing wiring technique again at present
Skill), higher cost.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of wiring methods again of paper base between disk
Technical scheme is as follows：
Wiring method includes the following steps paper base again between a kind of disk：
1) dielectric layer deposited on silicon wafer, in dielectric layer upper opening；
2) dielectric layer opening plating metal pad；
3) wiring pattern being smeared again on paper with water solubility pencil and obtaining paper base sacrificial layer, then attachment is to metal welding
On the dielectric layer of disk；
4) dielectric layer deposited again, and in obtained dielectric layer upper opening；
5) it is destroyed on paper using microwave and is coated with again the part of wiring pattern, and be partially filled with conductive filler in destruction；
6) soldered ball is implanted into step 4) photoetching tapping.
Common paper is difficult to absorb microwave, is smeared on paper with water-soluble pencil and forms pattern, which can absorb
Microwave, and then destroy the part (sacrificial layer) of picture case on paper.And specifically draw the (wiring of sacrificial layer of which type of pattern
Journey), then it is to be determined according to the design of chip and placement.
Preferably, the conductive filler of the step 5) is nanometer silver paste.
Preferably, the dielectric layer of the step 1) is silica dioxide medium layer, with a thickness of 0.8-1.2 μm.
Preferably, the opening mode in the step 1) and step 4) is that opening is etched by the way of deep etching
As metal pad window.
Preferably, the dielectric layer of the step 4) is silica dioxide medium layer, with a thickness of 0.5 μm.
Compared with prior art, the present invention possessed have the beneficial effect that：Using paper as sacrificial layer, and utilize nano silver
Slurry is used as conductive filler, avoids the micro Process means of the valuableness such as conventional splash-proofing sputtering metal layer, reduces processing cost.
Detailed description of the invention
Fig. 1 is that dielectric layer schematic diagram is arranged in silicon chip surface；
Fig. 2 is dielectric layer opening plating metal pad schematic diagram；
Fig. 3 is attachment paper base schematic diagram；
Fig. 4 is dielectric layer deposited schematic diagram on paper base；
Fig. 5 is filling conductive filler schematic diagram；
Fig. 6 is implantation soldered ball schematic diagram.
Fig. 7 is wire structures schematic diagram again in typical case WLP.
Specific embodiment
The invention discloses a kind of wiring methods again of paper base between disk, and its step are as follows：
Wiring method includes the following steps paper base again between a kind of disk：
1) dielectric layer deposited on silicon wafer, in dielectric layer upper opening；
2) dielectric layer opening plating metal pad；
3) wiring pattern being smeared again on paper with water solubility pencil and obtaining paper base sacrificial layer, then attachment is to metal welding
On the dielectric layer of disk；
4) dielectric layer deposited again, and in obtained dielectric layer upper opening；
5) it is destroyed on paper using microwave and is coated with again the part of wiring pattern, and be partially filled with conductive filler in destruction；
6) soldered ball is implanted into step 4) photoetching tapping.
In one particular embodiment of the present invention, the conductive filler of the step 5) is nanometer silver paste.
In one particular embodiment of the present invention, the dielectric layer of the step 1) is silica dioxide medium layer, thickness
It is 0.8-1.2 μm.
In one particular embodiment of the present invention, the opening mode in the step 1) and step 4) is using deep
The mode of etching etches opening as metal pad window.
In one particular embodiment of the present invention, the dielectric layer of the step 4) is silica dioxide medium layer, thickness
It is 0.5 μm.
The present invention utilizes the characteristic of paper, and using paper as sacrificial layer, common paper is difficult to absorb microwave, with water solubility
Pencil is smeared on paper and forms pattern, which can absorb microwave, and then destroy the part (sacrificial layer) of picture case on paper,
The micro Process means for avoiding the valuableness such as conventional splash-proofing sputtering metal layer, reduce processing cost.
And specifically draw which type of pattern (wiring process of sacrificial layer), then being will be according to the design of chip, and lays
Position determines.
In a specific implementation case of the invention, process is specific as follows：
1) with the mode of the dry dry oxygen of oxygen-wet oxygen-, the dielectric layer for being about 1 μm in grown above silicon a layer thickness, photoetching is adopted
Metal pad window is etched with the mode of deep etching, as shown in Figure 1.
2) metal pad is made by the way of plating, as shown in Figure 2
3) formation wiring pattern again is smeared on paper with water-soluble pencil, then attachment to the dielectric layer with metal pad
On, as shown in Figure 3；
4) 0.5 μm of silica dioxide medium layer, photoetching, using depth are grown at low ambient temperatures using technique for atomic layer deposition
The mode of etching etches exposed metal pad window, as shown in Figure 4；
5) paper base sacrificial layer is destroyed using microwave (such as micro-wave oven), is cleaned using acetone after removing residue, fills nanometer
Silver paste conductive filler simultaneously solidifies, as shown in Figure 5
6) at exposed metal pad window, metal soldered ball is made, as shown in Figure 6.
Water-soluble pencil is also referred to as, and water-soluble colored pencil belongs to one of colored pencil.During the embodiment of the present invention
The dry dry oxygen of oxygen-wet oxygen-mode -- drying -- dry-oxygen oxidation -- wet-oxygen oxidation -- dry-oxygen oxidation-oxidation that refers to Wafer Cleaning
The process of completion；Photoetching is a main technique in planar ransistor and integrated circuit production, is to semiconductor wafer table
The shelter (such as silica) in face carries out aperture.Atomic layer deposition is by the way that vaporous precursors pulse is alternately passed through reaction
Device simultaneously chemisorption and reacts and is formed a kind of method of deposition film on depositing base.Above-mentioned technology is normal in this field
With technology, and nanometer silver paste is material commonly used in the art.
If Fig. 7 is wire structures schematic diagram again in typical case WLP, compared with prior art, the present invention uses paper as sacrificial layer,
And using nanometer silver paste as conductive filler, the micro Process means of the valuableness such as conventional splash-proofing sputtering metal layer, and the present invention are avoided
It is easy to operate, reduce processing cost.
Claims (5)
1. paper base wiring method again between a kind of disk, it is characterised in that include the following steps：
1) dielectric layer deposited on silicon wafer, in dielectric layer upper opening；
2) dielectric layer opening plating metal pad；
3) wiring pattern being smeared again on paper with water solubility pencil and obtaining paper base sacrificial layer, then attachment is arrived with metal pad
On dielectric layer；
4) dielectric layer deposited again, and in obtained dielectric layer upper opening；
5) it is destroyed on paper using microwave and is coated with again the part of wiring pattern, and be partially filled with conductive filler in destruction；
6) soldered ball is implanted into step 4) photoetching tapping.
2. paper base wiring method again between disk according to claim 1, it is characterised in that the conduction of the step 5) is filled out
Material is nanometer silver paste.
3. paper base wiring method again between disk according to claim 1, it is characterised in that the dielectric layer of the step 1)
For silica dioxide medium layer, with a thickness of 0.8-1.2 μm.
4. paper base wiring method again between disk according to claim 1, it is characterised in that the step 1) and step 4)
In opening mode be that opening is etched by the way of deep etching as metal pad window.
5. paper base wiring method again between disk according to claim 1, it is characterised in that the dielectric layer of the step 4)
For silica dioxide medium layer, with a thickness of 0.5 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810503374.3A CN108831840B (en) | 2018-05-23 | 2018-05-23 | Paper base wiring method again between a kind of disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810503374.3A CN108831840B (en) | 2018-05-23 | 2018-05-23 | Paper base wiring method again between a kind of disk |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108831840A true CN108831840A (en) | 2018-11-16 |
| CN108831840B CN108831840B (en) | 2019-11-19 |
Family
ID=64148611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810503374.3A Expired - Fee Related CN108831840B (en) | 2018-05-23 | 2018-05-23 | Paper base wiring method again between a kind of disk |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108831840B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6180265B1 (en) * | 1997-06-27 | 2001-01-30 | Delco Electronics Corporation | Flip chip solder bump pad |
| JP2002344132A (en) * | 2001-05-15 | 2002-11-29 | Daisho Denshi:Kk | Manufacturing method of printed board |
| CN101197339A (en) * | 2006-12-08 | 2008-06-11 | 日月光半导体制造股份有限公司 | Soldered ball redistribution connecting structure |
| CN102833954A (en) * | 2012-08-27 | 2012-12-19 | 中国科学院理化技术研究所 | Pressure-sensitive adhesive printed circuit forming method |
-
2018
- 2018-05-23 CN CN201810503374.3A patent/CN108831840B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6180265B1 (en) * | 1997-06-27 | 2001-01-30 | Delco Electronics Corporation | Flip chip solder bump pad |
| JP2002344132A (en) * | 2001-05-15 | 2002-11-29 | Daisho Denshi:Kk | Manufacturing method of printed board |
| CN101197339A (en) * | 2006-12-08 | 2008-06-11 | 日月光半导体制造股份有限公司 | Soldered ball redistribution connecting structure |
| CN102833954A (en) * | 2012-08-27 | 2012-12-19 | 中国科学院理化技术研究所 | Pressure-sensitive adhesive printed circuit forming method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108831840B (en) | 2019-11-19 |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20191119 Termination date: 20200523 |
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| CF01 | Termination of patent right due to non-payment of annual fee |