CN108831395B - Display device and shift register circuit - Google Patents

Abstract

The present disclosure provides a display device and a shift register circuit thereof, the shift register circuit including a plurality of stages of shift registers, wherein any one of the stages of shift registers includes the following modules. And the input module inputs the input stage transmission signal to the boosting node. The pull-up module outputs a first pull-up signal to the boost node, and pulls up the voltage signal from a first level to a second level. And the output module is used for coupling and pulling up the voltage signal from the second level to a third level according to the clock signal and outputting a grid scanning signal through the output end. When the pulse of the clock signal is finished, the pull-up module outputs a second pull-up signal to the boost node to maintain the voltage signal at a second level. And the feedback module receives the feedback signal and pulls down the voltage signal and the grid scanning signal to a preset low level.

Description

Display device and shift register circuit

Technical Field

The present application relates to the field of display panel technology, and more particularly to a display device with an array substrate gate driving circuit and a shift register circuit thereof.

Background

In recent years, Liquid Crystal Displays (LCDs) have been widely used because of their advantages of clear and precise images, flat Display, thin thickness, light weight, no radiation, low power consumption, low operating voltage, and the like. An exemplary liquid crystal display is mainly implemented by a Gate Driver chip (Gate Driver 1C) when performing Gate driving. Since the gate driving chip needs to be connected to the display Panel (Panel) through a connector and a plurality of gate driving chips need to be used in one liquid crystal display, the manufacturing cost of the liquid crystal display is still high.

With the development of new technologies, many liquid crystal display panels have adopted Gate driver Array (GOA) technology to replace external Gate driver chips. The grid driving technology of the array substrate is to directly manufacture a grid driving integrated circuit on the surface of an active switch array substrate through the process of exposure and development, thereby saving an external grid driving chip. The array substrate gate driving technology can greatly reduce the product cost from the aspects of both material cost and process steps, and can further reduce the power consumption of the liquid crystal display panel.

A typical gate driving circuit of an array substrate has multiple stages of shift registers, and when each shift register scans and drives a gate signal line, a gate voltage point of each shift register receives a precharge signal, and the gate voltage point is precharged, so that the voltage of the point reaches a high voltage level under the action of a clock signal, and then a Thin-Film Transistor (TFT) for controlling output is turned on, and a signal is smoothly transmitted, thereby driving the gate signal line of a panel. Therefore, for the shift register of the substrate gate driving circuit, it is necessary to stably and accurately output the gate driving signal so as not to generate malfunction to cause noise, thereby affecting the image quality of the display.

Disclosure of Invention

The present invention provides a display device and a shift register circuit thereof, which can accurately and smoothly output a gate scan signal and improve the tailing phenomenon of the gate scan signal, thereby improving the image quality of the display device.

The present disclosure provides a shift register circuit including a plurality of stages of shift registers, wherein any one of the stages of shift registers includes: the input module inputs a stage transmission signal of the preceding stage shift register to a boosting node so as to increase a voltage signal Qn of the boosting node to a first level; the pull-up module outputs a first pull-up signal to the voltage boost node, and pulls up the voltage signal Qn from the first level to a second level; the output module receives a clock signal CKn and couples and pulls up the voltage signal Qn from the second level to a third level according to the clock signal CKn, the output module is controlled by the coupled voltage signal Qn and outputs a gate scanning signal through an output end, and when the pulse of the clock signal CKn is finished, the pull-up module outputs a second pull-up signal to the boost node to maintain the voltage signal Qn at the second level; and the feedback module receives a feedback signal and pulls down the voltage signal Qn and the grid scanning signal after the coupling of the boosting node to a preset low level.

In one embodiment, the nth stage shift register further includes a sub pull-down module for maintaining the voltage signal Qn at the predetermined low level; and a sub pull-down control module for controlling the operation of the sub pull-down module.

In one embodiment, the sub-pull-down module is electrically coupled to the boost node, the gate scan signal and the preset low potential.

In an embodiment, the output module includes a first switch, a control terminal of the first switch is electrically coupled to the boost node, a first terminal of the first switch is configured to receive the clock signal CKn, and a second terminal of the first switch is electrically coupled to the output terminal for outputting the gate scan signal, wherein when the voltage signal Qn of the boost node is coupled to the third level, the first switch is turned on and outputs the gate scan signal.

In an embodiment, the input module includes a second switch, a control terminal of the second switch is electrically coupled to a first terminal of the second switch, and a second terminal of the second switch is configured to output the stage transmission signal.

In one embodiment, the feedback module includes a third switch having a control terminal electrically coupled to a feedback signal, a first terminal electrically coupled to the output terminal, and a second terminal electrically coupled to the predetermined low level, wherein the third switch is turned on in response to the feedback signal to turn on the first terminal and the second terminal of the third switch to pull down the gate scan signal to the predetermined low level.

In one embodiment, the feedback module includes a fourth switch having a control terminal electrically coupled to the feedback signal, a first terminal electrically coupled to the boost node, and a second terminal electrically coupled to the predetermined low level, wherein the fourth switch is turned on in response to the feedback signal to turn on the first terminal and the second terminal of the fourth switch, so as to pull down the voltage signal Qn to the predetermined low level.

In one embodiment, the pull-up module comprises a fifth switch, a control end of which is electrically coupled to the clock signal CK (n-1) of the shift register of the previous stage, and a first end of which is electrically coupled to the clock signal CK (n-2) of the shift register of the previous stage, wherein the fifth switch is turned on in response to the clock signal CK (n-1) of the shift register of the previous stage, turns on the first end and a second end of the fifth switch, and transmits the clock signal CK (n-2) of the shift register of the previous stage to the second end of the fifth switch; a sixth switch, a control terminal of the sixth switch is electrically coupled to the voltage signal Q (n-1) of the previous stage shift register, a first terminal of the sixth switch is electrically coupled to the second terminal of the fifth switch, and a second terminal of the sixth switch is electrically coupled to the boost node, wherein the sixth switch is turned on in response to the voltage signal Q (n-1) of the previous stage shift register, turns on the first terminal and the second terminal of the sixth switch, and outputs the first pull-up signal to the boost node.

In one embodiment, the pull-up module includes a seventh switch, a control terminal of which is electrically coupled to the clock signal CK (n +1) of the next stage shift register, a first terminal of which is electrically coupled to the clock signal CK (n +2) of the next stage shift register, wherein the seventh switch is turned on in response to the clock signal CK (n +1) of the next stage shift register, and conducts the first terminal and a second terminal of the seventh switch to transmit the clock signal CK (n +2) of the next stage shift register to the second terminal of the seventh switch; and an eighth switch, a control terminal of the eighth switch being electrically coupled to the voltage signal Q (n +1) of the next shift register, a first terminal of the eighth switch being electrically coupled to the second terminal of the seventh switch, a second terminal of the eighth switch being electrically coupled to the voltage boost node, wherein the eighth switch is turned on in response to the voltage signal Q (n +1) of the next shift register, turns on the first terminal and the second terminal of the eighth switch, and outputs the second pull-up signal to the voltage boost node.

In an embodiment, the second terminal of the sixth switch is electrically coupled to the second terminal of the eighth switch.

In one embodiment, the pull-up module outputs the first pull-up signal under the control of the voltage signal Q (n-1) of the previous stage shift register, and outputs the second pull-up signal under the control of the voltage signal Q (n +1) of the next stage shift register.

In one embodiment, the pull-up module outputs the first pull-up signal according to a clock signal CK (n-1) of a shift register of a previous stage, pulls up the voltage signal Qn from the first level to the second level, and outputs the second pull-up signal according to a clock signal CK (n +2) of a shift register of a next stage, so that the voltage signal Qn is maintained at the second level.

In one embodiment, the input module inputs the stage signal to the boost node according to a clock signal CK (n-2) of a shift register of a previous stage to increase the voltage signal Qn of the boost node to the first level.

The present application provides a display device, which includes an active switch array substrate and an opposite substrate, disposed opposite to the active switch array substrate, wherein an array substrate gate driving circuit is fabricated on the active switch array substrate, and the array substrate gate driving circuit includes the shift register circuit in the above embodiments, wherein the shift register circuit includes an input module for inputting a stage signal of a preceding stage shift register to a voltage boost node and pulling up a voltage signal of the voltage boost node to a first level; the pull-up module outputs a first pull-up signal to the voltage boost node, pulls up the voltage signal from the first level to a second level, and outputs a second pull-up signal to the voltage boost node to maintain the voltage signal at the second level; the output module receives a clock signal and couples and pulls up the voltage signal from the second level to a third level according to the clock signal, the output module is controlled by the coupled voltage signal and outputs a grid scanning signal through an output end, and when a pulse of the clock signal is ended, the pull-up module outputs the second pull-up signal to the voltage boost node to maintain the voltage signal at the second level; and the feedback module is used for receiving a feedback signal and pulling down the voltage signal and the grid scanning signal after the voltage boost node is coupled to a preset low level.

In an embodiment, the output module includes a first switch, a control terminal of the first switch is electrically coupled to the boost node, a first terminal of the first switch is configured to receive the clock signal, and a second terminal of the first switch is electrically coupled to the output terminal for outputting the gate scan signal, wherein when the voltage signal coupling of the boost node is increased to the third level, the first switch is turned on and outputs the gate scan signal.

In an embodiment, the input module includes a second switch, a control terminal of the second switch is electrically coupled to a first terminal of the second switch, and a second terminal of the second switch is configured to output the stage transmission signal.

In one embodiment, the pull-up module includes a fifth switch, a control terminal of which is electrically coupled to the clock signal of the previous stage shift register, and a first terminal of which is electrically coupled to the clock signal of the previous stage shift register, wherein the fifth switch is turned on in response to the clock signal of the previous stage shift register, turns on the first terminal and a second terminal of the fifth switch, and transmits the clock signal of the previous stage shift register to the second terminal of the fifth switch; and a sixth switch, a control terminal of the sixth switch being electrically coupled to the voltage signal of the previous stage shift register, a first terminal of the sixth switch being electrically coupled to the second terminal of the fifth switch, and a second terminal of the sixth switch being electrically coupled to the voltage boost node, wherein the sixth switch is turned on in response to the voltage signal of the previous stage shift register, turns on the first terminal and the second terminal of the sixth switch, and outputs the first pull-up signal to the voltage boost node.

In one embodiment, the pull-up module comprises a seventh switch, a control terminal of which is electrically coupled to a clock signal of a next-stage shift register, and a first terminal of which is electrically coupled to a clock signal of a next-stage shift register, wherein the seventh switch is turned on in response to the clock signal of the next-stage shift register, so as to conduct the first terminal and a second terminal of the seventh switch, and transmit the clock signal of the next-stage shift register to the second terminal of the seventh switch; and an eighth switch, a control terminal of the eighth switch being electrically coupled to the voltage signal of the next shift register, a first terminal of the eighth switch being electrically coupled to the second terminal of the seventh switch, a second terminal of the eighth switch being electrically coupled to the voltage boost node, wherein the eighth switch is turned on in response to the voltage signal of the next shift register, turns on the first terminal and the second terminal of the eighth switch, and outputs the second pull-up signal to the voltage boost node.

In one embodiment, the pull-up module outputs the first pull-up signal under the control of a voltage signal of a previous stage shift register, and outputs the second pull-up signal under the control of a voltage signal of a next stage shift register.

In one embodiment, the pull-up module outputs the first pull-up signal according to a clock signal of a previous stage shift register, pulls up the voltage signal from the first level to the second level, and outputs the second pull-up signal according to a clock signal of a next stage shift register, so that the voltage signal is maintained at the second level.

In one embodiment, the input module inputs the stage signal to the boost node according to a clock signal of a shift register of a previous stage to increase a voltage signal of the boost node to the first level.

the voltage signal at the boost node can be pulled up to a higher level because a pull-up module is used to pre-charge the boost node, so that the shift register can accurately and smoothly output the gate scan signal. In addition, because the pull-up module can also output the pull-up signal when the pulse of the grid scanning signal is ended, and maintain the voltage signal of the boosted node at a high level, the pull-down grid scanning signal can be accelerated, the trailing phenomenon of the grid scanning signal can be further improved, and the quality of a display picture can be improved.

The above description is only an overview of the technology, and can be implemented in accordance with the description so as to make the technical means of the present application more clearly understood, and so as to make the above and other objects, features, and advantages of the present application more clearly understood, the following detailed description is given with reference to the accompanying drawings and specific examples.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

FIG. 1a is a schematic diagram of an exemplary display.

FIG. 1b is a schematic view of a display according to an embodiment of the present application.

FIG. 2a is a diagram of an exemplary shift register circuit.

FIG. 2b is a waveform diagram of an exemplary voltage signal at the boost node of the shift register circuit.

FIG. 2c is a timing diagram illustrating the operation of an exemplary shift register circuit.

Fig. 3a is a block configuration diagram of a shift register circuit in the first embodiment of the present invention.

Fig. 3b is a schematic circuit configuration diagram of the shift register circuit in the first embodiment of the present invention.

Fig. 3c is a block configuration diagram of a shift register circuit in the second embodiment of the present invention.

Fig. 3d is a schematic circuit configuration diagram of the shift register circuit in the second embodiment of the present invention.

Fig. 3e is a schematic diagram of the waveform of the voltage signal at the booster node in the shift register circuit in the present embodiment.

Fig. 4 is an operation timing diagram of the shift register circuit in the present embodiment.

FIG. 5 is a schematic view of a display device according to an embodiment of the present application.

Detailed Description

Specific circuit structural and functional details disclosed herein are merely representative and are for the purpose of describing example embodiments of the present invention. The present invention may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, it is to be understood that the terms "straight," "lateral," "upper," "lower," "left," "right," "inner," "outer," and the like are indicative of the orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, but are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or assembly referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present application . Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

In the present description, it is to be noted that, unless explicitly stated or limited otherwise, the terms "configured", "connected" and "connected" are to be interpreted broadly, e.g. as being fixedly connected, detachably connected or integrally connected; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meaning of the above terms in this application can be understood in a particular situation to one of ordinary skill in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.

To further explain the technical means and effects of the present invention adopted to achieve the predetermined object, the embodiments, structures, features and effects thereof of a shift register circuit and a waveform generating method thereof and a display device using the same according to the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

In certain embodiments, the display device may be, for example, a liquid crystal display device, an OLED display device, a QLED display device, a curved display device, or other display device. Taking a liquid crystal display device as an example, the display device of the present invention includes an active glass substrate (array glass substrate), an opposing substrate, and a liquid crystal layer formed between the substrates. Of course, the thin film transistor array (TFT array) and the Color Filter (CF) of the present invention may be formed on the same substrate according to the requirements. In addition, the display device of the present invention can also be manufactured as a curved-surface type display device.

FIG. 1a is a schematic diagram of an exemplary display device. Referring to fig. 1a, a display device 10 includes an active switch array substrate 101, an opposite substrate 100 opposite to the active switch array substrate 101, and a gate driver chip 102 for driving a circuit. As shown in fig. 1a, the gate driver chip 102 is externally connected to the right side of the active switch array substrate 101.

FIG. 1b is a schematic diagram of a display device according to an embodiment of the present application. Referring to fig. 1b, in an embodiment of the present invention, a display device 12 with array substrate gate driving includes an active switch array substrate 121, an opposite substrate 120 disposed opposite to the active switch array substrate 121, and an array substrate gate driving circuit 122, wherein the array substrate gate driving circuit 122 is directly fabricated on the surface of the active switch array substrate 121 by photolithography process. As shown in fig. 1b, the array substrate gate driving circuit 122 is respectively fabricated on the left and right surfaces of the active switch array substrate 121.

Fig. 2a is a schematic diagram of an exemplary shift register circuit of the present application. Referring to fig. 2a, a shift register circuit includes multiple stages of shift registers, and each shift register 2 includes a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, a sub pull-down controller (sub pull-down controller)21, and a sub pull-down module (sub pull-down) 22. In one embodiment, the shift register circuit includes n stages of shift registers, where n is a positive integer, and fig. 2a shows the nth stage of shift register 2.

A control terminal T1a of the first switch T1 is electrically coupled to a boost node (boost point) BP, a first terminal T1b of the first switch T1 is electrically coupled to a clock signal CK, and a second terminal T1c of the first switch T1 is electrically coupled to an output terminal O for outputting the gate scan signal Gn.

The second switch T2 is electrically coupled to a stage transmission signal ST of a shift register of a previous stage, and is used for inputting the stage transmission signal ST to the boost node BP to increase the level of the voltage signal Qn of the boost node BP. A control terminal T2a and a first terminal T2b of the second switch T2 are electrically coupled to the stage signal ST, and a second terminal T2c of the second switch T2 is electrically coupled to the boost node BP.

A control terminal T3a of the third switch T3 is electrically coupled to a feedback signal FB, a first terminal T3b of the third switch T3 is electrically coupled to the gate scan signal Gn of the output terminal O, and a second terminal T3c of the third switch T3 is electrically coupled to a predetermined low level Vss.

A control terminal T4a of the fourth switch T4 is electrically coupled to the feedback signal FB, a first terminal T4b of the fourth switch T4 is electrically coupled to the boost node BP, and a second terminal T4c of the fourth switch T4 is electrically coupled to the predetermined low level Vss.

The sub pull-down module 22 is electrically coupled to the boost node BP, the gate scan signal Gn and the predetermined low level Vss of the shift register 2, and configured to maintain the voltage signal Qn and the gate scan signal Gn at the predetermined low level Vss.

The sub pull-down control module 21 is electrically coupled to the low predetermined potential Vss of the shift register 2 and the sub pull-down module 22, and is configured to control the sub pull-down module 22 to operate at a correct time. That is, the sub pull-down module 22 can eliminate the noise at the boost node BP and the output terminal O, and ensure that the voltage signal Qn and the gate scan signal Gn can be continuously maintained at the predetermined low level Vss during the non-operation time, thereby avoiding the malfunction.

Fig. 2b is a waveform diagram of the voltage signal Qn of the boost node BP in the exemplary shift register circuit. Referring to fig. 2a, when the stage transmission signal ST of the previous stage shift register (n-1) in fig. 2a is transmitted to the boost node BP, the boost node BP is precharged to increase the voltage signal Qn to a level a, as shown in fig. 2 b. Subsequently, when the clock signal CK is applied to the first terminal T1B of the first switch T1, electrical coupling occurs, such that the voltage signal Qn of the boost node BP is further increased from the precharged level a to the level B, as shown in fig. 2B. The coupled voltage signal Qn is applied to the control terminal T1a of the first switch T1, such that the first switch T1 is turned on, the clock signal CK at the first terminal T1a is transmitted to the second terminal T1b, and is outputted via the output terminal O, such that the gate scan signal Gn is generated. Subsequently, as shown in fig. 2B, the voltage signal Qn of the boost node BP decreases from the coupled level B to the precharged level a with the end of the clock signal CK.

Fig. 2c is a schematic diagram of the operation timing of the shift register circuit in the present embodiment. Fig. 2c is a timing chart showing the operation of a 4 th stage (n-4) shift register 2. As shown in FIG. 2c, the shift register circuit uses eight sets of clock signals CK1-CK8 to control the operation. The voltage signal Q4 of the shift register 2 at the boost node BP can be divided into three periods, t1 is the precharge time; t2 is the output gate scan signal time; t3 is the pull-down gate scan signal time.

In the time period t1, the voltage signal Q4 is increased to the level a because the voltage boosting node BP is precharged by receiving the stage signal ST from the previous stage shift register, i.e., the stage signal ST from the 3 rd stage shift register. That is, the second switch T2 follows the pulse of the clock signal CK (n-2) of the previous stage shift register, i.e., the pulse of the clock signal CK2 in FIG. 2c, and inputs the stage signal ST to the boost node BP to increase the voltage signal Q4 of the boost node BP to the level A.

In the period T2, since the clock signal CK4 is electrically coupled to the boost node BP, the voltage signal Q4 is increased from the level a to the level B, and the first switch T1 in fig. 2a is turned on, so that the clock signal CK4 is turned on and the gate scan signal is output.

Subsequently, in the period t3, since the pulse of the clock signal CK4 ends, the voltage signal Q4 of the boost node BP is pulled down from the level B to the level a. Then, following the pulse of the clock signal CK8, the shift register 2 receives the feedback signal FB, discharges the boost node BP, and pulls down the voltage signal Q4 from level a to a predetermined low level.

Please refer to fig. 3a, fig. 3b, and fig. 3 e. Fig. 3a is a block configuration diagram of a shift register circuit in the first embodiment of the present invention. Fig. 3b is a schematic circuit configuration diagram of the shift register circuit in the first embodiment of the present invention. Fig. 3e is a schematic diagram showing the waveform of the voltage signal at the booster node in the shift register circuit according to the present embodiment.

Referring to fig. 3a and fig. 3e, a shift register circuit includes multiple stages of shift registers, wherein a shift register 3 mainly includes an input module 31, a pull-up module 32, an output module 33, and a feedback module 34. In one embodiment, the shift register circuit includes n stages of shift registers, where n is a positive integer, and fig. 3a shows the nth stage of shift register 3.

The input module 31 is configured to input a stage transmission signal ST of a previous stage shift register to a boost node BP, for example, the stage transmission signal ST of the previous stage shift register can be input to increase a voltage signal Qn of the boost node BP to a first level a', as shown in fig. 3 e. It is to be noted that although the stage signal ST of the previous stage shift register is input in this embodiment, the stage signal ST of the previous stage shift register, the previous stage, or other previous stage (n-x) shift register may be selected and input according to the signal configuration.

The pull-up module 32 is configured to output a first pull-up signal Pu1 to the boost node BP, pull up the voltage signal Qn from the first level a ' to a second level B ', and output a second pull-up signal Pu2 to the boost node BP, so that the voltage signal Qn is maintained at the second level B ', as shown in fig. 3 e.

The output module 33 receives a clock signal CKn and couples and pulls up the voltage signal Qn from the second high level B 'to the third high level C' according to the clock signal CKn, as shown in fig. 3 e. The output module 33 is controlled by the coupled voltage signal Qn to turn on, and outputs a gate scan signal Gn through an output terminal O. When the pulse of the clock signal CKn ends, the pull-up module 32 outputs the second pull-up signal Pu2 to the boost node BP, so that the voltage signal Qn is maintained at the second level B'.

The feedback module 34 receives a feedback signal FB, and pulls down the voltage signal Qn coupled to the boost node BP and the gate scan signal Gn to a predetermined low level Vss.

In one embodiment, the shift register 3 further includes a sub pull-down control module 35 and a sub pull-down module 36. The sub pull-down module 36 is configured to maintain the voltage signal Qn at the predetermined low level Vss. As for the sub pull-down control module 35, it is used to control the operation of the sub pull-down module 36.

Next, referring to fig. 3b, fig. 3b shows a detailed circuit structure of the nth stage shift register 3. The output module 33 includes a switch T11. A control terminal T11a of the switch T11 is electrically coupled to the boost node BP, a first terminal T11b of the switch T11 is configured to receive the clock signal CKn, and a second terminal T11c of the switch T11 is electrically coupled to the output terminal O for outputting the gate scan signal Gn. When the voltage signal Qn of the boost node BP is coupled to be raised to the third level C', the switch T11 is turned on and outputs the gate scan signal Gn.

The input module 31 includes a switch T12, a control terminal T12a of the switch T12 is electrically coupled to the first terminal T12b of the switch T12, and a second terminal T12c of the switch T12 is electrically coupled to the boost node BP for outputting the stage signal ST to the boost node BP to increase the voltage signal Qn of the boost node BP to the first level a'.

The feedback module 34 includes a switch T13 and a switch T14. A control terminal T13a of the switch T13 is electrically coupled to a feedback signal FB, a first terminal T13b of the switch T13 is electrically coupled to the output terminal O, and a second terminal T13c of the switch T13 is electrically coupled to the predetermined low level. The switch T13 is turned on in response to the feedback signal FB, turning on the first terminal T13b and the second terminal T13c of the switch T13, and pulling the gate scan signal Gn down to the predetermined low level Vss.

A control terminal T14a of the switch T14 is electrically coupled to the feedback signal FB, a first terminal T14b of the switch T14 is electrically coupled to the boost node BP, and a second terminal T14c of the switch T14 is electrically coupled to the predetermined low level Vss. The switch T14 is turned on in response to the feedback signal FB, and turns on the first terminal T14b and the second terminal T14c of the switch T14 to pull down the voltage signal Qn to the predetermined low level Vss.

The pull-up module 32 includes a switch T15, a switch T16, a switch T17, and a switch T18.

A control terminal T15a of the switch T15 is electrically coupled to the clock signal CK (n-1) of the previous stage shift register, and a first terminal T15b of the switch T15 is electrically coupled to the clock signal CK (n-2) of the previous stage shift register. The switch T15 is turned on in response to the clock signal CK (n-1) of the previous stage shift register, turns on the first terminal T15b and the second terminal T15c of the switch T15, and transmits the clock signal CK (n-2) of the previous stage shift register to the second terminal T15c of the switch T15.

A control terminal T16a of the switch T16 is electrically coupled to the voltage signal Q (n-1) of the previous stage shift register, a first terminal T16b of the switch T16 is electrically coupled to the second terminal T15c of the switch T15, and a second terminal T16c of the switch T16 is electrically coupled to the boost node BP. The switch T16 is turned on in response to the voltage signal Q (n-1) of the shift register of the previous stage, turns on the first terminal T16b and the second terminal T16c of the switch T16, and outputs the first pull-up signal Pu1(n) to the boost node BP.

A control terminal T17a of the switch T17 is electrically coupled to the clock signal CK (n +1) of the next stage of shift register, and a first terminal T17b of the switch T17 is electrically coupled to the clock signal CK (n +2) of the next stage of shift register. The switch T17 is turned on in response to a clock signal CK (n +1) of the next stage shift register, turns on the first terminal T17b and a second terminal T17c of the switch T17, and transmits the clock signal CK (n +2) of the next stage shift register to the second terminal T17c of the switch T17.

A control terminal T18a of the switch T18 is electrically coupled to the voltage signal Q (n +1) of the shift register of the next stage, a first terminal T18b of the switch T18 is electrically coupled to the second terminal T17c of the switch T17, and a second terminal T18c of the switch T18 is electrically coupled to the boost node BP. The switch T18 is turned on in response to the voltage signal Q (n +1) of the shift register of the next stage, turns on the first terminal T18b and the second terminal T18c of the switch T18, and outputs the second pull-up signal Pu2(n) to the boost node BP.

From the above circuit configuration, it can be understood that the pull-up module 32 outputs the first pull-up signal Pu1 under the control of the voltage signal Q (n-1) of the previous stage shift register, and outputs the second pull-up signal Pu2 under the control of the voltage signal Q (n +1) of the next stage shift register.

In other words, the pull-up module 32 outputs the first pull-up signal Pu1 according to the clock signal CK (n-1) of the previous stage shift register, pulls the voltage signal Qn from the first level a ' to the second level B ', and outputs the second pull-up signal Pu2 according to the clock signal CK (n +2) of the next stage shift register, so that the voltage signal Qn is maintained at the second level B '.

In addition, the input module 31 inputs the stage signal ST to the boost node BP according to the clock signal CK (n-2) of the shift register of the previous stage, so as to increase the voltage signal Qn of the boost node BP to the first level a'.

Fig. 3e is a waveform diagram of the voltage signal Qn of the boost node BP in the exemplary shift register circuit. When the stage signal ST of the previous stage shift register in fig. 3b is transmitted to the boost node BP according to the pulse of the clock signal CK (n-2), the boost node BP is precharged to raise the voltage signal Qn to the first level a', as shown in fig. 3 e.

Then, according to the pulse of the clock signal CK (n-1), the pull-up module 32 transmits the first pull-up signal Pu1 to the boost node BP, so that the voltage signal Qn of the boost node BP is pulled up from the first level a 'to the second level B'.

Subsequently, when the clock signal CKn is applied to the first terminal T11B of the switch T11, the electrical coupling is generated, so that the voltage signal Qn of the boost node BP is further increased from the second level B 'after the precharge to the third level C', as shown in fig. 3 e. The coupled voltage signal Qn is applied to the control terminal T11a of the switch T11, such that the switch T11 is turned on, the clock signal CKn at the first terminal T11a is transmitted to the second terminal T11b, and is outputted via the output terminal O, such that the gate scan signal Gn is generated.

Subsequently, as shown in fig. 3e, the voltage signal Qn of the boost node BP decreases from the third level C' after the coupling with the end of the clock signal CKn. At this time, according to the pulse of the clock signal CK (n +2), the pull-up module 32 transmits the second pull-up signal Pu2 to the boost node BP, so that the voltage signal of the boost node BP can be continuously maintained at the second level B'. When the pulse of the clock signal CK (n +1) ends, the pull-up module stops outputting the second pull-up signal Pu2, and the voltage signal Qn of the boost node BP is pulled down from the second level B 'to the first level a'.

Referring to fig. 3a, fig. 3b, fig. 3e and fig. 4, fig. 4 is a schematic diagram of the operation timing of the shift register circuit in the present embodiment, which is used to show the operation timing diagram of the 4 th (n-4) shift register 3, and also shows the partial operation timing of the 4 th shift register 2 for comparison.

As shown in FIG. 4, the shift register circuit uses eight sets of clock signals CK1-CK8 to control the operation. The voltage signal Q4 'of the shift register 3 at the boost node BP can be divided into five periods, wherein t 1' is the precharge time of the stage signal ST; t 2' is the action time of the first pull-up signal Pu 1; t 3' is the output gate scanning signal Gn time; t 4' is the action time of the second pull-up signal Pu 2; t 5' is the pull-down gate scan signal Gn time.

In the time period t1 ', the voltage signal Q4 ' is raised to the first level a ' because the voltage boosting node BP is precharged by the stage signal ST transmitted from the previous stage shift register, i.e., the stage signal ST of the 3 rd stage shift register, according to the clock signal CK 2. That is, the switch T12 inputs the stage signal ST to the boost node BP according to the clock signal CK 2.

In the time period t2 ', according to the clock signal CK3, the pull-up module 32 outputs the first pull-up signal Pu1 to pull up the voltage signal Q4' from the first level a 'to the second level B', and the pulse of the first pull-up signal Pu1 follows the end of the pulse of the clock signal CK 2.

In the period T3 ', since the clock signal CK4 is applied to the first terminal T11B of the switch T11 and electrically coupled to the boost node BP, the voltage signal Q4' is coupled from the second level B 'to the third level C', and the switch T11 in fig. 3B is turned on to turn on the clock signal CK4 and output the gate scan signal.

Subsequently, at the time period t4 ', the pulse of the clock signal CK4 ends, resulting in the voltage signal Q4 ' of the boost node BP being pulled down from the third level C '. However, according to the clock signal CK6, the pull-up module 32 outputs the second pull-up signal Pu2 such that the voltage signal Q4 'can be maintained at the second level B'. The pulse of the second pull-up signal Pu2 ends at the same time as the pulse of the clock signal CK 5.

In the time period t5 ', the voltage signal Q4' is pulled down from the second level B 'to the first level a' due to the end of the pulse of the second pull-up signal Pu 2. After the time period t5 ', the shift register 3 receives the feedback signal FB to discharge the boost node BP and pull down the voltage signal Q4 ' from the first level a ' to a predetermined low level with the pulse of the clock signal CK 8.

It should be noted that the pull-up module 32 can generate the required first pull-up signal Pu1 and the required second pull-up signal Pu2 through different signal control methods besides the signal control method shown in fig. 3 b.

For example, in FIG. 3b, the control terminal T15a of the switch T15 is electrically coupled to the clock signal CK (n-1) of the previous stage shift register, and the first terminal T15b is electrically coupled to the clock signal CK (n-2) of the previous stage shift register. However, in one embodiment, the control terminal T15a of the switch T15 can also be electrically coupled to the clock signal CK (n-2) of the previous stage shift register, and the first terminal T15b can be electrically coupled to the clock signal CK (n-1) of the previous stage shift register. The switch T15 is turned on in response to the clock signal CK (n-2) of the shift register of the previous stage, turns on the first terminal T15b and the second terminal T15c of the switch T15, and transmits the clock signal CK (n-1) of the shift register of the previous stage to the second terminal T15c of the switch T15.

In addition, in fig. 3b, the control terminal T17a of the switch T17 is electrically coupled to the clock signal CK (n +1) of the next stage shift register, and the first terminal T17b is electrically coupled to the clock signal CK (n +2) of the next stage shift register. However, in one embodiment, the control terminal T17a of the switch T17 may also be electrically coupled to the clock signal CK (n +2) of the next stage of shift register, and the first terminal T17b may be electrically coupled to the clock signal CK (n +1) of the next stage of shift register. Thus, the switch T17 is turned on in response to the clock signal CK (n +2) of the post-stage shift register, so as to turn on the first terminal T17b and the second terminal T17c of the switch T17, and transmit the clock signal CK (n +1) of the post-stage shift register to the second terminal T17c of the switch T17.

In one embodiment, a control terminal T16a of the switch T16 may also be electrically coupled to the voltage signal Q (n-2) of the shift register of the previous stage, and is turned on in response to the voltage signal Q (n-2) of the shift register of the previous stage to output the first pull-up signal Pu1(n) to the boost node BP.

In another embodiment, a control terminal T18a of the switch T18 may also be electrically coupled to the voltage signal Q (n +2) of the next stage shift register, and is turned on in response to the voltage signal Q (n +2) of the next stage shift register to output the second pull-up signal Pu2(n) to the boost node BP.

Please refer to fig. 3c, fig. 3d, and fig. 3 e. Fig. 3c is a block diagram of a shift register circuit according to a second embodiment of the present application. Fig. 3d is a circuit diagram of a shift register circuit according to a second embodiment of the present application. Fig. 3e is a schematic diagram illustrating a waveform of a voltage signal at a boost node in a shift register circuit according to an embodiment of the present disclosure.

Referring to fig. 3c and fig. 3e, a shift register circuit includes a plurality of shift registers, wherein a shift register 4 mainly includes an input module 41, a coupling pull-up module 42, an output module 43, and a feedback module 44. In one embodiment, the shift register circuit includes n stages of shift registers, where n is a positive integer, and fig. 3c shows the nth stage of shift register 4.

The input module 41 is configured to input a stage transmission signal ST of a previous stage shift register to a boost node BP, for example, the stage transmission signal ST of the previous stage shift register can be input to increase a voltage signal Qn of the boost node BP to a first level a', as shown in fig. 3 e. It is to be noted that although the stage signal ST of the previous stage shift register is input in this embodiment, the stage signal ST of the previous stage shift register may be selected to be input to the previous stage, or other previous stage shift registers according to the signal configuration.

The coupling pull-up module 42 is coupled to the boost node BP, and configured to generate a first pull-up signal Pu1 and a second pull-up signal Pu 2. The first pull-up signal Pu1 can be coupled to indirectly act on the boost node BP to pull up the voltage signal Qn from the first level a ' to a second level B ', and the second pull-up signal Pu2 can be coupled to indirectly act on the boost node BP to maintain the voltage signal Qn at the second level B ', as shown in fig. 3 e.

The output module 43 receives a clock signal CKn and couples and pulls up the voltage signal Qn from the second high level B 'to the third high level C' according to the clock signal CKn, as shown in fig. 3 e. The output module 43 is controlled by the coupled voltage signal Qn to turn on, and outputs a gate scan signal Gn through an output terminal O. When the pulse of the clock signal CKn is ended, the coupling pull-up module 42 generates the second pull-up signal Pu2, and indirectly acts on the boost node BP through electrical coupling, so that the voltage signal Qn is maintained at the second level B'.

The feedback module 44 receives a feedback signal FB, and pulls down the voltage signal Qn coupled to the boost node BP and the gate scan signal Gn to a predetermined low level Vss.

In one embodiment, the shift register 4 further includes a sub pull-down control module 45 and a sub pull-down module 46. The sub-pull-down module 46 is configured to maintain the voltage signal Qn at the predetermined low level Vss. As for the sub pull-down control module 45, it is used to control the operation of the sub pull-down module 46.

Next, referring to fig. 3d, fig. 3d shows a detailed circuit structure of the nth stage shift register 4. The output module 43 includes a switch T21. A control terminal T21a of the switch T21 is electrically coupled to the boost node BP, a first terminal T21b of the switch T21 is configured to receive the clock signal CKn, and a second terminal T21c of the switch T21 is electrically coupled to the output terminal O for outputting the gate scan signal Gn. When the voltage signal Qn of the boost node BP is coupled to be raised to the third level C', the switch T21 is turned on and outputs the gate scan signal Gn.

The input module 41 includes a switch T22, a control terminal T22a of the switch T22 is electrically coupled to the first terminal T22b of the switch T22, and a second terminal T22c of the switch T22 is electrically coupled to the boost node BP for outputting the stage signal ST to the boost node BP to increase the voltage signal Qn of the boost node BP to the first level a'.

The feedback module 44 includes a switch T23 and a switch T24. A control terminal T23a of the switch T23 is electrically coupled to a feedback signal FB, a first terminal T23b of the switch T23 is electrically coupled to the output terminal O, and a second terminal T23c of the switch T23 is electrically coupled to the predetermined low level Vss. The switch T23 is turned on in response to the feedback signal FB, turning on the first terminal T23b and the second terminal T23c of the switch T23, and pulling the gate scan signal Gn down to the predetermined low level Vss.

A control terminal T24a of the switch T24 is electrically coupled to the feedback signal FB, a first terminal T24b of the switch T24 is electrically coupled to the boost node BP, and a second terminal T24c of the switch T24 is electrically coupled to the predetermined low level Vss. The switch T24 is turned on in response to the feedback signal FB, and turns on the first terminal T24b and the second terminal T24c of the switch T24 to pull down the voltage signal Qn to the predetermined low level Vss.

The coupling pull-up module 42 includes a switch T25, a switch T26, a switch T27, a switch T28, and a switch T29.

A control terminal T25a of the switch T25 is electrically coupled to the clock signal CK (n-1) of the previous stage shift register, and a first terminal T25b of the switch T25 is electrically coupled to the clock signal CK (n-2) of the previous stage shift register. The switch T25 is turned on in response to the clock signal CK (n-1) of the previous stage shift register, turns on the first terminal T25b and the second terminal T25c of the switch T25, and transmits the clock signal CK (n-2) of the previous stage shift register to the second terminal T25c of the switch T25.

A control terminal T26a of the switch T26 is electrically coupled to the voltage signal Q (n-1) of the previous stage shift register, a first terminal T26b of the switch T26 is electrically coupled to the second terminal T25c of the switch T25, and a second terminal T26c of the switch T26 is electrically coupled to a first terminal T29b of the switch T29 and coupled to the boost node BP through the switch T29. The switch T26 is turned on in response to the voltage signal Q (n-1) of the shift register of the previous stage, turns on the first terminal T26b and the second terminal T26c of the switch T26, and outputs the first pull-up signal Pu1 (n).

A control terminal T27a of the switch T27 is electrically coupled to the clock signal CK (n +1) of the next stage of shift register, and a first terminal T27b of the switch T27 is electrically coupled to the clock signal CK (n +2) of the next stage of shift register. The switch T27 is turned on in response to a clock signal CK (n +1) of the next stage shift register, turns on the first terminal T27b and a second terminal T27c of the switch T27, and transmits the clock signal CK (n +2) of the next stage shift register to the second terminal T27c of the switch T27.

A control terminal T28a of the switch T28 is electrically coupled to the voltage signal Q (n +1) of the shift register of the next stage, a first terminal T28b of the switch T28 is electrically coupled to the second terminal T27c of the switch T27, and a second terminal T28c of the switch T28 is electrically coupled to the first terminal T29b of the switch T29 and coupled to the boost node BP through the switch T29. The switch T28 is turned on in response to the voltage signal Q (n +1) of the next stage shift register, turns on the first terminal T28b and the second terminal T28c of the switch T28, and outputs the second pull-up signal Pu2 (n).

A control terminal T29a of the switch T29 is electrically coupled to the boost node BP, a first terminal T29b of the switch T29 is configured to receive the first pull-up signal Pu1 and the second pull-up signal Pu2, and a second terminal T29b of the switch T29 is electrically coupled to the predetermined low level Vss, wherein the switch T29 is turned on in response to the voltage signal Qn to turn on the first terminal T29b and the second terminal T29c of the switch T29.

When the first terminal T29B of the switch T29 receives the first pull-up signal Pu1, the first pull-up signal is coupled to the control terminal T29a of the switch T29, and the voltage signal Qn of the boost node BP is pulled up to the second level B'. Subsequently, when the second terminal T29c of the switch T29 receives the second pull-up signal Pu2, the second terminal T29 is also coupled to the control terminal T29a of the switch T29, so as to maintain the voltage signal Qn of the boost node BP at the second level B'.

In addition, it can be understood from the above circuit structure that the coupling pull-up module 42 is controlled by the voltage signal Q (n-1) of the previous stage shift register to generate the first pull-up signal Pu1, and is controlled by the voltage signal Q (n +1) of the next stage shift register to generate the second pull-up signal Pu2, and is electrically coupled to the voltage boost node to maintain the voltage signal Qn at the second level.

In other words, the coupled pull-up module 42 generates the first pull-up signal Pu1 according to the clock signal CK (n-1) of the previous stage shift register, couples the voltage signal Qn from the first level a ' to the second level B ', and generates the second pull-up signal Pu2 according to the clock signal CK (n +2) of the next stage shift register, electrically coupled to the voltage boost node, so that the voltage signal Qn is maintained at the second level B '.

In addition, the input module 41 inputs the stage signal ST to the boost node BP according to the clock signal CK (n-2) of the shift register of the previous stage, so as to increase the voltage signal Qn of the boost node BP to the first level a'.

Fig. 3e is a waveform diagram of the voltage signal Qn of the boost node BP in the exemplary shift register circuit. When the stage signal ST of the previous stage shift register in fig. 3d is transmitted to the boost node BP according to the pulse of the clock signal CK (n-2), the boost node BP is precharged to raise the voltage signal Qn to the first level a', as shown in fig. 3 e.

Then, according to the pulse of the clock signal CK (n-1), the coupling pull-up module 42 generates a first pull-up signal Pu1, and electrically couples the voltage signal Qn of the boost node BP from the first level A 'to a second level B'.

Subsequently, when the clock signal CKn is applied to the first terminal T21B of the switch T21, the electrical coupling is generated, so that the voltage signal Qn of the boost node BP is further increased from the second level B 'after the precharge to the third level C', as shown in fig. 3 e. The coupled voltage signal Qn is applied to the control terminal T21a of the switch T21, such that the switch T21 is turned on, the clock signal CKn at the first terminal T21a is transmitted to the second terminal T21b, and is outputted via the output terminal O, such that the gate scan signal Gn is generated.

Subsequently, as shown in fig. 3e, the voltage signal Qn of the boost node BP decreases from the third level C' after the coupling with the end of the clock signal CKn. At this time, according to the pulse of the clock signal CK (n +2), the coupling pull-up module 42 generates the second pull-up signal Pu2, and indirectly acts on the boost node BP through electrical coupling, so that the voltage signal of the boost node BP can be continuously maintained at the second level B'. When the pulse of the clock signal CK (n +1) ends, the coupled pull-up module stops outputting the second pull-up signal Pu2, and the voltage signal Qn of the boost node BP is pulled down from the second level B 'to the first level a'.

The following description is made with reference to fig. 3c, 3d, 3e, and 4.

As shown in FIG. 4, the shift register circuit uses eight sets of clock signals CK1-CK8 to control the operation. The voltage signal Q4 'of the shift register 4 at the boost node BP can be divided into five periods, wherein t 1' is the stage signal ST for the pre-charging time; t 2' is the coupling time of the first pull-up signal Pu 1; t 3' is the output gate scanning signal Gn time; t 4' is the coupling action time of the second pull-up signal Pu 2; t 5' is the pull-down gate scan signal Gn time.

In the time period t1 ', the voltage signal Q4 ' is raised to the first level a ' because the voltage boosting node BP is precharged by the stage signal ST transmitted from the previous stage shift register, i.e., the stage signal ST of the 3 rd stage shift register, according to the clock signal CK 2. That is, the switch T22 inputs the stage signal ST to the boost node BP according to the clock signal CK 2.

At time t2 ', according to the clock signal CK3, the coupling pull-up module 42 generates the first pull-up signal Pu1 electrically coupled to the boost node BP to pull the voltage signal Q4' from the first level a 'to the second level B', and the pulse of the first pull-up signal Pu1 follows the end of the pulse of the clock signal CK 2.

In the period T3 ', since the clock signal CK4 is applied to the first terminal T21B of the switch T21 and electrically coupled to the boost node BP, the voltage signal Q4' is coupled from the second level B 'to the third level C', and the switch T21 in fig. 3d is turned on to turn on the clock signal CK4 and output the gate scan signal.

Subsequently, at the time period t4 ', the pulse of the clock signal CK4 ends, resulting in the voltage signal Q4 ' of the boost node BP being pulled down from the third level C '. However, according to the clock signal CK6, the coupling pull-up module 42 generates the second pull-up signal Pu2, which is electrically coupled to the boost node BP, such that the voltage signal Q4 'is maintained at the second level B'. The pulse of the second pull-up signal Pu2 ends at the same time as the pulse of the clock signal CK 5.

In the time period t5 ', the voltage signal Q4' is pulled down from the second level B 'to the first level a' due to the end of the pulse of the second pull-up signal Pu 2. After the time period t5 ', the shift register 4 receives the feedback signal FB to discharge the boost node BP and pull down the voltage signal Q4 ' from the first level a ' to a predetermined low level with the pulse of the clock signal CK 8.

It is noted that, in addition to the signal control manner shown in fig. 3d, the coupling pull-up module 42 can generate the required first pull-up signal Pu1 and the required second pull-up signal Pu2 through different signal control manners.

For example, in FIG. 3d, the control terminal T25a of the switch T25 is electrically coupled to the clock signal CK (n-1) of the previous stage shift register, and the first terminal T25b is electrically coupled to the clock signal CK (n-2) of the previous stage shift register. However, in one embodiment, the control terminal T25a of the switch T25 can also be electrically coupled to the clock signal CK (n-2) of the previous stage shift register, and the first terminal T25b can be electrically coupled to the clock signal CK (n-1) of the previous stage shift register. The switch T25 is turned on in response to the clock signal CK (n-2) of the shift register of the previous stage, turns on the first terminal T25b and the second terminal T25c of the switch T25, and transmits the clock signal CK (n-1) of the shift register of the previous stage to the second terminal T25c of the switch T25.

In addition, in fig. 3d, the control terminal T27a of the switch T27 is electrically coupled to the clock signal CK (n +1) of the next stage shift register, and the first terminal T27b is electrically coupled to the clock signal CK (n +2) of the next stage shift register. However, in one embodiment, the control terminal T27a of the switch T27 may also be electrically coupled to the clock signal CK (n +2) of the next stage of shift register, and the first terminal T27b may be electrically coupled to the clock signal CK (n +1) of the next stage of shift register. Thus, the switch T27 is turned on in response to the clock signal CK (n +2) of the post-stage shift register, so as to turn on the first terminal T27b and the second terminal T27c of the switch T27, and transmit the clock signal CK (n +1) of the post-stage shift register to the second terminal T27c of the switch T27.

In one embodiment, a control terminal T26a of the switch T26 may also be electrically coupled to the voltage signal Q (n-2) of the shift register of the previous stage, and is turned on in response to the voltage signal Q (n-2) of the shift register of the previous stage to output the first pull-up signal Pu1 (n).

In another embodiment, a control terminal T28a of the eighth switch T28 may also be electrically coupled to the voltage signal Q (n +2) of the post-stage shift register, and is turned on in response to the voltage signal Q (n +2) of the post-stage shift register to output the second pull-up signal Pu2 (n).

Fig. 5 is a schematic view of a display device according to an embodiment of the present application. Referring to fig. 5, the display device 12 includes an active switch array substrate 121, an opposite substrate 120 opposite to the active switch array substrate 121, and an array substrate gate driving circuit 122, wherein the array substrate gate driving circuit 122 is directly fabricated on the surface of the active switch array substrate 121 by a photolithography process. The array substrate gate driving circuit 122 includes the shift register circuits shown in fig. 3c and fig. 3 d. That is, the array substrate gate driving circuit 110 has a plurality of stages of shift registers 3 or 4.

Since the voltage boosting node uses a pull-up module to output the first pull-up signal Pu1, and pre-charges the voltage boosting node in cooperation with the stage signal ST of the input module, the voltage signal at the voltage boosting node can be pulled up to a higher level. Therefore, when the clock signal is electrically coupled with the output module, the switch can be ensured to be rapidly opened, so that the shift register can accurately and smoothly output the grid scanning signal.

Secondly, since the pull-up module outputs the second pull-up signal Pu2 to maintain the voltage signal at the boost node at a high level when the pulse of the gate scan signal ends, the pull-down gate scan signal can be accelerated, thereby improving the tailing of the gate scan signal and improving the quality of the display image.

Although the present invention has been described with reference to specific embodiments and examples only, and not to be limited thereto in any way, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the present invention , and all such changes and modifications as would fall within the spirit and scope of the present invention are to be embraced by the present invention in any simple modifications, equivalents and modifications of the above embodiments in accordance with the principles of the present invention .

Claims (9)

1. A kind of shift register circuit, characterized by, including the multiple-stage shift register, wherein any stage of shift register includes:

the input module inputs a stage transmission signal of the preceding stage shift register to a boosting node;

the pull-up module outputs a first pull-up signal to the voltage boost node, pulls up the voltage signal from a first level to a second level, and outputs a second pull-up signal to the voltage boost node to maintain the voltage signal at the second level;

the output module receives a clock signal and couples and pulls up the voltage signal from the second level to a third level according to the clock signal, the output module is controlled by the coupled voltage signal and outputs a grid scanning signal through an output end, and when a pulse of the clock signal is ended, the pull-up module outputs the second pull-up signal to the voltage boost node to maintain the voltage signal at the second level; and

the feedback module receives a feedback signal and pulls down the voltage signal and the grid scanning signal after the voltage boost node is coupled to a preset low level;

wherein the pull-up module comprises:

a fifth switch, a control end of which is electrically coupled to the clock signal of the previous stage shift register, a first end of which is electrically coupled to the clock signal of the previous stage shift register, wherein the fifth switch is turned on in response to the clock signal of the previous stage shift register, turns on the first end and a second end of the fifth switch, and transmits the clock signal of the previous stage shift register to the second end of the fifth switch;

a sixth switch, a control terminal of which is electrically coupled to the voltage signal of the previous stage shift register, a first terminal of which is electrically coupled to the second terminal of the fifth switch, and a second terminal of which is electrically coupled to the voltage boost node, wherein the sixth switch is turned on in response to the voltage signal of the previous stage shift register, turns on the first terminal and the second terminal of the sixth switch, and outputs the first pull-up signal to the voltage boost node;

a seventh switch, a control terminal of which is electrically coupled to the clock signal of the next-stage shift register, a first terminal of which is electrically coupled to the clock signal of the next-stage shift register, wherein the seventh switch is turned on in response to the clock signal of the next-stage shift register, turns on the first terminal and a second terminal of the seventh switch, and transmits the clock signal of the next-stage shift register to the second terminal of the seventh switch; and

a control terminal of the eighth switch is electrically coupled to the voltage signal of the next shift register, a first terminal of the eighth switch is electrically coupled to the second terminal of the seventh switch, and a second terminal of the eighth switch is electrically coupled to the voltage boost node, wherein the eighth switch is turned on in response to the voltage signal of the next shift register, turns on the first terminal and the second terminal of the eighth switch, and outputs the second pull-up signal to the voltage boost node.

2. The shift register circuit of claim 1, wherein said shift register further comprises a sub-pull-down module for maintaining said voltage signal at said predetermined low level; and a sub pull-down control module for controlling an operation of the sub pull-down module.

3. The shift register circuit of claim 1, wherein the output module comprises a first switch, a control terminal of the first switch is electrically coupled to the voltage boost node, a first terminal of the first switch is configured to receive the clock signal, and a second terminal of the first switch is electrically coupled to the output terminal for outputting the gate scan signal, wherein when the voltage signal coupling of the voltage boost node is raised to the third level, the first switch is turned on and outputs the gate scan signal.

4. The shift register circuit of claim 1, wherein the input module comprises a second switch, a control terminal of the second switch is electrically coupled to a first terminal of the second switch, and a second terminal of the second switch is configured to output the stage transmission signal.

5. The shift register circuit of claim 1, wherein the feedback module comprises:

a third switch having a control end electrically coupled to the feedback signal, a first end electrically coupled to the output end, and a second end electrically coupled to the preset low level, wherein the third switch is turned on in response to the feedback signal, turns on the first end and the second end of the third switch, and pulls down the gate scan signal to the preset low level; and

a fourth switch, a control terminal of the fourth switch being electrically coupled to the feedback signal, a first terminal of the fourth switch being electrically coupled to the boost node, a second terminal of the fourth switch being electrically coupled to the predetermined low level, wherein the fourth switch is turned on in response to the feedback signal, turns on the first terminal and the second terminal of the fourth switch, and pulls down the voltage signal to the predetermined low level.

6. The shift register circuit as claimed in claim 1, wherein the pull-up module outputs the first pull-up signal under the control of a voltage signal of a previous stage shift register, and outputs the second pull-up signal under the control of a voltage signal of a next stage shift register.

7. The shift register circuit as claimed in claim 1, wherein the pull-up module outputs the first pull-up signal according to a clock signal of a shift register of a previous stage, pulls up the voltage signal from the first level to the second level, and outputs the second pull-up signal according to a clock signal of a shift register of a next stage, so that the voltage signal is maintained at the second level.

8. The shift register circuit of claim 1, wherein the input module inputs the stage signal to the boost node according to a clock signal of a shift register of a previous stage to increase the voltage signal of the boost node to the first level.

9. A display device, characterized in that the display device comprises:

an active switch array substrate; and

an opposite substrate arranged opposite to the active switch array substrate;

an array substrate gate driving circuit is fabricated on the active switch array substrate, and the array substrate gate driving circuit includes the shift register circuit according to any one of claims 1 to 8.

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