WO2020220565A1 - Goa circuit and display device - Google Patents

Goa circuit and display device Download PDF

Info

Publication number
WO2020220565A1
WO2020220565A1 PCT/CN2019/106224 CN2019106224W WO2020220565A1 WO 2020220565 A1 WO2020220565 A1 WO 2020220565A1 CN 2019106224 W CN2019106224 W CN 2019106224W WO 2020220565 A1 WO2020220565 A1 WO 2020220565A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
node
pull
control module
Prior art date
Application number
PCT/CN2019/106224
Other languages
French (fr)
Chinese (zh)
Inventor
李骏
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2020220565A1 publication Critical patent/WO2020220565A1/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the invention relates to the field of display technology, in particular to a GOA circuit and a display device.
  • the scanning line of organic light-emitting diode is driven by an external integrated circuit.
  • the external integrated circuit can control the step-by-step turn-on of the scanning lines at all levels, and the GOA (Gate The Driver on Array method can integrate the line scan driving circuit on the display panel substrate, which can reduce the number of external chips, thereby reducing the production cost of the display panel, and can realize the narrow frame of the display device.
  • the structure of the existing GOA circuit is relatively complex and requires more thin film transistors, which results in a relatively complicated manufacturing process and increases production costs.
  • the purpose of the present invention is to provide a GOA circuit and a display device, which can simplify the manufacturing process and reduce the production cost.
  • the present invention provides a GOA circuit with m cascaded GOA units, and the nth level GOA unit includes:
  • the first potential control module is connected to the n-1th level scanning signal, the first clock signal and the third clock signal;
  • the second potential control module is connected to the third clock signal, and the second potential control module is respectively connected to the first node and the second node;
  • the first pull-up module is connected to a second clock signal, and the first pull-up module is respectively connected to the second node and the first node;
  • a pull-down control module to access the second clock signal, and the first pull-down control module is respectively connected to the second node and the third node;
  • a pull-up control module connected to the first node and the third node respectively;
  • the second pull-up module is respectively connected with the third node and the output terminal;
  • Pull-down modules respectively connected to the first node and the output terminal;
  • One end of the storage capacitor is connected to the second node, and the other end of the storage capacitor is connected to the pull-down control module, where m ⁇ n ⁇ 1.
  • the GOA circuit of the present invention improves the existing GOA circuit, and realizes the output of the scan signal by using fewer thin film transistors, thus saving the number of thin film transistors and simplifying the structure of the GOA circuit, thereby reducing Cost of production.
  • Figure 1 is a schematic diagram of the structure of the GOA circuit of the present invention.
  • FIG. 2 is a timing diagram of the GOA circuit of the present invention.
  • Figure 3 is a simulation diagram of the GOA circuit of the present invention.
  • the GOA circuit of the present invention includes m cascaded GOA units, and the nth level GOA unit includes a first potential control module 100, a second potential control module 200, a first pull-up module 300, and a pull-down control module. 400.
  • the first potential control module 100 is connected to the n-1th level scan signal (IN), the first clock signal CK1 and the third clock signal CK3; for example, it is used to respond to the n-1th level scan signal (IN) and the first clock signal.
  • CK1 and the third clock signal CK3 control the potential of the first node A point.
  • the second potential control module 200 is connected to the third clock signal CK3, and the second potential control module 200 is respectively connected to the first node A and the second node B, for example, according to the first node
  • the potential of point A and the third clock signal CK3 control the potential of point B of the second node.
  • the first pull-up module 300 is connected to the second clock signal CK2, and the first pull-up module 300 is respectively connected to the second node B point and the first node A point.
  • the pull-down control module 400 accesses the second clock signal CK2, and the first pull-down control module is connected to the second node B and the third node C respectively.
  • the pull-up control module 500 is respectively connected to the first node A point and the third node C point.
  • the second pull-up module 700 is respectively connected to the third node C point and the output terminal; for example, it is used to pull up the potential of the output terminal (used to output the OUT signal).
  • the pull-down module 600 is respectively connected to the first node A point and the output terminal; it is used to pull down the potential of the output terminal.
  • One end of the storage capacitor C2 is connected to the second node B, and the other end is connected to the pull-down control module 400.
  • the first potential control module 100 includes a first thin film transistor T1 and a second thin film transistor T2;
  • the gate of the first thin film transistor T1 is connected to the first clock signal CK1, and the source of the first thin film transistor T1 is connected to the n-1th stage scan signal IN.
  • the gate of the second thin film transistor T2 is connected to the third clock signal CK3, the source of the second thin film transistor T2 is connected to the high potential signal VGH, the drain of the second thin film transistor T2, the first The drains of the thin film transistor T1 are all connected to the first node A point.
  • the second potential control module 200 includes a third thin film transistor T3 and a fourth thin film transistor T4;
  • the gate of the third thin film transistor T3 is connected to the first node A, and the source of the third thin film transistor T3 is connected to the high potential signal VGH.
  • the gate of the fourth thin film transistor T4 is connected to the third clock signal CK3, the source of the fourth thin film transistor T4 is connected to a low potential signal, the drain T3 of the third thin film transistor, the fourth thin film The drains of the transistors T4 are all connected to the second node.
  • the first pull-up module 300 includes a fifth thin film transistor T5 and a sixth thin film transistor T6;
  • the gate of the fifth thin film transistor T5 is connected to the second node B, and the source of the fifth thin film transistor T5 is connected to the high potential signal VGH.
  • the gate of the sixth thin film transistor T6 is connected to the second clock signal CK2, the source of the sixth thin film transistor T6 is connected to the drain of the fifth thin film transistor T5, and the sixth thin film transistor T6 The drain of is connected to the first node A point.
  • the pull-down control module 400 includes a seventh thin film transistor T7 and an eighth thin film transistor T8;
  • the gate of the seventh thin film transistor T7 is connected to the second node B, and the source of the seventh thin film transistor T7 is connected to the second clock signal CK2.
  • the gate of the eighth thin film transistor T8 is connected to the second clock signal CK2, the source of the eighth thin film transistor T8 is connected to the drain of the seventh thin film transistor T7, and the eighth thin film transistor T8 The drain of is connected to the third node C point.
  • One end of the storage capacitor C2 is connected to the second node B, and the other end of the first capacitor C2 is connected to the source of the eighth thin film transistor T8.
  • the pull-up control module 500 includes a ninth thin film transistor T9; the gate of the ninth thin film transistor T9 is connected to the first node A, and the source of the ninth thin film transistor T9 is connected to a high potential signal VGH , The drain of the ninth thin film transistor T9 is connected to the third node C.
  • the second pull-up module 700 includes a tenth thin film transistor T10; the gate of the tenth thin film transistor T10 is connected to the third node C, and the source of the tenth thin film transistor T10 is connected to a high potential signal VGH, the drain of the tenth thin film transistor T10 is connected to the output terminal.
  • the second pull-up module 700 further includes a second capacitor C3, one end of the second capacitor C3 is connected to the gate of the tenth thin film transistor T10, and the other end of the second capacitor C3 is connected to the tenth The source of the thin film transistor T10 is connected.
  • the pull-down module 600 includes an eleventh thin film transistor T11; the gate of the eleventh thin film transistor T11 is connected to the first node A, and the source of the eleventh thin film transistor T11 is connected to a low potential signal VGL, the drain of the eleventh thin film transistor T11 is connected to the output terminal.
  • the pull-down module further includes a third capacitor C1, one end of the third capacitor C1 is connected to the gate of the eleventh thin film transistor T11, and one end of the third capacitor C1 is connected to the second clock signal CK2.
  • CK1, CK2, and CK3 are the first clock signal, the second clock signal, and the third clock signal respectively.
  • IN is the n-1th level scan signal
  • OUT is the current level scan signal, that is, the output terminal outputs signal of.
  • the first thin film transistor to the eleventh thin film transistor are all PMOS tubes, that is, P-type MOS tubes.
  • t1 period (that is, the first stage): CK1 is low, CK2, CK3, and IN are all high. At this time, T1, T5, and T7 are turned on, and other PMOS transistors are turned off. The output terminal (OUT) maintains the previous low state.
  • t2 period (that is, the second stage): CK2 is low, CK1, CK3, and IN are all high. At this time, T5, T6, T7, T8, T10 are turned on, other PMOS transistors are turned off, and the output is high Level.
  • Period t3 (that is, the third stage): CK3 is low, CK1, CK2, and IN are high. At this time, T2, T4, T5, and T7 are turned on, other PMOS transistors are turned off, and the output terminal remains high.
  • Period t4 CK1 is low level, CK2, CK3, IN are high level, GOA repeats the process of the first stage, the output terminal maintains the previous state and outputs high level.
  • Time period t5 CK2 is low level, CK1, CK3, IN are high level, GOA repeats the second stage process, and the output terminal outputs high level;
  • Period t6 CK3 is low level, CK1, CK2, IN are high level, GOA repeats the third stage process, and the output terminal outputs high level;
  • CK1, IN are low level
  • CK2, CK3 are high level
  • T1, T3, T9, T11 are open, and the output terminal outputs low level.
  • t8 period CK2, IN are low level, CK1, CK3 are high level, at this time, T3, T6, T8, T9, T11 are turned on, other PMOS transistors are turned off, and the output terminal outputs low level;
  • Time period t9 CK3 and IN are low level, CK1 and CK2 are high level. At this time, T2, T4, T5, T7 are turned on, other PMOS transistors are turned off, and the OUT terminal remains low. The subsequent stage repeats the period from t7 to t9, and the output terminal continues to output low level.
  • the GOA circuit of the present invention adopts a relatively simple structure and can also output scan signals to meet actual driving requirements.
  • OUT1 to OUT3 represent the scan signals of the first to third-level GOA units, respectively.
  • the GOA circuit of the present invention by improving the existing GOA circuit, realizes the output of the scan signal due to the use of fewer thin film transistors, thus saving the number of thin film transistors, and simplifies the structure of the GOA circuit, thereby reducing The production cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

A GOA circuit and a display device. The GOA circuit comprises m cascaded GOA units, and the nth-level GOA unit comprises: a first potential control module (100), connected to the (n-1)th-level scan signal (IN), a first clock signal (CK1), and a third clock signal (CK3); a second potential control module (200) connected to the third clock signal (CK3), the second potential control module (200) being separately connected to a first node (A) and a second node (B); a first pull-up module (300) connected to a second clock signal (CK2), the first pull-up module (300) being separately connected to the second node (B) and the first node (A); a pull-down control module (400) connected to the second clock signal (CK2), the first pull-down control module (400) being separately connected to the second node (B) and a third node (C); a pull-up control module (500), separately connected to the first node (A) and the third node (C); and a second pull-up module (700), separately connected to the third node (C) and an output end. According to the GOA circuit, the manufacturing process can be simplified and production costs are reduced.

Description

一种GOA电路及显示装置A GOA circuit and display device 技术领域Technical field
本发明涉及显示技术领域，特别是涉及一种GOA电路及显示装置。The invention relates to the field of display technology, in particular to a GOA circuit and a display device.
背景技术Background technique
目前显示面板（比如有源矩阵有机发光二极体面板（AMOLED，Active-matrix organic light-emitting diode）的扫描线的驱动是由外接集成电路来实现的，外接集成电路可以控制各级行扫描线的逐级开启，而采用GOA(Gate Driver on Array)方法，可以将行扫描驱动电路集成在显示面板基板上，能够减少外接芯片的数量，从而降低了显示面板的生产成本，并且能够实现显示装置的窄边框化。Current display panels (such as active matrix organic light-emitting diode panels (AMOLED, Active-matrix) The scanning line of organic light-emitting diode) is driven by an external integrated circuit. The external integrated circuit can control the step-by-step turn-on of the scanning lines at all levels, and the GOA (Gate The Driver on Array method can integrate the line scan driving circuit on the display panel substrate, which can reduce the number of external chips, thereby reducing the production cost of the display panel, and can realize the narrow frame of the display device.
然而，现有的GOA电路的结构较复杂，且需要较多的薄膜晶体管，因此导致制程工艺比较复杂，增大了生产成本。However, the structure of the existing GOA circuit is relatively complex and requires more thin film transistors, which results in a relatively complicated manufacturing process and increases production costs.
因此，有必要提供一种GOA电路及显示装置，以解决现有技术所存在的问题。Therefore, it is necessary to provide a GOA circuit and a display device to solve the problems in the prior art.
技术问题technical problem
本发明的目的在于提供一种GOA电路及显示装置，能够简化制程工艺，降低生产成本。The purpose of the present invention is to provide a GOA circuit and a display device, which can simplify the manufacturing process and reduce the production cost.
技术解决方案Technical solutions
为解决上述技术问题，本发明提供一种GOA电路，其m个级联的GOA单元，第n级GOA单元包括：In order to solve the above technical problems, the present invention provides a GOA circuit with m cascaded GOA units, and the nth level GOA unit includes:
第一电位控制模块，接入第n-1级扫描信号、第一时钟信号以及第三时钟信号；The first potential control module is connected to the n-1th level scanning signal, the first clock signal and the third clock signal;
第二电位控制模块，接入所述第三时钟信号，所述第二电位控制模块分别与第一节点和第二节点连接；The second potential control module is connected to the third clock signal, and the second potential control module is respectively connected to the first node and the second node;
第一上拉模块，接入第二时钟信号，所述第一上拉模块分别与所述第二节点和所述第一节点连接；The first pull-up module is connected to a second clock signal, and the first pull-up module is respectively connected to the second node and the first node;
下拉控制模块，接入所述第二时钟信号，所述第一下拉控制模块分别与所述第二节点和第三节点连接；A pull-down control module to access the second clock signal, and the first pull-down control module is respectively connected to the second node and the third node;
上拉控制模块，分别与所述第一节点和所述第三节点连接；A pull-up control module connected to the first node and the third node respectively;
第二上拉模块，分别与所述第三节点和输出端连接；The second pull-up module is respectively connected with the third node and the output terminal;
下拉模块，分别与所述第一节点和输出端连接；Pull-down modules, respectively connected to the first node and the output terminal;
存储电容，其一端与所述第二节点连接，所述存储电容的另一端与所述下拉控制模块连接，其中m≥n≥1。One end of the storage capacitor is connected to the second node, and the other end of the storage capacitor is connected to the pull-down control module, where m≥n≥1.
有益效果Beneficial effect
本发明的GOA电路，通过对现有的GOA电路进行改进，由于采用较少的薄膜晶体管便实现了扫描信号的输出，因此节省了薄膜晶体管的数量，还简化了GOA电路的结构，从而降低了生产成本。The GOA circuit of the present invention improves the existing GOA circuit, and realizes the output of the scan signal by using fewer thin film transistors, thus saving the number of thin film transistors and simplifying the structure of the GOA circuit, thereby reducing Cost of production.
附图说明Description of the drawings
图1为本发明GOA电路的结构示意图；Figure 1 is a schematic diagram of the structure of the GOA circuit of the present invention;
图2为本发明GOA电路的时序图；Figure 2 is a timing diagram of the GOA circuit of the present invention;
图3为本发明GOA电路的仿真图。Figure 3 is a simulation diagram of the GOA circuit of the present invention.
本发明的实施方式Embodiments of the invention
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。The description of the following embodiments refers to the attached drawings to illustrate specific embodiments that the present invention can be implemented. The directional terms mentioned in the present invention, such as "up", "down", "front", "rear", "left", "right", "in", "out", "side", etc., are for reference only The direction of the additional schema. Therefore, the directional terms used are used to describe and understand the present invention, rather than to limit the present invention. In the figure, units with similar structures are indicated by the same reference numerals.
如图1所示，本发明的GOA电路包括m个级联的GOA单元，第n级GOA单元包括第一电位控制模块100、第二电位控制模块200、第一上拉模块300、下拉控制模块400、上拉控制模块500、第二上拉模块700、下拉模块600、存储电容C2，其中m≥n≥1。As shown in FIG. 1, the GOA circuit of the present invention includes m cascaded GOA units, and the nth level GOA unit includes a first potential control module 100, a second potential control module 200, a first pull-up module 300, and a pull-down control module. 400. The pull-up control module 500, the second pull-up module 700, the pull-down module 600, and the storage capacitor C2, where m≥n≥1.
第一电位控制模块100接入第n-1级扫描信号(IN)、第一时钟信号CK1以及第三时钟信号CK3；比如用于根据第n-1级扫描信号(IN)、第一时钟信号CK1以及第三时钟信号CK3控制所述第一节点A点的电位。The first potential control module 100 is connected to the n-1th level scan signal (IN), the first clock signal CK1 and the third clock signal CK3; for example, it is used to respond to the n-1th level scan signal (IN) and the first clock signal. CK1 and the third clock signal CK3 control the potential of the first node A point.
第二电位控制模块200接入所述第三时钟信号CK3，所述第二电位控制模块200分别与所述第一节点A点和第二节点B点连接，比如用于根据所述第一节点A点的电位和所述第三时钟信号CK3控制所述第二节点B点的电位。The second potential control module 200 is connected to the third clock signal CK3, and the second potential control module 200 is respectively connected to the first node A and the second node B, for example, according to the first node The potential of point A and the third clock signal CK3 control the potential of point B of the second node.
第一上拉模块300接入第二时钟信号CK2，所述第一上拉模块300分别与所述第二节点B点和所述第一节点A点连接。The first pull-up module 300 is connected to the second clock signal CK2, and the first pull-up module 300 is respectively connected to the second node B point and the first node A point.
下拉控制模块400接入所述第二时钟信号CK2，所述第一下拉控制模块分别与所述第二节点B点和第三节点C点连接。The pull-down control module 400 accesses the second clock signal CK2, and the first pull-down control module is connected to the second node B and the third node C respectively.
上拉控制模块500分别与所述第一节点A点和所述第三节点C点连接。The pull-up control module 500 is respectively connected to the first node A point and the third node C point.
第二上拉模块700分别与所述第三节点C点和输出端连接；比如用于上拉输出端(用于输出OUT信号)的电位。The second pull-up module 700 is respectively connected to the third node C point and the output terminal; for example, it is used to pull up the potential of the output terminal (used to output the OUT signal).
下拉模块600分别与所述第一节点A点和输出端连接；用于下拉所述输出端的电位。The pull-down module 600 is respectively connected to the first node A point and the output terminal; it is used to pull down the potential of the output terminal.
存储电容C2的一端与所述第二节点B点连接，另一端与所述下拉控制模块400连接。One end of the storage capacitor C2 is connected to the second node B, and the other end is connected to the pull-down control module 400.
其中所述第一电位控制模块100包括第一薄膜晶体管T1和第二薄膜晶体管T2；The first potential control module 100 includes a first thin film transistor T1 and a second thin film transistor T2;
所述第一薄膜晶体管T1的栅极接入第一时钟信号CK1，所述第一薄膜晶体管T1的源极接入第n-1级扫描信号IN。The gate of the first thin film transistor T1 is connected to the first clock signal CK1, and the source of the first thin film transistor T1 is connected to the n-1th stage scan signal IN.
所述第二薄膜晶体管T2的栅极接入第三时钟信号CK3，所述第二薄膜晶体管T2的源极接入高电位信号VGH，所述第二薄膜晶体管T2的漏极、所述第一薄膜晶体管T1的漏极均与所述第一节点A点连接。The gate of the second thin film transistor T2 is connected to the third clock signal CK3, the source of the second thin film transistor T2 is connected to the high potential signal VGH, the drain of the second thin film transistor T2, the first The drains of the thin film transistor T1 are all connected to the first node A point.
所述第二电位控制模块200包括第三薄膜晶体管T3和第四薄膜晶体管T4；The second potential control module 200 includes a third thin film transistor T3 and a fourth thin film transistor T4;
所述第三薄膜晶体管T3的栅极与所述第一节点A点连接，所述第三薄膜晶体管T3的源极接入高电位信号VGH。The gate of the third thin film transistor T3 is connected to the first node A, and the source of the third thin film transistor T3 is connected to the high potential signal VGH.
所述第四薄膜晶体管T4的栅极接入第三时钟信号CK3，所述第四薄膜晶体管T4的源极接入低电位信号，所述第三薄膜晶体管的漏极T3、所述第四薄膜晶体管T4的漏极均与所述第二节点连接。The gate of the fourth thin film transistor T4 is connected to the third clock signal CK3, the source of the fourth thin film transistor T4 is connected to a low potential signal, the drain T3 of the third thin film transistor, the fourth thin film The drains of the transistors T4 are all connected to the second node.
所述第一上拉模块300包括第五薄膜晶体管T5以及第六薄膜晶体管T6；The first pull-up module 300 includes a fifth thin film transistor T5 and a sixth thin film transistor T6;
所述第五薄膜晶体管T5的栅极与所述第二节点B点连接，所述第五薄膜晶体管T5的源极接入高电位信号VGH。The gate of the fifth thin film transistor T5 is connected to the second node B, and the source of the fifth thin film transistor T5 is connected to the high potential signal VGH.
所述第六薄膜晶体管T6的栅极接入所述第二时钟信号CK2，所述第六薄膜晶体管T6的源极与所述第五薄膜晶体管T5的漏极连接，所述第六薄膜晶体管T6的漏极与所述第一节点A点连接。The gate of the sixth thin film transistor T6 is connected to the second clock signal CK2, the source of the sixth thin film transistor T6 is connected to the drain of the fifth thin film transistor T5, and the sixth thin film transistor T6 The drain of is connected to the first node A point.
所述下拉控制模块400包括第七薄膜晶体管T7以及第八薄膜晶体管T8；The pull-down control module 400 includes a seventh thin film transistor T7 and an eighth thin film transistor T8;
所述第七薄膜晶体管T7的栅极与所述第二节点B点连接，所述第七薄膜晶体管T7的源极与所述第二时钟信号CK2连接。The gate of the seventh thin film transistor T7 is connected to the second node B, and the source of the seventh thin film transistor T7 is connected to the second clock signal CK2.
所述第八薄膜晶体管T8的栅极与所述第二时钟信号CK2连接，所述第八薄膜晶体管T8的源极与所述第七薄膜晶体管T7的漏极连接，所述第八薄膜晶体管T8的漏极与所述第三节点C点连接。The gate of the eighth thin film transistor T8 is connected to the second clock signal CK2, the source of the eighth thin film transistor T8 is connected to the drain of the seventh thin film transistor T7, and the eighth thin film transistor T8 The drain of is connected to the third node C point.
所述存储电容C2的一端与所述第二节点B点连接，所述第一电容C2的另一端与所述第八薄膜晶体管T8的源极连接。One end of the storage capacitor C2 is connected to the second node B, and the other end of the first capacitor C2 is connected to the source of the eighth thin film transistor T8.
所述上拉控制模块500包括第九薄膜晶体管T9；所述第九薄膜晶体管T9的栅极与所述第一节点A点连接，所述第九薄膜晶体管T9的源极接入高电位信号VGH，所述第九薄膜晶体管T9的漏极与所述第三节点C点连接。The pull-up control module 500 includes a ninth thin film transistor T9; the gate of the ninth thin film transistor T9 is connected to the first node A, and the source of the ninth thin film transistor T9 is connected to a high potential signal VGH , The drain of the ninth thin film transistor T9 is connected to the third node C.
所述第二上拉模块700包括第十薄膜晶体管T10；所述第十薄膜晶体管T10的栅极与所述第三节点C点连接，所述第十薄膜晶体管T10的源极接入高电位信号VGH，所述第十薄膜晶体管T10的漏极与输出端连接。The second pull-up module 700 includes a tenth thin film transistor T10; the gate of the tenth thin film transistor T10 is connected to the third node C, and the source of the tenth thin film transistor T10 is connected to a high potential signal VGH, the drain of the tenth thin film transistor T10 is connected to the output terminal.
所述第二上拉模块700还包括第二电容C3，所述第二电容C3的一端与所述第十薄膜晶体管T10的栅极连接，所述第二电容C3的另一端与所述第十薄膜晶体管T10的源极连接。The second pull-up module 700 further includes a second capacitor C3, one end of the second capacitor C3 is connected to the gate of the tenth thin film transistor T10, and the other end of the second capacitor C3 is connected to the tenth The source of the thin film transistor T10 is connected.
所述下拉模块600包括第十一薄膜晶体管T11；所述第十一薄膜晶体管T11的栅极与所述第一节点A点连接，所述第十一薄膜晶体管T11的源极接入低电位信号VGL，所述第十一薄膜晶体管T11的漏极与所述输出端连接。The pull-down module 600 includes an eleventh thin film transistor T11; the gate of the eleventh thin film transistor T11 is connected to the first node A, and the source of the eleventh thin film transistor T11 is connected to a low potential signal VGL, the drain of the eleventh thin film transistor T11 is connected to the output terminal.
所述下拉模块还包括第三电容C1，所述第三电容C1的一端与所述第十一薄膜晶体管T11的栅极连接，所述第三电容C1的一端接入第二时钟信号CK2。The pull-down module further includes a third capacitor C1, one end of the third capacitor C1 is connected to the gate of the eleventh thin film transistor T11, and one end of the third capacitor C1 is connected to the second clock signal CK2.
如图2所示，CK1、CK2、CK3分别为第一时钟信号、第二时钟信号以及第三时钟信号，IN为第n-1级扫描信号，OUT为本级扫描信号，也即输出端输出的信号。As shown in Figure 2, CK1, CK2, and CK3 are the first clock signal, the second clock signal, and the third clock signal respectively. IN is the n-1th level scan signal, and OUT is the current level scan signal, that is, the output terminal outputs signal of.
其中第一薄膜晶体管至第十一薄膜晶体管都为PMOS管，也即P型MOS管。Among them, the first thin film transistor to the eleventh thin film transistor are all PMOS tubes, that is, P-type MOS tubes.
电路工作前，先输入低电平的CK3，使得第二节点B点的电位为低电平。Before the circuit works, input the low level CK3 first, so that the potential of the second node B point is low.
如图2和3所示，t1时段(也即第一阶段)：CK1为低电平，CK2、CK3、IN均为高电平，此时，T1、T5、T7打开，其他PMOS管关闭，输出端（OUT）保持之前的低电平状态。As shown in Figures 2 and 3, t1 period (that is, the first stage): CK1 is low, CK2, CK3, and IN are all high. At this time, T1, T5, and T7 are turned on, and other PMOS transistors are turned off. The output terminal (OUT) maintains the previous low state.
t2时段(也即第二阶段)：CK2为低电平、CK1、CK3、IN均为高电平，此时，T5、T6、T7、T8、T10打开，其他PMOS管关闭，输出端输出高电平。t2 period (that is, the second stage): CK2 is low, CK1, CK3, and IN are all high. At this time, T5, T6, T7, T8, T10 are turned on, other PMOS transistors are turned off, and the output is high Level.
t3时段(也即第三阶段)：CK3为低电平，CK1、CK2、IN为高电平，此时，T2、T4、T5、T7打开，其他PMOS管关闭，输出端保持高电平。Period t3 (that is, the third stage): CK3 is low, CK1, CK2, and IN are high. At this time, T2, T4, T5, and T7 are turned on, other PMOS transistors are turned off, and the output terminal remains high.
t4时段：CK1为低电平、CK2、CK3、IN为高电平，GOA重复阶第一阶段的过程，输出端保持之前的状态，输出高电平。Period t4: CK1 is low level, CK2, CK3, IN are high level, GOA repeats the process of the first stage, the output terminal maintains the previous state and outputs high level.
t5时段：CK2为低电平、CK1、CK3、IN为高电平，GOA重复阶第二阶段的过程，输出端输出高电平；Time period t5: CK2 is low level, CK1, CK3, IN are high level, GOA repeats the second stage process, and the output terminal outputs high level;
t6时段：CK3为低电平，CK1、CK2、IN为高电平，GOA重复第三阶段的过程，输出端输出高电平；Period t6: CK3 is low level, CK1, CK2, IN are high level, GOA repeats the third stage process, and the output terminal outputs high level;
t7时段：CK1、IN为低电平，CK2、CK3为高电平，此时，T1、T3、T9、T11打开，输出端输出低电平.t7 period: CK1, IN are low level, CK2, CK3 are high level, at this time, T1, T3, T9, T11 are open, and the output terminal outputs low level.
t8时段：CK2、IN为低电平、CK1、CK3为高电平，此时，T3、T6、T8、T9、T11打开，其他PMOS管关闭，输出端输出低电平；t8 period: CK2, IN are low level, CK1, CK3 are high level, at this time, T3, T6, T8, T9, T11 are turned on, other PMOS transistors are turned off, and the output terminal outputs low level;
t9时段：CK3、IN为低电平，CK1、CK2为高电平，此时，T2、T4、T5、T7打开，其他PMOS管关闭，OUT端保持低电平。后续阶段重复t7到t9时段，输出端持续输出低电平。Time period t9: CK3 and IN are low level, CK1 and CK2 are high level. At this time, T2, T4, T5, T7 are turned on, other PMOS transistors are turned off, and the OUT terminal remains low. The subsequent stage repeats the period from t7 to t9, and the output terminal continues to output low level.
从图3的仿真图可以看出，本发明的GOA电路采用较为简单的结构，也能够输出扫描信号，满足实际驱动需求。其中OUT1至OUT3分别代表第1至3级GOA单元的扫描信号。It can be seen from the simulation diagram of FIG. 3 that the GOA circuit of the present invention adopts a relatively simple structure and can also output scan signals to meet actual driving requirements. Among them, OUT1 to OUT3 represent the scan signals of the first to third-level GOA units, respectively.
本发明的GOA电路，通过对现有的GOA电路进行改进，由于采用较少的薄膜晶体管便实现了扫描信号的输出，因此节省了薄膜晶体管的数量，此外还简化了GOA电路的结构，从而降低了生产成本。The GOA circuit of the present invention, by improving the existing GOA circuit, realizes the output of the scan signal due to the use of fewer thin film transistors, thus saving the number of thin film transistors, and simplifies the structure of the GOA circuit, thereby reducing The production cost.
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示意性实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples", or "some examples" etc. means to incorporate the implementation The specific features, structures, materials or characteristics described by the examples or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above-mentioned terms does not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.
尽管已经示出和描述了本发明的实施例，本领域的普通技术人员可以理解：在不脱离本发明的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由权利要求及其等同物限定。Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and modifications can be made to these embodiments without departing from the principle and purpose of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims (11)

  1. 一种GOA电路，其特征在于，包括m个级联的GOA单元，第n级GOA单元包括：A GOA circuit, characterized in that it includes m cascaded GOA units, and the nth level GOA unit includes:
    第一电位控制模块，接入第n-1级扫描信号、第一时钟信号以及第三时钟信号；The first potential control module is connected to the n-1th level scanning signal, the first clock signal and the third clock signal;
    第二电位控制模块，接入所述第三时钟信号，所述第二电位控制模块分别与第一节点和第二节点连接；The second potential control module is connected to the third clock signal, and the second potential control module is respectively connected to the first node and the second node;
    第一上拉模块，接入第二时钟信号，所述第一上拉模块分别与所述第二节点和所述第一节点连接；The first pull-up module is connected to a second clock signal, and the first pull-up module is respectively connected to the second node and the first node;
    下拉控制模块，接入所述第二时钟信号，所述第一下拉控制模块分别与所述第二节点和第三节点连接；A pull-down control module to access the second clock signal, and the first pull-down control module is respectively connected to the second node and the third node;
    上拉控制模块，分别与所述第一节点和所述第三节点连接；A pull-up control module connected to the first node and the third node respectively;
    第二上拉模块，与所述第三节点连接；The second pull-up module is connected to the third node;
    下拉模块，分别与所述第一节点和输出端连接；Pull-down modules, respectively connected to the first node and the output terminal;
    存储电容，其一端与所述第二节点连接，所述存储电容的另一端与所述下拉控制模块连接，其中m≥n≥1。One end of the storage capacitor is connected to the second node, and the other end of the storage capacitor is connected to the pull-down control module, where m≥n≥1.
  2. 根据权利要求1所述的GOA电路，其特征在于，The GOA circuit according to claim 1, wherein:
    所述第一电位控制模块包括第一薄膜晶体管和第二薄膜晶体管；The first potential control module includes a first thin film transistor and a second thin film transistor;
    所述第一薄膜晶体管的栅极接入所述第一时钟信号，所述第一薄膜晶体管的源极接入所述第n-1级扫描信号；The gate of the first thin film transistor is connected to the first clock signal, and the source of the first thin film transistor is connected to the n-1th level scan signal;
    所述第二薄膜晶体管的栅极接入所述第三时钟信号，所述第二薄膜晶体管的源极接入高电位信号，所述第二薄膜晶体管的漏极和所述第一薄膜晶体管的漏极均与所述第一节点连接。The gate of the second thin film transistor is connected to the third clock signal, the source of the second thin film transistor is connected to a high potential signal, and the drain of the second thin film transistor is connected to the first thin film transistor. The drains are all connected to the first node.
  3. 根据权利要求1所述的GOA电路，其特征在于，The GOA circuit according to claim 1, wherein:
    所述第二电位控制模块包括第三薄膜晶体管和第四薄膜晶体管；The second potential control module includes a third thin film transistor and a fourth thin film transistor;
    所述第三薄膜晶体管的栅极与所述第一节点连接，所述第三薄膜晶体管的源极接入高电位信号；The gate of the third thin film transistor is connected to the first node, and the source of the third thin film transistor is connected to a high potential signal;
    所述第四薄膜晶体管的栅极接入所述第三时钟信号，所述第四薄膜晶体管的源极接入低电位信号，所述第三薄膜晶体管的漏极和所述第四薄膜晶体管的漏极均与所述第二节点连接。The gate of the fourth thin film transistor is connected to the third clock signal, the source of the fourth thin film transistor is connected to a low potential signal, and the drain of the third thin film transistor is connected to the fourth thin film transistor. The drains are all connected to the second node.
  4. 根据权利要求1所述的GOA电路，其特征在于，The GOA circuit according to claim 1, wherein:
    所述第一上拉模块包括第五薄膜晶体管以及第六薄膜晶体管；The first pull-up module includes a fifth thin film transistor and a sixth thin film transistor;
    所述第五薄膜晶体管的栅极与所述第二节点连接，所述第五薄膜晶体管的源极接入高电位信号；The gate of the fifth thin film transistor is connected to the second node, and the source of the fifth thin film transistor is connected to a high potential signal;
    所述第六薄膜晶体管的栅极接入所述第二时钟信号，所述第六薄膜晶体管的源极与所述第五薄膜晶体管的漏极连接，所述第六薄膜晶体管的漏极与所述第一节点连接。The gate of the sixth thin film transistor is connected to the second clock signal, the source of the sixth thin film transistor is connected to the drain of the fifth thin film transistor, and the drain of the sixth thin film transistor is connected to the drain of the fifth thin film transistor. The first node connection.
  5. 根据权利要求1所述的GOA电路，其特征在于，The GOA circuit according to claim 1, wherein:
    所述下拉控制模块包括第七薄膜晶体管以及第八薄膜晶体管；The pull-down control module includes a seventh thin film transistor and an eighth thin film transistor;
    所述第七薄膜晶体管的栅极与所述第二节点连接，所述第七薄膜晶体管的源极与所述第二时钟信号连接；The gate of the seventh thin film transistor is connected to the second node, and the source of the seventh thin film transistor is connected to the second clock signal;
    所述第八薄膜晶体管的栅极与所述第二时钟信号连接，所述第八薄膜晶体管的源极与所述第七薄膜晶体管的漏极连接，所述第八薄膜晶体管的漏极与所述第三节点连接。The gate of the eighth thin film transistor is connected to the second clock signal, the source of the eighth thin film transistor is connected to the drain of the seventh thin film transistor, and the drain of the eighth thin film transistor is connected to the The third node connection.
  6. 根据权利要求5所述的GOA电路，其特征在于，The GOA circuit of claim 5, wherein:
    所述存储电容的一端与所述第二节点连接，所述第一电容的另一端与所述第八薄膜晶体管的源极连接。One end of the storage capacitor is connected to the second node, and the other end of the first capacitor is connected to the source of the eighth thin film transistor.
  7. 根据权利要求1所述的GOA电路，其特征在于，The GOA circuit according to claim 1, wherein:
    所述上拉控制模块包括第九薄膜晶体管；The pull-up control module includes a ninth thin film transistor;
    所述第九薄膜晶体管的栅极与所述第一节点连接，所述第九薄膜晶体管的源极接入高电位信号，所述第九薄膜晶体管的漏极与所述第三节点连接。The gate of the ninth thin film transistor is connected to the first node, the source of the ninth thin film transistor is connected to a high potential signal, and the drain of the ninth thin film transistor is connected to the third node.
  8. 根据权利要求1所述的GOA电路，其特征在于，The GOA circuit according to claim 1, wherein:
    所述第二上拉模块包括第十薄膜晶体管；The second pull-up module includes a tenth thin film transistor;
    所述第十薄膜晶体管的栅极与所述第三节点连接，所述第十薄膜晶体管的源极接入高电位信号，所述第十薄膜晶体管的漏极与输出端连接。The gate of the tenth thin film transistor is connected to the third node, the source of the tenth thin film transistor is connected to a high potential signal, and the drain of the tenth thin film transistor is connected to the output terminal.
  9. 根据权利要求8所述的GOA电路，其特征在于，The GOA circuit according to claim 8, wherein:
    所述第二上拉模块还包括第二电容，所述第二电容的一端与所述第十薄膜晶体管的栅极连接，所述第二电容的另一端与所述第十薄膜晶体管的源极连接。The second pull-up module further includes a second capacitor, one end of the second capacitor is connected to the gate of the tenth thin film transistor, and the other end of the second capacitor is connected to the source of the tenth thin film transistor. connection.
  10. 根据权利要求1所述的GOA电路，其特征在于，The GOA circuit according to claim 1, wherein:
    所述下拉模块包括第十一薄膜晶体管；The pull-down module includes an eleventh thin film transistor;
    所述第十一薄膜晶体管的栅极与所述第一节点连接，所述第十一薄膜晶体管的源极接入低电位信号，所述第十一薄膜晶体管的漏极与所述输出端连接。The gate of the eleventh thin film transistor is connected to the first node, the source of the eleventh thin film transistor is connected to a low potential signal, and the drain of the eleventh thin film transistor is connected to the output terminal .
  11. 一种显示装置，其特征在于，包括如权利要求1所述的GOA电路。A display device, characterized in that it comprises the GOA circuit according to claim 1.
PCT/CN2019/106224 2019-04-29 2019-09-17 Goa circuit and display device WO2020220565A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910356454.5A CN109961745B (en) 2019-04-29 2019-04-29 GOA circuit
CN201910356454.5 2019-04-29

Publications (1)

Publication Number Publication Date
WO2020220565A1 true WO2020220565A1 (en) 2020-11-05

Family

ID=67026846

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/106224 WO2020220565A1 (en) 2019-04-29 2019-09-17 Goa circuit and display device

Country Status (2)

Country Link
CN (1) CN109961745B (en)
WO (1) WO2020220565A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109961745B (en) * 2019-04-29 2020-11-24 武汉华星光电半导体显示技术有限公司 GOA circuit
CN111508415B (en) * 2020-04-28 2021-09-03 Tcl华星光电技术有限公司 Grid array substrate driving circuit
US11315473B2 (en) 2020-06-16 2022-04-26 Tcl China Star Optoelectronics Technology Co., Ltd. Gate-on-array driving circuit
CN111798788B (en) * 2020-07-13 2022-09-20 昆山国显光电有限公司 Light emission control circuit, light emission control driver, and display panel
CN112150960A (en) * 2020-09-17 2020-12-29 福建华佳彩有限公司 Dual-output GIP circuit

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2360651A (en) * 1998-10-21 2001-09-26 Lg Philips Lcd Co Ltd A shift register for driving an LCD pixel row
CN102708799A (en) * 2012-05-31 2012-10-03 京东方科技集团股份有限公司 Shift register unit, shift register circuit, array substrate and display device
CN105741744A (en) * 2016-05-12 2016-07-06 京东方科技集团股份有限公司 Shifting register unit, grid driving circuit and display device
CN106710544A (en) * 2016-12-12 2017-05-24 武汉华星光电技术有限公司 Shift register circuit, gate drive circuit and display device
CN107993615A (en) * 2017-12-06 2018-05-04 武汉华星光电半导体显示技术有限公司 GOA circuit units, GOA circuits and display panel
CN108039150A (en) * 2017-11-16 2018-05-15 武汉华星光电半导体显示技术有限公司 Shift register circuit and shifting deposit unit
CN109961745A (en) * 2019-04-29 2019-07-02 武汉华星光电半导体显示技术有限公司 A kind of GOA circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777386B (en) * 2010-01-06 2013-04-24 友达光电股份有限公司 Shift register circuit
TWI473059B (en) * 2013-05-28 2015-02-11 Au Optronics Corp Shift register circuit
CN103714792B (en) * 2013-12-20 2015-11-11 京东方科技集团股份有限公司 A kind of shift register cell, gate driver circuit and display device
CN105976751A (en) * 2016-07-28 2016-09-28 武汉华星光电技术有限公司 Scan drive circuit and planar display device provided with same
KR102652815B1 (en) * 2016-09-30 2024-04-01 엘지디스플레이 주식회사 Shift register and display device using the same
KR101882435B1 (en) * 2016-10-05 2018-08-24 실리콘 디스플레이 (주) Shift register
CN106531048B (en) * 2016-11-29 2020-03-27 京东方科技集团股份有限公司 Shift register, grid driving circuit, display panel and driving method
CN107293269B (en) * 2017-08-15 2019-06-21 京东方科技集团股份有限公司 A kind of shift register and its driving method, gate driving circuit
CN109637430B (en) * 2019-02-21 2020-12-25 合肥鑫晟光电科技有限公司 Shift register and driving method thereof, gate drive circuit and display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2360651A (en) * 1998-10-21 2001-09-26 Lg Philips Lcd Co Ltd A shift register for driving an LCD pixel row
CN102708799A (en) * 2012-05-31 2012-10-03 京东方科技集团股份有限公司 Shift register unit, shift register circuit, array substrate and display device
CN105741744A (en) * 2016-05-12 2016-07-06 京东方科技集团股份有限公司 Shifting register unit, grid driving circuit and display device
CN106710544A (en) * 2016-12-12 2017-05-24 武汉华星光电技术有限公司 Shift register circuit, gate drive circuit and display device
CN108039150A (en) * 2017-11-16 2018-05-15 武汉华星光电半导体显示技术有限公司 Shift register circuit and shifting deposit unit
CN107993615A (en) * 2017-12-06 2018-05-04 武汉华星光电半导体显示技术有限公司 GOA circuit units, GOA circuits and display panel
CN109961745A (en) * 2019-04-29 2019-07-02 武汉华星光电半导体显示技术有限公司 A kind of GOA circuit

Also Published As

Publication number Publication date
CN109961745A (en) 2019-07-02
CN109961745B (en) 2020-11-24

Similar Documents

Publication Publication Date Title
WO2020220565A1 (en) Goa circuit and display device
CN106683631B (en) The GOA circuits and display device of a kind of IGZO thin film transistor (TFT)s
WO2019095435A1 (en) Goa circuit
JP2018507433A (en) GOA circuit used in liquid crystal display device
WO2017096658A1 (en) Goa circuit based on ltps semiconductor thin film transistor
WO2014166251A1 (en) Shift register unit and gate drive circuit
WO2018120330A1 (en) Gate drive circuit, and liquid crystal display
WO2017181481A1 (en) Cmos goa circuit for reducing load of clock signal
WO2021203508A1 (en) Goa circuit and display panel
WO2018120328A1 (en) Drive method and drive device for goa circuit
WO2013152604A1 (en) Shift register unit and driving method for the same, shift register, and display device
WO2022007147A1 (en) Goa circuit and display panel
WO2017096704A1 (en) Goa circuit based on ltps semiconductor thin film transistor
WO2019095492A1 (en) Shift register circuit and shift register unit
WO2018107533A1 (en) Gate drive circuit, driving method and display device
WO2017107294A1 (en) Goa circuit and liquid crystal display device
WO2020164193A1 (en) Goa circuit and display panel
CN110060639B (en) Array substrate
WO2020206792A1 (en) Goa circuit and display panel
WO2020206816A1 (en) Goa circuit and display panel
WO2020077897A1 (en) Goa drive circuit and display panel
WO2020224133A1 (en) Goa circuit, display panel and display apparatus
WO2020220480A1 (en) Goa circuit
WO2021012313A1 (en) Gate driving circuit
WO2020215435A1 (en) Goa circuit and display panel

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19927015

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19927015

Country of ref document: EP

Kind code of ref document: A1