TWI769910B - Gate of array driving circuit and display panel including the same - Google Patents

Abstract

A gate of array driving circuit and a display panel including the same are disclosed. The gate of array driving circuit and the source driving circuit are disposed on the same side of the display area, so as to drive the plurality of pixels in the display area. The gate of array driving circuit includes a plurality of shift registers. The plurality of shift registers are arranged as multiple sets of serial circuits. Among the plurality of shift registers, the shift registers with the same pull-up signal transmission path are arranged adjacently in the same group of serial circuits.

Description

Gate drive circuit and display panel including the same

The present invention relates to a gate drive circuit and a display panel including the same, and more particularly to a gate drive circuit and a display including the gate drive circuit which reduces the circuit configuration width by grouping the shift registers to achieve a narrow frame design panel.

In the competition of the panel industry, light, thin and short products have always been the design goals pursued by companies. For display panels, in order to achieve a narrow frame or no frame design, integrating the gate driver chip on the glass substrate seems to be a kind of feasible solution. Therefore, under the consideration of design and cost, the application of Gate Driver on Array (GOA) has become a technical topic that various manufacturers are scrambling to study.

In order to reduce the width of the peripheral circuits of the display panel, various changes or simplifications can be made in the design of circuit components to save the installation space. However, many simplified circuits may cause various abnormalities or abnormality in the operation of the display panel. The poor display effect reduces the display quality of the device on the contrary. How to reduce the installation space required by the driving circuit without affecting the operation of the driving circuit will be the main problem that needs to be solved in the design of the narrow-frame display device.

In view of the foregoing, the inventors of the present invention have considered and designed a gate driving circuit and a display panel including the same, with a view to improving the problems of the prior art, thereby enhancing the implementation and utilization in the industry.

In view of the problems mentioned in the prior art, the purpose of the present invention is to provide a gate driving circuit and a display panel including the same, change the circuit configuration to reduce the frame width, and then solve the problem of the display panel originally designed with the gate driving circuit and the gate driving circuit. Due to the difference in frame width, the display panels of the polar chip design cannot share the mechanism design.

Based on the above object, the present invention provides a gate driving circuit, wherein the gate driving circuit and the source driving circuit are arranged on the same side of the display area, and are used for driving a plurality of pixels in the display area. The gate drive circuit includes a plurality of shift registers, the plurality of shift registers receive n-phase clock signals, the latter stage a shift registers are controlled by the pull-up signal of this stage, and the first stage b is pulled down by the pull-down signal of this stage. Stage shift register, a, b, n are positive integers. A plurality of shift registers are configured as m groups of series circuits, m is a positive integer between 2 and a and m is a factor of a, and the shift registers have the same pull-up signal transmission path among the plurality of shift registers. The bit registers are adjacently arranged in the same group of series circuits.

In the embodiment of the present invention, the shift registers having the same pull-down signal transmission path among the plurality of shift registers can be adjacently arranged in the same group of series circuits.

In an embodiment of the present invention, the plurality of shift registers may include a wiring area, a first circuit area, a transfer line area, and a second circuit area, respectively.

In the embodiment of the present invention, a plurality of clock signal lines can be set in the wiring area, and the number of the plurality of clock signal lines is n/m.

In the embodiment of the present invention, the transmission line area may include signal transmission lines for transmitting the pull-up signal and the pull-down signal.

In an embodiment of the present invention, the first circuit area may include a pull-down circuit, and the second circuit area may include a pull-up circuit.

In the embodiment of the present invention, a plurality of shift registers can receive sixteen-phase clock signals, the pull-up signal of this stage controls the eight-stage shift registers, and the pull-down signal of this stage pulls down the first eight-stage shift registers. register.

In the embodiment of the present invention, the series-connected circuits can be divided into two groups, four groups or eight groups.

The present invention provides a display panel including a gate drive circuit, which includes a display area and a peripheral circuit area, the peripheral circuit area is disposed on one side of the display area, and the peripheral circuit area includes the gate drive circuit as described above, the gate electrode The driving circuits are respectively connected to the plurality of pixels in the display area, and transmit gate driving signals to drive the plurality of pixels.

In an embodiment of the present invention, the peripheral circuit area may include source driving circuits, which are respectively connected to the plurality of pixels in the display area and transmit data signals to the plurality of pixels.

Based on the above, in the gate driving circuit and the display panel including the same, the gate driving circuit can be divided into two groups by arranging the shift temporary storage circuits with the same pull-up signal transmission path or the same pull-down signal transmission path adjacent to each other. In order to connect multiple groups of circuits in series, the circuit configuration space is reduced by reducing the wiring in the wiring area and the transmission circuit area, and the goal of reducing the setting width of the peripheral circuit is achieved. The effect of reducing the perimeter width of the panel.

10, 41, 51: Gate drive circuit

20: Pixel Matrix

21: Pixels

30,30A: Shift register

31,42,52: Cable area

32: The first circuit area

32a: pull-down circuit

33, 33a: Transfer line area

34: Second circuit area

34a: pull-up circuit

40,50: Peripheral circuit area

100: Display panel

AA: display area

C: Capacitor

COF1~COF8: chip-on-film area

D: data signal

G: gate drive signal

G1~G2160: 1st stage shift register ~ 2160th stage shift register

GOA1~GOA8: 1st series circuit ~ 8th series circuit

HC1~HC16: 1st clock signal~16th clock signal

LC/VSS: Other wiring area

NA: Peripheral circuit area

Q(n): Node

ST(n-8): The first 8-level pull-up control signal

ST(n+8): The last 8 pull-down control signals

T11~T64: Transistor

W: width

In order to make the technical features, contents and advantages of the present invention and the effect it can achieve more obvious, the present invention is described with reference to the following drawings: FIG. 1 is a schematic diagram of a gate driving circuit grouping according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of a gate driving circuit according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a peripheral circuit area according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a peripheral circuit area of another grouping according to an embodiment of the present invention.

In order to facilitate the understanding of the technical features, content and advantages of the present invention and the effects that can be achieved, the present invention is hereby described in detail with the accompanying drawings, and in the form of embodiments as follows, and the drawings used therein are only for the purpose of For the purpose of illustrating and assisting the description, it is not necessarily the real proportion and precise configuration after the implementation of the present invention. Therefore, the proportion and configuration relationship of the attached drawings should not be interpreted or limited to the scope of rights of the present invention in actual implementation. Say Ming.

In the drawings, the thickness or width of substrates, panels, regions, lines, etc., are exaggerated for clarity. The same reference numerals refer to the same elements throughout the specification. It will be understood that when an element such as a substrate, panel, region or line is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements. Furthermore, it should be understood that although the terms "first," "second," and "third" may be used herein to describe various Elements, components, regions, layers and/or sections are used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Therefore, it is for descriptive purposes only and should not be construed to indicate or imply relative importance or their sequential relationship.

Unless otherwise defined, all terms used herein have the meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning unless expressly so defined herein.

Please refer to FIG. 1 , which is a schematic diagram of a grouping of gate driving circuits according to an embodiment of the present invention. As shown in the figure, the display panel 100 includes a display area AA and a peripheral circuit area NA, the peripheral circuit area NA is disposed on the sky side of the display area AA, the peripheral circuit area NA includes a gate driving circuit 10 , and the display area AA includes a plurality of pixels 21 composed of pixel matrix 20. The gate driving circuit 10 and the source driving circuit are disposed on the same side, the gate driving circuit 10 transmits the gate driving signal G to each pixel row in the pixel matrix 20 , and drives each pixel 21 in the pixel row to write to the source driving circuit The transmitted data signal D is used to present the display screen of the display area AA. The gate driving circuit 10 and the source driving circuit are arranged on the same side of the display area AA, which can reduce the width of the peripheral circuit NA on the side of the display area AA, so that the display panel 100 conforms to the design of a narrow-frame display device.

The gate driving circuit 10 includes a plurality of shift registers connected in series, and the number of the plurality of shift registers is different according to the pixel rows of the pixel matrix 20. In this embodiment, the plurality of shift registers It includes the first stage shift register G1, the second stage shift register G2... to the 2160th stage shift register G2160. The gate drive circuit 10 receives 16-phase clock signals, the plurality of shift registers are controlled by the pull-up signal of the current stage, and the shift registers of the last eight stages are controlled by the pull-up signal of the current stage, and the shift registers of the first eight stages are pulled down by the pull-down signal of the current stage. shift temporarily The register receives the clock signal, and pulls down the voltage level provided by the pull-up signal to a predetermined level through the pull-down signal, and then outputs it to the corresponding pixel row to drive each pixel 21 in the pixel row. The plurality of shift registers include a plurality of chip on film (Chip on Film) regions COF1-COF8, which are configured to provide clock signal sources to provide clock signals required by each shift register.

In the general gate driving circuit 10 , a plurality of shift registers are arranged in sequence according to the pixel rows, namely from the first stage shift register G1 , the second stage shift register G2 . . . to the first stage shift register G1 . The sequential arrangement of the 2160-level shift register G2160. However, the shift register is controlled by the pull-up signal of the current stage, and the shift register of the previous stage b is pulled down by the pull-down signal of the current stage. A and b are positive integers. The shift registers with the same pull-up signal transmission path are arranged adjacently between the shift registers, or the shift registers with the same pull-down signal transmission path between the shift registers are adjacently arranged , the routing layout of the pull-up signal or the pull-down signal can effectively reduce the line configuration space, thereby reducing the width W set by the peripheral circuit NA. In addition, the configuration of the clock signal can also be reduced accordingly, and further set the width W of the low peripheral circuit NA.

In this embodiment, the 2160 shift registers can be divided into 8 groups of series circuits, which are the order of the first series circuit GOA1, the second series circuit GOA2, ... to the eighth series circuit GOA8 configuration. The first series circuit GOA1 includes the first stage shift register G1, the ninth stage shift register G9... to the 2153rd stage shift register G2153; the second series circuit GOA2 includes the second stage The shift register G2, the 10th stage shift register G10... to the 2154th stage shift register G2154; and so on. Since the shift register is controlled by the pull-up signal of the current stage, the shift register of the next 8 stages, the shift register G9 of the ninth stage receives the control signal of the shift register G1 of the first stage, and the shift register of the 17th stage The bit register G17 receives the control signal of the ninth-stage shift register G9, and so on, that is, the transmission path of the same pull-up signal in the first series circuit GOA1, and the line does not need to cross other shift registers Scratchpad to reduce the space required for line configuration. In the pull-down signal transmission path Above, the shift register pulls down the first 8-stage shift register through the pull-down signal of this stage, the first-stage shift register G1 receives the control signal of the ninth-stage shift register G9, and the ninth-stage shift register The bit register G9 receives the control signal of the shift register G17 of the 17th stage, and so on. Each shift register in the first series circuit GOA1 has the same pull-down signal transmission path. The lines for transmitting these signals can also be adjacently arranged in the same set of series circuits without crossing other shift registers.

In the above gate driving circuit 10, the number of stages of the 8-stage shift register after the pull-up and the 8-stage shift register before the pull-down are the same (a=b), so the best line saving can be obtained in the grouping effect. In other embodiments, the number of pull-up or pull-down stages of the shift registers may be different. In terms of grouping configuration, the configuration with the same pull-up signal transmission path can be selected as the same group, or the configuration with the same pull-down signal transmission path can be selected as the same group. for the same group. As for the number of groups (m), if the same pull-up signal with the same path is divided into the same group, then m is a positive integer between 2 and a and m is a factor of a. In this embodiment, a=8 is For example, a plurality of shift registers can be divided into 2 groups, 4 groups, 8 groups and other different group numbers. The more the number of division groups, the greater the width of circuit saving. The number of groups can be based on the required width of the peripheral circuit NA or the coordination The display panel 100 is determined according to the needs of the organization.

Please refer to FIG. 2 , which is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. The gate driving circuit includes a plurality of shift registers. As shown in the figure, the circuit configuration of the shift register 30 includes a wiring area 31 , a first circuit area 32 , a transmission line area 33 and a second circuit area 34 . The cable area 31 includes various signal lines of the gate drive circuit, such as a clock signal line and a voltage signal line, these lines are coupled to the first circuit area 32, the first circuit area 32 includes a pull-down circuit, and the pull-down circuit is coupled to the first circuit area 32. The pull-up circuit of the second circuit area 34, the pull-up circuit receives the pull-up signal and the pulse signal of the previous stage a, and pulls the voltage of the voltage node to a high level, and the pull-down circuit uses the pull-down signal of the subsequent stage b to temporarily shift the shift. The node voltage of the register is pulled down to a predetermined level, and the gate drive signal is output from the output terminal. In order to pass the control between the pull-up circuit and the pull-down circuit There is a transmission line area 33 between the first circuit area 32 and the second circuit area 34 for transmitting the pull-up signal and the pull-down signal, and the signal is transmitted to the pull-up of the previous a stage or the rear b stage through the transmission line area 33 circuit or pull-down circuit.

As described in the foregoing embodiment, the pull-up circuit of the shift register 30 receives the pull-up control signals of the first eight stages, and the pull-down circuit receives the pull-down control signals of the last eight stages. Set 9 traces to transmit pull-up control signals and 9 traces to transmit pull-down control signals. In the configuration of the present embodiment, the shift registers with the same pull-up signal transmission path and the same pull-down signal transmission path are adjacently arranged in the same set of series circuits, and there is no need to set up the wiring across the stages. The traces can be reduced to one pull-up control signal trace and one transmission pull-down control signal trace, which reduces the circuit configuration space required for the transmission circuit area 33 and further reduces the configuration space required for the shift register 30 .

In addition to reducing the configuration space of the transmission line area 33, in the above-mentioned series circuit, the adjacently arranged shift registers only use part of the clock signal. For example, in the first series circuit GOA1, only the first It is driven by the clock signal and the ninth clock signal, so there is no need to draw all 16-phase clock signal lines in the wiring area 31, which can reduce the configuration space of 14 signal lines and reduce the need for the shift register 30. configuration space. By arranging the shift registers 30 with the same transmission path adjacent to the same set of series circuits, the space required for the arrangement of the wiring area 31 and the transmission circuit area 33 can be effectively reduced, thereby reducing the number of shift registers The setting width of 10000 , which reduces the space configuration required for the gate driving circuit, and meets the design requirements of the narrow frame of the display device.

Please refer to FIG. 3 , which is a schematic circuit diagram of a gate driving circuit according to an embodiment of the present invention. Please also refer to FIG. 2. As shown in the figure, the circuit configuration of the shift register 30A includes a pull-down circuit 32a and a pull-up circuit 34a. The pull-down circuit 32a and the pull-up circuit 34a are circuit configurations of 19 transistors (T11~T64) and 1 capacitor (C). The pull-up circuit 34a is coupled to the high voltage source VGHD and receives the clock signals HC1 and HC1. The first 8-stage pull-up control signal ST(n-8) pulls up the voltage of the node Q(n) to a high level. The pull-down circuit 32a is coupled to the low-voltage sources VSSQ and VSSG, and receives the eight-stage pull-down control signal ST(n+8) to pull down the voltage of the node Q(n) to a predetermined level, so that the shift register 30A can output corresponding The control signal to drive the gate of each pixel.

In this embodiment, the transmission lines of the pull-up control signal ST(n-8) and the pull-down control signal ST(n+8) are set to be coupled to the transmission line area 33a. The shift registers of the last eight stages are arranged adjacently, and there is no need to set up transmission lines across the stages, which can effectively reduce the installation space of the transmission line area 33a. The transmission line of the clock signal HC1 is arranged in the wiring area 31. Similar to the control signal, the same set of serial circuits only need to set the corresponding clock signal transmission wiring, which can reduce the setting space of the wiring area 31. When the required transmission lines are reduced, the installation space required for the gate drive circuit can be reduced accordingly, and the installation width of the peripheral circuit can be reduced.

Please refer to FIG. 4 , which is a schematic diagram of a peripheral circuit area according to an embodiment of the present invention. As shown in the figure, the peripheral circuit area 40 includes a gate driving circuit 41 and a wiring area 42, and the gate driving circuit 41 includes a first-stage shift register G1, a second-stage shift register G2... to In the 2160th stage shift register G2160, the wiring area 42 includes the first clock signal HC1, the second clock signal HC2... to the 16th clock signal HC16 and other wiring areas LC/VSS. The gate driving circuit 41 receives 16-phase clock signals, each shift register is controlled by the pull-up signal of the current stage and the shift registers of the last eight stages are controlled by the pull-up signal of the current stage, and the shift registers of the first eight stages are pulled down by the pull-down signal of the current stage.

In this embodiment, the gate driving circuit 41 arranges the shift registers in groups to form 8 groups of series circuits ( GOA1 to GOA8 ). From the bit register G1, the ninth stage shift register G9... to the 2153rd stage shift register G2153, corresponding to the cable area 42 of this series circuit area, other cable areas LC/VSS, The first clock signal HC1 and the ninth clock signal HC9. The second series circuit GOA2 includes the second-stage shift register G2 and the tenth-stage shift register G2 arranged adjacently. The registers G10... to the 2154th-level shift register G2154, and correspondingly set other wiring areas LC/VSS, the second clock signal HC2, and the tenth clock signal HC10, and so on. Similar to the foregoing embodiment, the transmission line of the gate driving circuit 41 between the pull-up circuit and the pull-down circuit can reduce the configuration space of the gate driving circuit 41 according to the grouping configuration, and the number of clock signals configured in each series circuit can be reduced. As 2, the width of the peripheral circuit region 40 can also be significantly reduced compared to the original configuration space required for 16 clock signal lines.

Please refer to FIG. 5 , which is a schematic diagram of a peripheral circuit area of another group according to an embodiment of the present invention. As shown in the figure, the peripheral circuit area 50 includes a gate driving circuit 51 and a wiring area 52, and the gate driving circuit 51 includes a first-stage shift register G1, a second-stage shift register G2... to In the 2160th-stage shift register G2160, the wiring area 52 includes the first clock signal HC1, the second clock signal HC2 . . . to the 16th clock signal HC16 and other wiring areas LC/VSS. The gate driving circuit 51 receives 16-phase clock signals, each shift register is controlled by the pull-up signal of the current stage and the shift registers of the last eight stages are controlled by the pull-up signal of the current stage, and the shift registers of the first eight stages are pulled down by the pull-down signal of the current stage.

In this embodiment, the gate driving circuit 51 arranges the shift registers in groups to form four groups of series circuits ( GOA1 - GOA4 ). The first series circuit GOA1 includes adjacently arranged first-level shift registers The bit register G1, the fifth-stage shift register G5... to the 2157th-stage shift register G2157, corresponding to the wiring area 52 of this serial circuit area, other wiring areas LC/VSS, The first clock signal HC1, the fifth clock signal HC5, the ninth clock signal HC9, and the thirteenth clock signal HC13. The second series circuit GOA2 includes the second-stage shift register G2, the sixth-stage shift register G6... to the 2158-stage shift register G2158, which are arranged adjacently, and other cables are arranged correspondingly. Zone LC/VSS, the second clock signal HC2, the sixth clock signal HC6, the tenth clock signal HC10, and the fourteenth clock signal HC14, and so on. The transmission line of the gate driving circuit 51 between the pull-up circuit and the pull-down circuit can reduce the configuration space of the gate driving circuit 51 according to the grouping configuration. Originally 16 hours The configuration space required for the pulse signal lines can also significantly reduce the width of the peripheral circuit region 50 . In another embodiment, the gate driving circuit 51 can also be further divided into two groups of series-connected circuits. The connecting circuits are respectively configured with odd-numbered clock signal lines and even-numbered clock signal lines.

For the above-mentioned grouping methods with different numbers of groups, the number of control signal transmission lines in each group of series circuits is different, and the number of clock signal lines corresponding to each group of series circuits is also different. However, different grouping methods can reduce the peripheral circuit installation space in terms of configuration space, so as to meet the requirement of reducing the width of the peripheral circuits. Therefore, the grouping method can be determined according to the requirements of the frame width required by the display device, and then conforms to the display device specifications or compatibility. Institutional specification design.

The above description is exemplary only, not limiting. Any equivalent modifications or changes that do not depart from the spirit and scope of the present invention shall be included in the appended patent application scope.

10: Gate drive circuit

20: Pixel Matrix

21: Pixels

100: Display panel

AA: display area

COF1~COF8: chip-on-film area

D: data signal

G: gate drive signal

G1~G2160: 1st stage shift register ~ 2160th stage shift register

GOA1~GOA8: 1st series circuit ~ 8th series circuit

NA: Peripheral circuit area

W: width

Claims (10)

A gate drive circuit is arranged on the same side of a display area as a source drive circuit, and is used for driving a plurality of pixels in the display area. The gate drive circuit comprises: a plurality of shift registers, the A plurality of shift registers receive n-phase clock signals, the latter stage a shift register is controlled by the pull-up signal of this stage, and the former stage b shift register is pulled down by the pull-down signal of this stage, a, b, n are A positive integer; wherein, the plurality of shift registers is configured as a series circuit of m groups, m is a positive integer between 2 and a and m is a factor of a, and the plurality of shift registers have the same The shift registers of the pull-up signal transmission path are adjacently arranged in the series circuit of the same group. The gate driving circuit of claim 1, wherein the shift registers having the same pull-down signal transmission path among the plurality of shift registers are adjacently arranged in the same group of the series-connected circuits. The gate driving circuit according to claim 1, wherein the plurality of shift registers respectively comprise a wiring area, a first circuit area, a transfer circuit area and a second circuit area. The gate driving circuit of claim 3, wherein a plurality of clock signal lines are arranged in the wiring area, and the number of the plurality of clock signal lines is n/m. The gate driving circuit of claim 3, wherein the transmission line area includes wires for transmitting the pull-up control signal and the pull-down control signal. The gate driving circuit of claim 3, wherein the first circuit region includes a pull-down circuit, and the second circuit region includes a pull-up circuit. The gate driving circuit according to claim 1, wherein the plurality of shift registers receive sixteen-phase clock signals, the pull-up signal of this stage controls the next eight-stage shift registers, and the pull-down signal of this stage Pull down the first eight shift registers. The gate driving circuit of claim 7, wherein the series connection circuit is divided into two groups, four groups or eight groups. A display panel including a gate drive circuit, which includes a display area and a peripheral circuit area, the peripheral circuit area is arranged on one side of the display area, and the peripheral circuit area includes any one of claims 1 to 8 In the gate driving circuit, the gate driving circuit is respectively connected to a plurality of pixels in the display area, and transmits a gate driving signal to drive the plurality of pixels. The display panel including a gate driver circuit as claimed in claim 9, wherein the peripheral circuit area includes a source driver circuit, and the source driver circuit is respectively connected to the plurality of pixels in the display area to transmit a data signal to the plurality of pixels.

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