TWI818667B - Display panel - Google Patents

Abstract

A display panel includes a pixel array and a gate driver. A specification of the pixel array is X*Y pixels. The pixel array includes Y gate lines and a plurality of auxiliary gate lines. A part of the auxiliary gate lines are electrically coupled to the Y gate lines, and the other part of the auxiliary gate lines and the Y gate lines are insulation. The gate driver includes (Y+Z) gate driving circuit. The (Y+Z) gate driving circuit respectively corresponding to the auxiliary gate lines, wherein the said Z included in (Y+Z) is integral.

Description

display panel

This case relates to a display panel, particularly a display panel suitable for any cutting ratio.

In some embodiments, after pixels, gate drivers and corresponding traces of the same size are fabricated on a large glass substrate, one or more panels can be obtained by cutting the large glass substrate.

In order to independently drive panels cut out from a large glass substrate, a corresponding number of gate drivers will need to be installed on the large glass substrate so that one or more panels cut out can operate independently. Moreover, the number of gate drive circuits included in each gate driver is usually determined based on the number of pixels in the vertical direction of the large glass substrate, and the number of driver chips is determined based on the number of pixels in the horizontal direction of the large glass substrate.

However, if the number of gate drivers is not proportional to the number of driver chips, it will cause problems with fan-out package docking. Furthermore, if the number of drive circuits in the gate driver is not proportional to the number of drive chips, it will also cause problems with fan-out package docking. Therefore, how to provide a display panel to solve the above problems is an important issue in this field.

This disclosure document provides a display panel. The display panel includes a pixel array and a gate driver. The pixel array includes Y gate lines and a plurality of auxiliary gate lines. The specification of the pixel array is X*Y pixels. The pixel array includes Y gate lines and a plurality of auxiliary gate lines. One part of the auxiliary gate lines is electrically coupled to the Y gate lines, and another part of the auxiliary gate lines is electrically isolated from the gate lines. The gate driver includes (Y+Z) gate drive circuits, and the (Y+Z) gate drive circuits respectively correspond to the auxiliary gate lines, where Z is a positive integer.

To sum up, the display panel provided by this disclosure document contains redundant gate driving circuits, thereby improving the problem of interconnection with the driving chip. Also, the redundant gate drive circuit will have corresponding auxiliary gate lines. Therefore, the redundant vertical auxiliary gate lines in the display panel of this disclosure are electrically insulated from the horizontal gate lines, further reducing the impact of redundant wiring on the pixel array.

The following embodiments are described in detail with the accompanying figures. However, the embodiments provided are not intended to limit the scope of the present disclosure, and the description of the structural operation is not intended to limit its execution sequence. Any recombination of components Structures and devices with equal functions are all within the scope of this disclosure. In addition, the illustrations are for illustrative purposes only and are not drawn to original size. To facilitate understanding, the same elements or similar elements will be designated with the same symbols in the following description.

Unless otherwise noted, the terms used throughout the specification and patent claims generally have their ordinary meanings as used in the field, in the disclosure and in the particular content.

In addition, the words "including", "including", "having", "containing", etc. used in this article are all open terms, which mean "including but not limited to". In addition, "and/or" used in this article includes any one or more of the relevant listed items and all combinations thereof.

In this article, when a component is called "coupling" or "coupling," it may mean "electrical coupling" or "electrical coupling." "Coupling" or "coupling" can also be used to indicate the coordinated operation or interaction between two or more components. In addition, although terms such as "first", "second", ... are used to describe different components in this document, these terms are only used to distinguish components or operations described with the same technical terms.

Please refer to FIG. 1A , which is a schematic diagram of a display panel 100 according to some embodiments of this disclosure document. As shown in FIG. 1A , the display panel 100 includes a substrate 110 , a pixel array 130 , gate drivers 112 , 114 and 116 and driving chips 122 , 124 and 126 . In some embodiments, substrate 110 may be implemented as a glass substrate. The pixel array 130 and the gate drivers 112, 114 and 116 are disposed on the substrate 110, and the pixel array 130 is disposed in the display area AA on the substrate 110.

In order to reduce the width of the left and right borders in the display panel, the auxiliary gate lines VG1 ~ VGy will extend from the driving chips 122 , 124 and 126 on one side (for example, the upper/lower side) of the display panel 100 so that they are disposed on the display panel. The gate drivers 112, 114 and 116 in 100 located on the same side as the driving chip groups 122, 124 and 126 are respectively connected to the horizontal gate lines G1~Gy via the vertical auxiliary gate lines VG1~VGy. Each of the horizontal gate lines G1 ~ Gy is electrically coupled to the pixel PIX located in the same column in the pixel array 130 , so that at least one of the gate drivers 112 , 114 and 116 passes through the auxiliary gate lines VG1 ~ VGy The corresponding one sends the corresponding gate control signal to the horizontal gate lines G1~Gy.

In the embodiment of this case, in order to complete the connection of the fan-out package, some of the driving chips COF will be divided into groups (for example, 3 gate drivers 112, 114 and 116) according to the number of gate drivers (for example, 3 gate drivers 112, 114 and 116). Three sets of driving chip sets 122, 124 and 126) are used to correspond to each gate driver respectively, and the remaining driving chip COF is implemented as a data driving chip that does not need to be connected to the gate driver.

For example, if the display panel 100 requires a total of 16 driving chips COF to drive 16*256 channels (pixel rows), the 16 driving chips COF cannot evenly correspond to the three gate drivers 112, 114 and 116. Therefore, the 15 driving chips COF are divided into three driving chip groups 122, 124, and 126, corresponding to three gate drivers 112, 114, and 116 respectively. Moreover, the remaining 16th driver chip COF is a data driver chip that does not need to be connected to a gate driver.

Please refer to FIG. 1A and FIG. 1B. FIG. 1B is a schematic diagram of the gate driver 112 according to some embodiments of this disclosure document. As shown in FIG. 1B , the gate driver 112 includes driving circuits GOA and GOAr.

The total number of gate drive circuits GOA and GOAr of the gate driver 112 will be determined based on the number of drive chips COF included in the drive chip set 122, so that the number of drive circuits GOA and GOAr in the gate driver 112 is equal to the number of drive chips COF included in the drive chip set 122. A multiple of the number of driving chips COF, so that the fan-out package between the gate driver 112 and the driving chips COF included in the corresponding driving chip group 122 can be completely connected.

Under such a structure, the total number of gate driving circuits GOA and GOAr will be greater than the number of pixel columns/gate lines included in the pixel array 130 . Therefore, the Y gate driving circuits GOA in the gate driver 112 are electrically coupled to the corresponding gate lines G1 ~ Gy via the auxiliary gate lines VG1 ~ VGy, and the Z gate driving circuits in the gate driver 112 GOAr can be understood by the residual gate drive circuit. How to configure the remaining gate drive circuit GOAr and its related layout will be described in detail in subsequent embodiments.

Specifically, it is assumed that the pixel array 130 has X pixels in the horizontal direction, Y pixels in the vertical direction, and its specification is X*Y pixels. The pixel array 130 will include Y gate lines G1 ~ Gy. The gate lines G1 ~ Gy are electrically coupled to the corresponding Y gate driving circuits GOA via the auxiliary gate lines VG1 ~ VGy respectively.

The total number of Y gate driving circuits GOA and Z gate driving circuits GOAr included in the gate driver 112 "(Y+Z)" will be determined by the number "M" of M driving chips COF in the aforementioned driving chip group 122 Implemented in multiples. In other words, the "M" is a factor of the "(Y+Z)". Moreover, the "M", "Y" and "Z" are all positive integers.

In this way, the gate drive circuits GOA and GOAr in the gate driver 112 will evenly correspond to/distribute to the drive chips COF in the drive chip set 122 , so that the gate drive circuits GOA and GOAr included in the gate driver 112 are compatible with the drive chips. The fan-out packages between the driving chips COF included in the chipset 122 can be completely connected.

The architecture of gate drivers 114 and 116 is generally similar to gate driver 112 . The gate drive circuits included in the gate drivers 114 and 116 can also be evenly corresponding/distributed to the drive chips COF in the drive chip sets 124 and 126. The respective gate drive circuits of the gate drivers 114 and 116 and the drive chip set 124 The corresponding relationship between the driving chip COF included in and 126 is similar to the corresponding relationship between the gate driving circuits GOA and GOAr included in the gate driver 112 and the driving chip COF included in the driving chip group 122, so no details are given here.

In some embodiments, the gate driving circuit GOAr is used to provide a voltage stabilizing signal. In other embodiments, the gate driving circuit GOAr is electrically isolated from the pixel array 130 . The layout and operation method of the gate driving circuit GOAr and the pixel array 130 will be described in detail in subsequent embodiments.

Please refer to Figure 2. Figure 2 illustrates the gate driving circuits GOA and GOAr, the driving chip COF, the auxiliary gate lines VG1~VGy, the gate lines G1~Gy, and the signals according to some embodiments of this disclosure document. Schematic diagram of the circuit layout of lines BUSL1, BUSL2 and data line groups D1~Dq. As shown in Figure 2, the gate driving circuit GOA is electrically coupled to the auxiliary gate lines VG1~VGy disposed in the display area AA, and the gate driving circuit GOAr is electrically coupled to the auxiliary gate lines disposed in the display area AA. Polar line VGp-1~VGp. The auxiliary gate lines VG1 ~ VGy are electrically coupled to the corresponding gate lines G1 ~ Gy respectively, and the auxiliary gate lines VG1 ~ VGy are electrically insulated from the gate lines G1 ~ Gy.

The gate driving circuit GOA is electrically coupled to the corresponding signal lines BUSL1 and BUSL2. The signal lines BUSL1 and BUSL2 are used to transmit clock signals HC1 and HC2 respectively. In some embodiments, the display panel 100 will have a larger number of signal lines to transmit a larger number of clock signals respectively, for example, 7 signal lines are used to transmit 7 clock signals respectively. Therefore, this case is not limited to this.

The driving chips COF included in the driving chip group 122 are electrically coupled to the corresponding data line groups D1 to Db and Db+1 to Dq respectively. The data line group D1 includes data lines D11, D12 and D13. Similarly, data line group D2 includes data lines D21, D22, and D23, and so on.

In this way, when the total number of gate driving circuits GOA and GOAr included in the gate driver 112 is a multiple of the number of driving chips COF included in the driving chip group 122 , the gate driving circuit GOA included in the gate driver 112 And the fan-out package between the GOAr and the driver chip COF included in the driver chipset 122 can be completely connected.

Please also refer to Figure 3. Figure 3 illustrates the gate drive circuits GOA and GOAr and the auxiliary gate lines VG1, VG2, VGp-1 and VGp, and the gate line G1 according to some embodiments of this disclosure document. Schematic diagram of the circuit layout of G2 and signal lines BUSL1 and BUSL2. As shown in Figure 3, a through hole 30 is provided at the overlap between the wiring 31 of the gate driving circuit GOA and the auxiliary gate lines VG1 and VG2, so that the gate driving circuit GOA and the auxiliary gate lines VG1 and VG2 are electrically coupled. catch. A through hole 30 is provided at the overlap between the trace 33 of the gate drive circuit GOAr and the auxiliary gate lines VGp-1 and VG-p, so that the gate drive circuit GOAr and the auxiliary gate lines VGp-1 and VG-p are electrically connected coupling.

Through holes 30 are provided at the overlapping portions of the traces 32 of the gate driving circuit GOA and the signal lines BUSL1 and BUSL2, so that the gate driving circuit GOA and the signal lines BUSL1 and BUSL2 are electrically coupled. On the other hand, no through holes are provided at the overlaps between the traces 34 of the gate driving circuit GOAr and the signal lines BUSL1 and BUSL2, so that the gate driving circuit and the signal lines BUSL1 and BUSL2 are electrically insulated.

In some embodiments, each of the data lines D21, D22, and D23 included in the data line group D2 is electrically coupled to the sub-pixels R, G, or B located in the same sub-pixel row in the pixel array 130, respectively. The connection relationship between the data line group D3, Dq-1 and Dq and the sub-pixel R, G or B is similar to the connection between the data line D21, D22 and D23 included in the data line group D2 and the corresponding sub-pixel R, G or B. relationship, so I won’t go into details here.

Please refer to Figures 3 and 4. Figure 4 is a schematic diagram of the circuit architecture of the gate driving circuit GOA(n) according to some embodiments of this disclosure document. Each of the gate driving circuits GOA shown in FIG. 3 corresponds to the gate driving circuit GOA(n) of FIG. 4 . As shown in FIG. 4 , the gate driving circuit GOA(n) includes a pull-up control circuit 410 , a pull-up circuit 420 , pull-down control circuits 450 and 460 , a first pull-down circuit 430 and a second pull-down circuit 440 .

Pull-up control circuit 410 includes transistors T12 and T11. The first terminal of the transistor T12 is used to receive the clock signal HC7, the two terminals of the transistor T12 are electrically coupled to the gate terminal of the transistor T11, and the gate terminal of the transistor T12 is used to receive the control signal Q(n-6) . The transistor T12 is used to conduct a circuit path from the clock signal HC7 to the gate terminal of the transistor T11 according to the control signal Q(n-6).

The first terminal of the transistor T11 is electrically coupled to the system high voltage terminal VDD, and the second terminal of the transistor T11 is electrically coupled to the operating node Q(n). When the transistor T11 is turned on according to the clock signal HC7, the voltage of the system high voltage terminal VDD is transmitted to the operating node Q(n) through the transistor T11.

Pull-up circuit 420 includes transistor T21. The first terminal of the transistor T21 is used to receive the clock signal HC1. The second terminal of the transistor T21 is electrically coupled to the line 31 for outputting the gate control signal G(n). The gate terminal of the transistor T21 is electrically Couple operation node Q(n). The transistor T21 is used to turn on or off the circuit path between the clock signal HC1 and the gate control signal G(n) according to the potential of the operating node Q(n).

When the transistor T21 conducts the circuit path between the clock signal HC1 and the gate control signal G(n) and the clock signal HC1 has a high logic level, the gate control signal G(n) has a high logic level, and the gate The gate control signal G(n) will be transmitted to the corresponding gate line (for example, the gate line VG1) through the wiring 31 and the corresponding auxiliary gate line (for example, the auxiliary gate line VG1), thereby conducting the conduction on the pixel array. 130 The circuit path for setting the data voltage within each pixel in the same column is shown in Figures 2 and 3.

The pull-down control circuit 450 includes transistors T51 to T56. The first terminal and the gate terminal of the transistor T51 are used to receive the low-frequency clock signal LC1. The second terminal of the transistor T51 is electrically coupled to the gate terminal of the transistor T53. The transistor T51 is used to conduct a circuit path from the low-frequency clock signal LC1 to the first terminal of the transistor T55 and the gate terminal of the transistor T53 according to the low-frequency clock signal LC1.

The first terminal of the transistor T52 is electrically coupled to the gate terminal of the transistor T53, the second terminal of the transistor T52 is electrically coupled to the system low voltage terminal VSSQ, and the gate terminal of the transistor T52 is electrically coupled to the operating node Q(n ). The transistor T52 is used to conduct a circuit path from the gate terminal of the transistor T53 to the system low voltage terminal VSSQ according to the potential of the operating node Q(n).

The first terminal of the transistor T53 is used to receive the low-frequency clock signal LC1. The gate terminal of the transistor T53 is electrically coupled to the second terminal of the transistor T51 and the first terminal of the transistor T55. The second terminal of the transistor T53 is electrically coupled to the second terminal of the transistor T53. Sexually coupled voltage stabilizing node P(n). When the potential of the operating node Q(n) has a low logic level and the transistor T51 is turned on according to the low-frequency clock signal LC1, the low-frequency clock signal LC1 is transmitted to the gate terminal of the transistor T53 through the transistor T51, causing the transistor T53 to be turned on. The circuit path of the low-frequency clock signal LC1 to the voltage stabilizing node P(n) thereby pulling up the potential of the voltage stabilizing node P(n).

The first terminal of the transistor T55 is electrically coupled to the gate terminal of the transistor T53. The gate terminal of the transistor T55 is used to receive the control signal Q(n-2). The second terminal of the transistor T55 is electrically coupled to the system low voltage. terminal VSSQ, the transistor T55 is used to conduct a circuit path from the gate terminal of the transistor T53 to the system low voltage terminal VSSQ according to the control signal Q(n-2). When the control signal Q(n-2) has a high logic level, the transistor T55 turns on the circuit path from the gate terminal of the transistor T53 to the system low voltage terminal VSSQ, so that the transistor T53 turns off the low-frequency clock signal LC1 to the voltage stabilizing node. circuit path of P(n).

Both transistors T56 and T54 are electrically coupled between the voltage stabilizing node P(n) and the system low voltage terminal VSSQ. The gate terminals of the transistors T56 and T54 are used to receive the control signals Q(n-2) and Q respectively. (n). The transistors T56 and T54 are respectively used to conduct the circuit path between the voltage stabilizing node P(n) and the system low voltage terminal VSSQ according to the control signals Q(n-2) and Q(n). When the control signal Q(n-2) or Q(n) has a high logic level, the corresponding one of the transistors T56 and T54 is turned on, thereby pulling down the potential of the voltage stabilizing node P(n).

The first pull-down circuit 430 includes transistors T32˜T35. The first pull-down circuit 430 is used to pull down the potential of the gate control signal G(n) and the potential of the gate terminal of the transistor T11 in the pull-up control circuit 410 . The second pull-down circuit 440 includes transistors T41˜T44. The second pull-down circuit 440 is used to pull down the potential of the operating node Q(n). The transistor T44 and the transistor T41 conduct the circuit path from the operating node Q(n) to the system voltage terminal VSSQ according to the control signals ST and S(n+6) respectively.

The voltage stabilizing node P(n) is electrically coupled to the gate terminals of the transistors T42, T32 and T34. When the potential of the voltage stabilizing node P(n) has a high logic level, the transistor T42 conducts the circuit path from the system low voltage terminal VSSQ to the operating node Q(n), causing the transistor T21 to turn off according to the potential of the operating node Q(n). Cut off the circuit path from the clock signal HC1 to the gate control signal G(n). At this time, the transistor T34 conducts the circuit path from the gate terminal of the transistor T11 (the potential of the gate terminal of the transistor T11 is indicated by the control signal S(n)) to the system low voltage terminal VSSQ. Furthermore, the transistor T32 conducts a circuit path from the gate control signal G(n) to the system low voltage terminal VSS, and outputs the voltage of the system low voltage terminal VSS as the gate control signal G(n).

The connection relationship between the transistors T61 - T66 in the pull-down control circuit 460 is similar to the connection relationship between the transistors T51 - T55 in the pull-down control circuit 450 . Compared with the pull-down control circuit 450, the difference of the pull-down control circuit 460 is that the clock signal LC1 is replaced by LC2, and the voltage stabilizing node P(n) is replaced by K(n). The remaining connection relationships and operating methods of the transistors T61 - T66 in the pull-down control circuit 460 are generally similar to the connection relationships and operating methods of the transistors T51 - T55 in the pull-down control circuit 450 , and therefore will not be described again here.

Similarly, the voltage stabilizing node K(n) is electrically coupled to the gate terminals of the transistors T43, T33 and T35. When the potential of the voltage stabilizing node P(n) has a high logic level, the transistor T43 conducts the circuit path from the system low voltage terminal VSSQ to the operating node Q(n), causing the transistor T21 to turn off according to the potential of the operating node Q(n). Cut off the circuit path from the clock signal HC1 to the gate control signal G(n). At this time, the transistor T35 conducts the circuit path from the gate terminal of the transistor T11 (the potential of the gate terminal of the transistor T11 is indicated by the control signal S(n)) to the system low voltage terminal VSSQ. Furthermore, the transistor T33 conducts a circuit path from the gate control signal G(n) to the system low voltage terminal VSS, and outputs the voltage of the system low voltage terminal VSS as the gate control signal G(n).

Please refer to Figures 3 and 5. Figure 5 is a schematic diagram of the circuit architecture of the gate driving circuit GOAr(n) according to some embodiments of this disclosure document. Each of the gate driving circuits GOAr shown in FIG. 3 corresponds to the gate driving circuit GOAr(n) of FIG. 5 . As shown in FIG. 5 , the gate driving circuit GOAr(n) includes a pull-up control circuit 510 , a pull-up circuit 520 , pull-down control circuits 550 and 560 , a first pull-down circuit 530 and a second pull-down circuit 540 . The pull-up control circuit 510 includes transistors T11 and T12, and the pull-up circuit 520 includes a transistor T21.

In the embodiment of FIG. 3, no through holes are provided at the overlaps between the traces 34 of the gate driving circuit GOAr(n) and the signal lines BUS1 and BUS2, so that the gate driving circuit GOAr(n) and the signal lines BUS1 and BUS2 are used for transmission. The signal line BUSL1 of the clock signal HC1 and the signal line (not shown) of HC7 are electrically insulated. Therefore, compared with the structure of the gate driving circuit GOA(n) in Figure 4, the difference in the structure of the gate driving circuit GOAr(n) is that the first end of the transistor T12 does not receive the clock signal HC7 Instead, it is a floating wire, and the first end of the transistor T21 does not receive the clock signal HC1 but is a floating wire.

In this way, the transistor T11 does not operate according to the potential Vf (for example, a low logic level) transmitted by the transistor T12. When the transistor T11 does not operate, the transistor T21 will also remain in the off state.

In this way, the pull-up control circuit 510 and the pull-up circuit 520 in the gate driving circuit GOAr(n) remain turned off and inactive, thereby not pulling up the potential of the output terminal of the gate driving circuit GOAr(n).

In some embodiments, the gate driving circuit GOAr(n) is further used to output the voltage stabilizing signal SV(n). Specifically, the pull-down control circuits 550, 560 and the pull-down circuits 530 and 540 in the gate drive circuit GOAr(n) continue to operate and provide a stable voltage stabilizing signal SV(n) at a low logic level to the corresponding auxiliary device. Gate line (for example, the auxiliary gate line VGp-1 or VGp shown in Figure 3).

In the embodiment of FIG. 5 , the connection relationship and operation mode of the pull-down control circuits 550 and 560 and the pull-down circuits 530 and 540 in the gate drive circuit GOAr(n) are generally similar to the gate drive circuit in FIG. 4 The connection relationship and operation mode of the pull-down control circuits 450 and 460 and the pull-down circuits 430 and 440 in GOA(n) will not be described again here.

Please refer to Figure 6. Figure 6 illustrates the gate driving circuits GOA and GOAr, the auxiliary gate lines VG1, VG2, VGp-1 and VGp, and the gate lines G1 and G2 according to some embodiments of this disclosure document. And the schematic diagram of the signal lines BUSL1 and BUSL2. In the embodiment of FIG. 6 , no through holes are provided at the overlaps between the traces 33 of the remaining gate driving circuit GOAr(n) and the auxiliary gate lines VGp-1 and VGp. Therefore, the gate driving circuit GOAr(n) It is electrically isolated from the auxiliary gate lines VGp-1 and VGp. In some embodiments, auxiliary gate lines VGp-1 and VGp are floating conductors.

In the embodiment of FIG. 6 , since the gate driving circuit GOAr(n) is electrically isolated from the auxiliary gate lines VGp-1 and VGp, the gate driving circuit GOAr(n) is connected to the signal lines BUSL1 and BUSL2 via the through hole 30 Electrical coupling still does not send signals to the auxiliary gate lines VGp-1 and VGp.

In other embodiments, the through hole 30 may not be provided at the overlap between the trace 34 of the gate driving circuit GOAr(n) and the signal lines BUSL1 and BUSL2. Therefore, this case does not take this as a line.

In Figure 6, the layout of the gate drive circuit GOA(n), gate lines G1 and G2, auxiliary gate lines VG1, VG2, VGp-1 and VGp is roughly similar to the gate drive circuit GOA(n) in Figure 3 ( n), the layout of gate lines G1 and G2, auxiliary gate lines VG1, VG2, VGp-1 and VGp, so they will not be described again here.

Please refer to Figure 7. Figure 7 illustrates the gate driving circuits GOA and GOAr, the auxiliary gate lines VG1, VG2, VGp-1 and VGp, and the gate lines G1 and G2 according to some embodiments of this disclosure document. As well as a schematic diagram of the circuit layout of the signal lines BUSL1, BUSL2 and the signal line DC. In the embodiment of FIG. 7, no through holes are provided at the overlaps between the traces 33 of the remaining gate driving circuit GOAr(n) and the auxiliary gate lines VGp-1 and VGp. Therefore, the gate driving circuit GOAr(n) It is electrically isolated from the auxiliary gate lines VGp-1 and VGp.

Furthermore, before entering the display area AA, through holes 30 can be provided at the overlaps between the auxiliary gate lines VGp-1 and VGp and the DC signal signal line DC, so that the auxiliary gate lines VGp-1 and VGp can connect to the DC signal signals. The lines DC are electrically coupled to transmit DC signals to the auxiliary gate lines VGp-1 and VGp, thereby stabilizing the voltages of the auxiliary gate lines VGp-1 and VGp.

In the embodiment of FIG. 7, since the gate driving circuit GOAr(n) is electrically isolated from the auxiliary gate lines VGp-1 and VGp, the gate driving circuit GOAr(n) can be electrically coupled with the signal lines BUSL1 and BUSL2. If connected, the signal will still not be output to the auxiliary gate lines VGp-1 and VGp.

In other embodiments, the through hole 30 may not be provided at the overlap between the trace 34 of the gate driving circuit GOAr(n) and the signal lines BUSL1 and BUSL2. Therefore, this case is not limited to this.

In Figure 7, the layout of the gate drive circuit GOA(n), gate lines G1 and G2, auxiliary gate lines VG1, VG2, VGp-1 and VGp is roughly similar to the gate drive circuit GOA(n) in Figure 3 ( n), the layout of gate lines G1 and G2, auxiliary gate lines VG1, VG2, VGp-1 and VGp, so they will not be described again here.

In summary, the display panel 100 provided by this disclosure document includes a redundant gate driving circuit GOAr, thereby improving the problems of fan-out packaging. Moreover, the redundant gate driving circuit GOAr will have corresponding auxiliary gate lines (for example, auxiliary gate lines VGp-1 and VGp). The redundant vertical auxiliary gate lines VGp-1 and VGp in the display panel 100 of this disclosure document VGp is electrically insulated from the horizontal gate lines G1 ~ GY, thereby reducing the impact of redundant wiring on the pixel array 130 . Furthermore, this disclosure document can provide the voltage regulation signal SV(n) or the DC signal to the redundant vertical auxiliary gate lines VGp-1 and VGp, further reducing redundant wiring (for example, the vertical auxiliary gate lines VGp-1 and VGp VGp) on the pixel array 130.

Although the disclosure has been disclosed in the above embodiments, it is not intended to limit the disclosure. Anyone with ordinary knowledge in the art can make various modifications and modifications without departing from the spirit and scope of the disclosure. Therefore, this disclosure The scope of protection disclosed shall be subject to that defined in the appended patent application scope.

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying symbols are explained as follows:

30:Through hole

31,32,33,34: Routing

100:Display panel

110:Substrate

112,114,116: Gate driver

122,124,126: Driver chipset

130:Pixel array

410,510: Pull-up control circuit

420,520: pull-up circuit

430,440,530,540: pull-down circuit

450,460,550,560: pull-down control circuit

GOA,GOAr,GOA(n),GOAr(n):gate drive circuit

COF: driver chip

G1, G2~Gy-1, Gy: gate line

VG1, VG2~VGy-1, VGy, VGp-1, VGp: auxiliary gate line

AA: display area

D1~Db,Db~Dq: data line group

D11~D13,D21~D23: data lines

BUSL1,BUSL2,DC: signal line

HC1, HC2, HC7: clock signal

T11, T12, T21, T32~T35, T41~T44, T51~T56, T61~T66: transistor

LC1, LC2: low frequency clock signal

Q(n): Operation node

P(n),K(n): voltage stabilizing node

VSS, VSSQ: system low voltage end

Q(n-6),Q(n-2),ST,S(n+6),S(n): control signal

Vf: potential

G(n):gate control signal

SV(n): Stabilized voltage signal

R,G,B: sub-pixels

PIX: pixel

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: FIG. 1A is a schematic diagram of a display panel according to some embodiments of this disclosure document. Figure 1B is a schematic diagram of a gate driver according to some embodiments of the present disclosure. Figure 2 is a schematic diagram of a gate driving circuit and a circuit layout of a driving chip and an auxiliary gate line, a gate line, a signal line and a data line group according to some embodiments of this disclosure. Figure 3 is a schematic diagram of the circuit layout of a gate drive circuit and an auxiliary gate line, a gate line and a signal line according to some embodiments of this disclosure document. FIG. 4 is a schematic diagram of the circuit architecture of a gate driving circuit according to some embodiments of this disclosure document. FIG. 5 is a schematic diagram of the circuit architecture of a gate driving circuit according to some embodiments of the present disclosure. FIG. 6 is a schematic diagram of the circuit layout of a gate drive circuit and an auxiliary gate line, a gate line, and a signal line according to some embodiments of this disclosure document. FIG. 7 is a schematic diagram of the circuit layout of a gate drive circuit and an auxiliary gate line, a gate line, and a signal line according to some embodiments of the present disclosure.

112: Gate driver

GOA, GOAr: gate drive circuit

VG1, VG2~VGy-1, VGy: auxiliary gate line

Claims (9)

A display panel includes: a pixel array, wherein the specification of the pixel array is X*Y pixels, wherein the pixel array includes: Y gate lines; and a plurality of auxiliary gate lines, wherein the A portion of the auxiliary gate lines is electrically coupled to the Y gate lines, and another portion of the auxiliary gate lines is electrically isolated from the gate lines; and a gate driver including ( Y+Z) gate drive circuits, wherein the (Y+Z) gate drive circuits respectively correspond to the auxiliary gate lines, and the Z is a positive integer, and the gate driver includes Z driving circuits among the (Y+Z) driving circuits are respectively used to provide voltage stabilizing signals to other parts of the auxiliary gate lines. The display panel as claimed in claim 1, wherein the Y drive circuits among the (Y+Z) drive circuits included in the gate driver are connected to the Y gates via a part of the auxiliary gate lines respectively. The poles are electrically coupled. The display panel of claim 2, wherein each of the Y drive circuits includes: a pull-up circuit for conducting according to the potential of an operating node to output a first clock signal as a gate control signal ; A pull-up control circuit for controlling a first control signal and a first The second clock signal pulls up the potential of the operating node so that the pull-up circuit conducts the circuit path from the first clock signal to the gate control signal; the first pull-up circuit is used to conduct the gate according to the potential of a voltage stabilizing node. A circuit path between a control signal and a low-voltage end of the system; and a pull-down control circuit for controlling the potential of the voltage stabilizing node according to a second control signal so that the pull-down circuit conducts the circuit path between the gate control signal and the low-voltage end of the system. . The display panel of claim 1, wherein a pull-up circuit and a pull-up control circuit of each of the Z drive circuits are electrically isolated from a first clock signal and a second clock signal respectively, so that the pull-up circuit The pull circuit is turned off according to a low logic level of an operating node and electrically isolates a circuit path from the first clock signal to a regulated signal. The display panel of claim 4, wherein each of the Z drive circuits includes: a pull-down circuit for conducting a circuit path between the voltage-stabilizing signal and a system low-voltage end according to the potential of a voltage-stabilizing node; and a pull-down circuit. The pull-down control circuit is used to control the potential of the voltage stabilizing node according to a second control signal so that the pull-down circuit conducts the circuit path of the voltage stabilizing signal to the low voltage end of the system. The display panel of claim 1, wherein the gate drivers respectively correspond to a driving chipset, wherein the driving chipset includes M driver wafers, and M is a factor of (Y+Z). The display panel of claim 6, wherein the driving chip set and the gate driver are disposed on the same side of a substrate. A display panel includes: a pixel array, wherein the specification of the pixel array is X*Y pixels, wherein the pixel array includes: Y gate lines; and a plurality of auxiliary gate lines, wherein the A portion of the auxiliary gate lines is electrically coupled to the Y gate lines, and another portion of the auxiliary gate lines is electrically isolated from the gate lines; and a gate driver including ( Y+Z) gate drive circuits, wherein the (Y+Z) gate drive circuits respectively correspond to the auxiliary gate lines, and the Z is a positive integer, where the (Y+Z) gate driver includes Z driving circuits among the Y+Z) driving circuits are electrically isolated from other parts of the auxiliary gate lines, and the other parts of the auxiliary gate lines are used to receive DC signals. A display panel includes: a pixel array, wherein the specification of the pixel array is X*Y pixels, wherein the pixel array includes: Y gate lines; and a plurality of auxiliary gate lines, wherein the One of the auxiliary gate lines The Y gate lines are electrically coupled separately, wherein another part of the auxiliary gate lines is electrically isolated from the gate lines; and a gate driver including (Y+Z) gates Driving circuit, wherein the (Y+Z) gate driving circuits respectively correspond to the auxiliary gate lines, and the Z is a positive integer, wherein the (Y+Z) driving circuits included in the gate driver The Z driving circuits in the circuit are electrically isolated from other parts of the auxiliary gate lines, and the other parts of the auxiliary gate lines are floating conductors.