CN108807607A - A kind of manufacturing method of specular removal high voltage LED chip - Google Patents
A kind of manufacturing method of specular removal high voltage LED chip Download PDFInfo
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- CN108807607A CN108807607A CN201710287023.9A CN201710287023A CN108807607A CN 108807607 A CN108807607 A CN 108807607A CN 201710287023 A CN201710287023 A CN 201710287023A CN 108807607 A CN108807607 A CN 108807607A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000001259 photo etching Methods 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 17
- 238000001459 lithography Methods 0.000 claims abstract description 7
- 150000002739 metals Chemical class 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052681 coesite Inorganic materials 0.000 claims description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052682 stishovite Inorganic materials 0.000 claims description 9
- 229910052905 tridymite Inorganic materials 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000005260 corrosion Methods 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000010079 rubber tapping Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000001737 promoting effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
It includes step that the present invention, which provides a kind of manufacturing method of specular removal high voltage LED chip,：S1, CBL is generated in epitaxial wafer, photoetching is carried out to the CBL according to the first assignment graph, forms substrate；S2, ITO is grown on the substrate and carries out Mesa photoetching, Mesa etchings are carried out after corroding the ITO, form the ITO that shape is the second assignment graph；S3, photoetching is carried out to the high voltage LED chip and is etching third assignment graph；S4, insulating layer is grown on the substrate, the extra insulating layer is removed by photoetching or etching；S5, it makes metal electrode figure by lithography on the substrate, PN electrode metals is deposited according to the metal electrode figure；S6, on the substrate growth of passivation layer, photoetching simultaneously remove the passivation layer on the PN electrode metals, form the high voltage LED chip.Under the premise of ensureing specular removal high voltage LED chip quality, photoetching number is greatly simplified, shortens CT Cycle Time, reduces cost, while promoting light-emitting area to a certain degree.
Description
Technical field
The present invention relates to LED chip manufacturing technology fields, more particularly to the manufacturer of a specular removal high voltage LED chip
Method.
Background technology
High pressure (HV) LED chip is to prepare section in LED chip multiple chips series connection shines, and reduces downstream encapsulation factory bonding wire
Number, improves its production efficiency and cost-effective, and the reliability of packaging body is promoted with the reduction of bonding wire number.
The technology path that mainstream LED chip manufacturer uses both at home and abroad at present is 6 photoetching (mask), respectively Mesa
Photoetching, deep etching photoetching (Isolation), CBL (Current barrier layer) photoetching, ITO photoetching, PN metal lithographics,
SiO2 photoetching uses at the bridge joint of metal spans adjacent chips CBL as the insulating layer of isolation adjacent chips, therefore CBL photoetching
Must be between Mesa photoetching and ITO photoetching, i.e. this two step photoetching must be distributed progress, so in order to which there are remainings, it is necessary to sacrificial
The certain light-emitting area of domestic animal, to loss chips brightness and increase chip use voltage and heat, reducing it to a certain degree makes
Use the service life.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of specular removal high voltage LED chips
Manufacturing method, for solving complex procedures in the prior art, problem of high cost, efficiency is low.
It includes step that the present invention, which provides a kind of manufacturing method of specular removal high voltage LED chip,：S1, CBL is generated in epitaxial wafer,
Photoetching is carried out to the CBL according to the first assignment graph, forms substrate；S2, ITO is grown on the substrate and carries out Mesa light
It carves, Mesa etchings is carried out after corroding the ITO, form the ITO that shape is the second assignment graph；S3, to the high voltage LED chip
It carries out photoetching and is etching third assignment graph；S4, insulating layer is grown on the substrate, it is more by photoetching or etching removal
The remaining insulating layer；S5, metal electrode figure is made by lithography on the substrate, according to metal electrode figure vapor deposition PN electricity
Pole metal；S6, on the substrate growth of passivation layer, photoetching simultaneously remove the passivation layer on the PN electrode metals, are formed
The high voltage LED chip.
In one embodiment of the invention, the step S1 includes step：S11, it is deposited on the surface of the epitaxial wafer
SiO2As the CBL；S12, photoetching is carried out to the CBL, forms the CBL that shape is first assignment graph；
Extra SiO outside S13, corrosion first assignment graph2；S14, removal photoresist, and clean up.
In one embodiment of the invention, the thickness of the CBL is 250nm~500nm.
In one embodiment of the invention, the step S2 includes step：S21, shape is deposited or sputtered on the substrate
At ITO；S22, the ITO is carried out to be lithographically formed the ITO that shape is second assignment graph；S23, corrosion described second refer to
Determine the extra ITO outside figure；S24, the extension that the ITO is etched using ICP；S25, removal photoresist, and clean up.
In one embodiment of the invention, the thickness of the ITO is 20nm~200nm；The depth of the ICP etchings is 1 μ
M~2 μm.
In one embodiment of the invention, the step S3 includes step：S31, the cleaning epitaxial wafer；S32, described
Isolation photoetching is carried out on epitaxial wafer, and exposed part is etched to the substrate layer of the high voltage LED chip；S33, removal light
Photoresist, and clean up.
In one embodiment of the invention, the step S4 includes step：S41, SiO is deposited on the surface of the substrate2
As the insulating layer；S42, the insulating layer is carried out to be lithographically formed the insulating layer that shape is the 4th assignment graph；
S43, the extra SiO outside the 4th assignment graph is removed using wet etching or dry etching2；S44, removal photoresist, and
It cleans up.
In one embodiment of the invention, the step S5 includes step：S51, according to the 5th assignment graph in institute
It states and the metal electrode figure is made by lithography by PN-Pad photoetching on substrate；S52, according to the metal electrode figure vapor deposition described in
PN metal electrodes；S53, stripping excess metal；S54, removal photoresist, and clean up.
In one embodiment of the invention, the step S6 includes step：S61, deposition SiO2As passivation layer；It is S62, right
The passivation layer carries out trepanning photoetching, forms the trepanning of the 6th assignment graph；S63, it is removed by wet etching or dry etching
The extra SiO of the tapping2；S64, removal photoresist, and clean up.
In one embodiment of the invention, the thickness of the insulating layer is 80nm~500nm；The PN metal electrodes thickness
It is 1 μm~3 μm；The thickness of the passivation layer is 80-240nm.
As described above, a kind of manufacturing method of specular removal high voltage LED chip of the present invention, has the advantages that：
Under the premise of ensureing specular removal high voltage LED chip quality, photoetching number is greatly simplified, shortens CT Cycle Time, drop
Low cost, while light-emitting area is promoted to a certain degree.
Description of the drawings
Fig. 1 is shown as in the present invention structural schematic diagram after the first assignment graph of photoetching in specular removal high voltage LED chip.
Fig. 2 is shown as in the present invention structural schematic diagram after the second assignment graph of photoetching in specular removal high voltage LED chip.
Fig. 3 is shown as in the present invention structural schematic diagram after photoetching third assignment graph in specular removal high voltage LED chip.
Fig. 4 is shown as in the present invention structural schematic diagram after the 4th assignment graph of photoetching in specular removal high voltage LED chip.
Fig. 5 is shown as in the present invention structural schematic diagram after the 5th assignment graph of photoetching in specular removal high voltage LED chip.
Fig. 6 is shown as in the present invention structural schematic diagram after the 6th assignment graph of photoetching in specular removal high voltage LED chip.
Fig. 7 is shown as the structural schematic diagram of specular removal high voltage LED chip product in the present invention.
Component label instructions：
The first assignment graphs of A
The second assignment graphs of B
C third assignment graphs
The 4th assignment graphs of D
The 5th assignment graphs of E
The 6th assignment graphs of F
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
It should be noted that the diagram provided in following embodiment only illustrates the basic structure of the present invention in a schematic way
Think, component count, shape and size when only display is with related component in the present invention rather than according to actual implementation in schema then
Draw, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its assembly layout kenel
It is likely more complexity.
Referring to Fig. 1 to Fig. 7, it should however be clear that structure, ratio, size etc. depicted in this specification institute accompanying drawings, only matching
The revealed content of specification is closed, so that those skilled in the art understands and reads, being not limited to the present invention can implement
Qualifications, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size,
In the case where not influencing the effect of present invention can be generated and the purpose that can reach, should all still fall in disclosed technology
In the range of Rong get Neng is covered.Meanwhile it is cited such as "upper", "lower", "left", "right", " centre " and " one " in this specification
Deng term, be merely convenient to being illustrated for narration, rather than to limit the scope of the invention, the change of relativeness
Or adjustment, in the case where changing technology contents without essence, when being also considered as the enforceable scope of the present invention.
As shown in Figures 1 to 7, Fig. 1 is shown as in the present invention in specular removal high voltage LED chip after the first assignment graph of photoetching
Structural schematic diagram.Fig. 2 is shown as in the present invention structural representation after the second assignment graph of photoetching in specular removal high voltage LED chip
Figure.Fig. 3 is shown as in the present invention structural schematic diagram after photoetching third assignment graph in specular removal high voltage LED chip.Fig. 4 is shown
For the structural schematic diagram in the present invention in specular removal high voltage LED chip after the 4th assignment graph of photoetching.Fig. 5 is shown as in the present invention
Structural schematic diagram in specular removal high voltage LED chip after the 5th assignment graph of photoetching.Fig. 6 is shown as specular removal high pressure in the present invention
Structural schematic diagram in LED chip after the 6th assignment graph of photoetching.Fig. 7 is shown as specular removal high voltage LED chip in the present invention and produces
The structural schematic diagram of product.The present invention provides a kind of manufacturing methods of specular removal high voltage LED chip, wherein specular removal high-voltage LED
Chip includes at least two concatenated specular removal high voltage LED chips, in embodiment below and Fig. 1 to Fig. 7, with three blooms
It is illustrated for effect high voltage LED chip series connection, the tandem compound of other kinds of specular removal high voltage LED chip, in this hair
Among bright protection domain.The manufacturing method of specular removal high voltage LED chip provided by the invention includes step：
S1, CBL (Current barrier layer) is generated in epitaxial wafer, CBL is carried out according to the first assignment graph A
Photoetching forms substrate；Wherein, the first assignment graph A is as shown in Figure 1.In one embodiment of this invention, step S1 includes step
Suddenly：S21, SiO is deposited on the surface of epitaxial wafer2As CBL；S22, photoetching is carried out to CBL, it is the first assignment graph to form shape
The CBL of A；Extra SiO outside S23, the first assignment graph A of corrosion2；S24, removal photoresist, and clean up.Preferably one
In embodiment, the thickness of CBL is 250nm~500nm.In the present embodiment, the SiO used by CBL2For fine and close, high transmittance
SiO2。
S2, ITO is grown on substrate and carries out Mesa photoetching, Mesa etchings are carried out after corroding ITO, it is second to form shape
The ITO of assignment graph B；Wherein, the second assignment graph B is as shown in Figure 2.In this step, Mesa photoetching and ITO photoetching are merged into
One of photoetching can simplify photoetching number, shorten the support period, reduce cost；To light-emitting area when can also reduce ITO in the past
Sacrifice, add somewhat to the light-emitting area of high voltage LED chip.Meanwhile by high pressure when Mesa photoetching and ITO photoetching
It is protected at the bridge joint of LED chip, avoids Mesa etching injuries CBL in this step.In one embodiment of this invention, step S2 packets
Include step：S21, vapor deposition or sputtering form ITO on substrate；S22, ITO is carried out being lithographically formed shape being the second assignment graph B
ITO；Extra ITO outside S23, the second assignment graph B of corrosion；S24, the extension that ITO is etched using ICP；S25, removal light
Photoresist, and clean up.Further, the thickness of ITO is 20nm~200nm；The depth of ICP etchings is 1 μm~2 μm.
S3, photoetching is carried out to high voltage LED chip and is etching third assignment graph C；Wherein, the first assignment graph C is such as
Shown in Fig. 3.In one embodiment of this invention, step S3 includes step：S31, cleaning epitaxial wafer；S32, it is carried out in extension on piece
Exposed part is etched to the substrate layer of high voltage LED chip by Isolation photoetching；S33, removal photoresist, and clean up.
S4, insulating layer is grown on substrate, extra insulating layer is removed by photoetching or etching；Wherein, the 4th specified figure
Shape D is as shown in Figure 4；In one embodiment of this invention, step S4 includes step：S41, SiO is deposited on the surface of substrate2As
Insulating layer；S42, insulating layer is carried out to be lithographically formed the insulating layer that shape is the 4th assignment graph D；S43, using wet etching or
Dry etching removes the extra SiO outside the 4th assignment graph D2；S44, removal photoresist, and clean up.It is same in Mesa photoetching
When due to remaining ITO herein, can effectively protect bottom CBL by the wet etching or dry etching damage in step S4, does not make
It obtains CBL and effectively plays insulating effect, reduction high voltage LED chip electric leakage is possible, and increases the anti-ESD abilities of high voltage LED chip.Into one
The thickness on step ground, insulating layer is 80nm~500nm；In the present embodiment, the SiO used by CBL2It is fine and close, high transmittance
SiO2。
S5, it makes metal electrode figure by lithography on substrate, PN electrode metals is deposited according to metal electrode figure；Wherein,
Five assignment graph E are as shown in Figure 5.In one embodiment of this invention, step S5 includes step：S51, according to the 5th assignment graph
E makes metal electrode figure by lithography on substrate by PN-Pad photoetching；S52, PN metal electrodes are deposited according to metal electrode figure；
S53, stripping excess metal；S54, removal photoresist, and clean up.Further, PN metal electrodes thickness is 1 μm~3 μm.
S6, on the substrate growth of passivation layer, photoetching simultaneously remove the passivation layer on the PN electrode metals, are formed
The high voltage LED chip.Wherein, the 6th assignment graph F is as shown in Figure 6；Finally formed COW products figure is as shown in Figure 7.At this
In one embodiment of invention, the step S6 includes step：S61, deposition SiO2As passivation layer；S62, to the passivation layer into
Row trepanning photoetching forms the trepanning of the 6th assignment graph (F)；S63, the tapping is removed by wet etching or dry etching
Extra SiO2；S64, removal photoresist, and clean up.After cleaning up, final COW products are formed.In the present embodiment,
SiO used by passivation layer2For fine and close, high transmittance SiO2。
In conclusion the manufacturing method of the specular removal high voltage LED chip of the present invention, is ensureing specular removal high voltage LED chip
Under the premise of quality, photoetching number is greatly simplified, shortens CT Cycle Time, reduces cost, while promoting light-emitting area to a certain degree.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of manufacturing method of specular removal high voltage LED chip, which is characterized in that including step：
S1, CBL is generated in epitaxial wafer, photoetching is carried out to the CBL according to the first assignment graph (A), forms substrate；
S2, ITO is grown on the substrate and carries out Mesa photoetching, carry out Mesa etchings after corroding the ITO, forming shape is
The ITO of second assignment graph (B)；
S3, photoetching is carried out to the high voltage LED chip and is etching third assignment graph (C)；
S4, insulating layer is grown on the substrate, the extra insulating layer is removed by photoetching or etching；
S5, it makes metal electrode figure by lithography on the substrate, PN electrode metals is deposited according to the metal electrode figure；
S6, on the substrate growth of passivation layer, photoetching simultaneously removes the passivation layer on the PN electrode metals, described in formation
High voltage LED chip.
2. the manufacturing method of specular removal high voltage LED chip according to claim 1, which is characterized in that the step S1 packets
Include step：
S11, SiO is deposited on the surface of the epitaxial wafer2As the CBL；
S12, photoetching is carried out to the CBL, forms the CBL that shape is first assignment graph (A)；
S13, the extra SiO of corrosion first assignment graph (A) outside2；
S14, removal photoresist, and clean up.
3. the manufacturing method of specular removal high voltage LED chip according to claim 2, which is characterized in that the thickness of the CBL
For 250nm~500nm.
4. the manufacturing method of specular removal high voltage LED chip according to claim 1, which is characterized in that the step S2 packets
Include step：
S21, on the substrate vapor deposition or sputtering form ITO；
S22, the ITO is carried out to be lithographically formed the ITO that shape is second assignment graph (B)；
S23, the extra ITO of corrosion second assignment graph (B) outside；
S24, the extension that the ITO is etched using ICP；
S25, removal photoresist, and clean up.
5. the manufacturing method of specular removal high voltage LED chip according to claim 4, which is characterized in that the thickness of the ITO
For 20nm~200nm；The depth of the ICP etchings is 1 μm~2 μm.
6. the manufacturing method of specular removal high voltage LED chip according to claim 1, which is characterized in that the step S3 packets
Include step：
S31, the cleaning epitaxial wafer；
S32, Isolation photoetching is carried out on the epitaxial wafer, exposed part is etched to the substrate of the high voltage LED chip
Layer；
S33, removal photoresist, and clean up.
7. the manufacturing method of specular removal high voltage LED chip according to claim 1, which is characterized in that the step S4 packets
Include step：
S41, SiO is deposited on the surface of the substrate2As the insulating layer；
S42, the insulating layer is carried out to be lithographically formed the insulating layer that shape is the 4th assignment graph (D)；
S43, the extra SiO of the 4th assignment graph (D) outside is removed using wet etching or dry etching2；
S44, removal photoresist, and clean up.
8. the manufacturing method of specular removal high voltage LED chip according to claim 7, which is characterized in that the step S5 packets
Include step：
S51, the metal electrode figure is made by lithography by PN-Pad photoetching on the substrate according to the 5th assignment graph (E)
Shape；
S52, the PN metal electrodes are deposited according to the metal electrode figure；
S53, stripping excess metal；
S54, removal photoresist, and clean up.
9. the manufacturing method of specular removal high voltage LED chip according to claim 8, which is characterized in that the step S6 packets
Include step：
S61, deposition SiO2As passivation layer；
S62, trepanning photoetching is carried out to the passivation layer, forms the trepanning of the 6th assignment graph (F)；
S63, the extra SiO of the tapping is removed by wet etching or dry etching2；
S64, removal photoresist, and clean up.
10. the manufacturing method of specular removal high voltage LED chip according to claim 9, which is characterized in that the insulating layer
Thickness is 80nm~500nm；The PN metal electrodes thickness is 1 μm~3 μm；The thickness of the passivation layer is 80-240nm.
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| CN201710287023.9A CN108807607A (en) | 2017-04-27 | 2017-04-27 | A kind of manufacturing method of specular removal high voltage LED chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116705925A (en) * | 2023-08-08 | 2023-09-05 | 江西兆驰半导体有限公司 | Forward-mounted high-voltage LED chip and preparation method thereof |
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2017
- 2017-04-27 CN CN201710287023.9A patent/CN108807607A/en active Pending
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| CN103227250A (en) * | 2013-05-07 | 2013-07-31 | 中国科学院半导体研究所 | Fabrication method of flexible transparent conducting layer interconnected arrayed LED device |
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| CN116705925A (en) * | 2023-08-08 | 2023-09-05 | 江西兆驰半导体有限公司 | Forward-mounted high-voltage LED chip and preparation method thereof |
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Application publication date: 20181113 |
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