CN108807414B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN108807414B
CN108807414B CN201710307435.4A CN201710307435A CN108807414B CN 108807414 B CN108807414 B CN 108807414B CN 201710307435 A CN201710307435 A CN 201710307435A CN 108807414 B CN108807414 B CN 108807414B
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CN108807414A (zh
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冯立伟
何建廷
邹世芳
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法包括，首先形成一第一凹槽于一基底内，然后形成一第一浅沟隔离于第一凹槽内并同时形成一第二凹槽于第一凹槽旁，其中浅沟隔离包含一上半部以及一下半部且上半部上表面切齐或高于第二凹槽下表面，之后再形成一导电层于第一凹槽及第二凹槽内以形成第一栅极结构与第二栅极结构。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种制作动态随机存取存储器(Dynamic Random Access Memory,DRAM)元件的方法。
背景技术
随着各种电子产品朝小型化发展的趋势，动态随机存取存储器(DRAM)单元的设计也必须符合高集成度及高密度的要求。对于一具备凹入式栅极结构的DRAM单元而言，由于其可以在相同的半导体基底内获得更长的载流子通道长度，以减少电容结构的漏电情形产生，因此在目前主流发展趋势下，其已逐渐取代仅具备平面栅极结构的DRAM单元。
一般来说，具备凹入式栅极结构的DRAM单元会包含一晶体管元件与一电荷贮存装置，以接收来自于位线及字符线的电压信号。然而，受限于制作工艺技术之故，现有具备凹入式栅极结构的DRAM单元仍存在有许多缺陷，还待进一步改良并有效提升相关存储器元件的效能及可靠度。
发明内容
本发明一实施例公开一种制作半导体元件的方法。首先形成一第一凹槽于一基底内，然后形成一第一浅沟隔离于第一凹槽内并同时形成一第二凹槽于第一凹槽旁，其中浅沟隔离包含一上半部以及一下半部且上半部上表面切齐或高于第二凹槽下表面，之后再形成一导电层于第一凹槽及第二凹槽内以形成第一栅极结构与第二栅极结构。
本发明另一实施例公开一种半导体元件，其主要包含一第一栅极结构设于一基底内、一第二栅极结构设于第一栅极结构旁的基底内以及一浅沟隔离设于第一栅极结构下方，其中浅沟隔离包含一上半部以及一下半部且上半部上表面切齐或高于第二栅极结构下表面。
本发明又一实施例公开一种半导体元件，其包含一浅沟隔离设于一基底内，浅沟隔离又包含一下半部以及一上半部设于下半部上方，其中上半部上表面切齐或高于基底上表面且下半部上表面低于基底上表面。
附图说明
图1至图5为本发明优选实施例制作一动态随机存取存储器元件的方法示意图。
主要元件符号说明
10 动态随机存取存储器元件 12 位线
14 字符线 16 基底
18 主动区 20 存储器区
22 栅极 24 浅沟绝缘
26 第一凹槽 28 第二凹槽
30 上半部 32 下半部
34 衬垫层 36 介电层
38 功函数金属层 40 导电层
42 第一栅极结构 44 第二栅极结构
46 硬掩模
具体实施方式
请参照图1至图5，图1至图5为本发明优选实施例制作一动态随机存取存储器元件的方法示意图，其中图1为俯视图，图2显示图1中沿着切线AA’的剖视图，图3显示图1中沿着切线BB’的剖视图，图4为接续图2的制作工艺示意图，图5为接续图3的制作工艺示意图。本实施例是提供一存储器元件，例如是具备凹入式栅极的动态随机存取存储器元件10，其包含有至少一晶体管元件(图未示)以及至少一电容结构(图未示)，以作为DRAM阵列中的最小组成单元并接收来自于位线12及字符线14的电压信号。
如图1所示，动态随机存取存储器元件10包含一基底16，例如一由硅所构成的半导体基底，然后于基底16内形成有至少一浅沟绝缘24，以于基底16上定义出多个主动区(active area,AA)18。此外，基底16上还定义有一存储器区20以及一周边区(图未示)。其中，动态随机存取存储器元件10的多个字符线(word line,WL)14与多个位线(bit line,BL)12较佳形成于存储器区20的基底16上而其他的主动元件等(未绘示)则可形成在周边区。需注意的是，为简化说明，本发明的图1仅绘示出位于存储器区20的元件上视图并省略了位于周边区的元件。
在本实施例中，各主动区18例如是相互平行地朝向一第一方向延伸，而字符线14或多条栅极22是形成在基底16内并穿越各主动区18及浅沟绝缘24。具体来说，各栅极22是沿着不同于第一方向的一第二方向，例如Y方向延伸，且第二方向与第一方向相交并小于90度。
另一方面，位线12是相互平行地形成在基底16上沿着一第三方向，例如X方向延伸，并同样横跨各主动区18及浅沟绝缘24。其中，第三方向同样是不同于第一方向，并且较佳是与第二方向垂直。也就是说，第一方向、第二方向及第三方向彼此都不同，且第一方向与第二方向及第三方向都不垂直。此外，字符线14两侧的主动区18内较佳设有接触插塞，例如包括位线接触插塞(bit line contact,BLC)(图未示)来电连接至各晶体管元件的源极/漏极区域(图未示)以及存储节点(storage node)接触插塞(图未示)来电连接一电容。
以下针对字符线14(或又称埋藏式字符线)的制作进行说明。首先如图2与图3所示，先于基底16内形成第一凹槽26，然后形成浅沟隔离24于第一凹槽26内以及一第二凹槽28于第一凹槽26旁，其中浅沟隔离24包含一上半部30以及一下半部32且上半部30上表面切齐或高于第二凹槽28下表面。
更具体而言，本发明形成浅沟隔离24的方法可先于第一凹槽26形成后依序形成一衬垫层34以及一介电层36于第一凹槽26内，然后形成一图案化掩模(图未示)于基底16上暴露第一凹槽26与第一凹槽26旁的部分基底16表面，再以图案化掩模为掩模利用蚀刻制作工艺去除第一凹槽26内的部分衬垫层34与部分介电层36，并同时去除第一凹槽26旁的部分基底16以形成第二凹槽28，其中蚀刻制作工艺后所剩余的介电层36即形成浅沟隔离24的上半部30而剩余的衬垫层34即形成浅沟隔离24的下半部32。
在本实施例中，衬垫层34与介电层36较佳包含不同材料，例如本实施例的衬垫层34较佳包含氧化硅而介电层36包含氮化硅。另外蚀刻制作工艺的蚀刻剂较佳选自由氟甲烷(CH3F)以及氧气所构成的群组，且本实施例以此配方去除部分衬垫层34与部分介电层36的时候氧化硅所构成的衬垫层34与氮化硅所构成的介电层36之间的蚀刻选择比较佳控制约20比1。换句话说，本发明较佳在进行前述蚀刻制作工艺时去除大部分的衬垫层34与小部分的介电层36，使剩余的介电层36或浅沟隔离24上半部30上表面切齐或略高于旁边的第二凹槽28底部。另外需注意的是，虽然本实施例中上半部30上表面呈现约略圆弧状，且圆弧状的上半部30上表面无论顶点或两侧的二谷点均切齐或高于旁边第二凹槽28底部，但不局限于此，依据本发明一实施例，又可于去除部分衬垫层34与部分介电层36时调整蚀刻制作工艺的参数，使剩余的介电层36或上半部30上表面呈现平坦表面，且平坦表面高于或切齐第二凹槽28底部。此实施例也属本发明所涵盖的范围。
随后如图4与图5所示，可选择性进行一现场蒸气成长(in-situ steamgeneration,ISSG)制作工艺以形成一栅极介电层(图未示)于第一凹槽26与第二凹槽28内，并再沉积一功函数金属层38以及一导电层40于栅极介电层上。接着进行一回蚀刻制作工艺去除部分导电层40与部分功函数金属层38，使剩余的导电层40与功函数金属层38略低于基底16上表面以形成第一栅极结构42于第一凹槽26内以及第二栅极结构44于第二凹槽28内。之后再形成一硬掩模46于第一栅极结构42与第二栅极结构44上方，并使硬掩模46上表面切齐基底12上表面。
在本实施例中，栅极介电层较佳包含氧化硅或可依据制作工艺需求包含高介电常数介电层，其中高介电常数介电层可包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层38可依据制作工艺或产品需求选用N型功函数金属层或P型功函数金属层，其中N型功函数金属层可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限。另外P型功函数金属层可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。导电层40可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合。
之后可依据制作工艺需求进行一离子注入制作工艺，以于第一栅极电极42与第二栅极电极44两侧的基底16内形成掺杂区(图未示)，例如轻掺杂漏极或源极/漏极区域。最后进行接触插塞制作工艺，例如可分别于第一栅极结构42与第二栅极结构44两侧形成位线接触插塞电连接源极/漏极区域与后续所制作的位线，以及形成存储节点接触插塞同时电连接源极/漏极区域与后续所制作的电容。
请再参照图4，图4另揭露本发明一实施例的动态随机存取存储器元件的结构示意图。如图4所示，动态随机存取存储器元件10主要包含第一栅极结构42设于基底16内、第二栅极结构44设于第一栅极结构42旁的基底16内、硬掩模46设于第一栅极结构42与第二栅极结构44上方以及浅沟隔离24设于第一栅极结构42下方。
其中浅沟隔离24包含一上半部30与一下半部32，上半部30上表面较佳如图中所示切齐第二栅极结构44下表面或可选择高于第二栅极结构44下表面，第一栅极结构42与第二栅极结构44分别包含功函数金属层38与导电层40，第一栅极结构42上表面切齐第二栅极结构44上表面，且硬掩模46上表面较佳切齐基底16上表面。另外如上所述，虽然本实施例中上半部30上表面呈现约略圆弧状，且圆弧状的上半部30上表面无论顶点或两侧的二谷点均可选择切齐或高于第二栅极结构44底部，但不局限于此，依据本发明一实施例，浅沟隔离24上半部30上表面又可呈现完全平坦表面，且平坦表面可选择高于或切齐第二栅极结构44下表面。在本实施例中，浅沟隔离24的上半部30与下半部32较佳包含不同材料，例如上半部30较佳包含氮化硅而下半部32包含氧化硅，但不局限于此。
请再参照图5，图5另揭露本发明一实施例的动态随机存取存储器元件的结构示意图。如图5所示，动态随机存取存储器元件10主要包含一浅沟隔离24设于基底16内，浅沟隔离24包含一上半部30以及一上半部32，其中上半部30上表面切齐或高于基底16上表面且下半部32上表面低于基底16上表面。从另一角度来看，浅沟隔离24的下半部32呈现约略U型且U型的两个垂直侧壁较佳设于上半部30与基底16之间。在本实施例中，浅沟隔离24的上半部30与下半部32较佳包含不同材料，例如上半部30较佳包含氮化硅而下半部32包含氧化硅，但不局限于此。
一般而言，动态随机存取存储器元件在制作过程中设于浅沟隔离上方的栅极(如前述实施例中第一栅极结构)底部常因低于邻近栅极结构(如前述实施例中第二栅极结构)底部而造成漏电或电子之间的干扰，进而产生所谓行列撞击效应(row hammer effect)。为了解决此问题，本发明主要在形成栅极结构之前先垫高浅沟隔离的高度，使浅沟隔离上半部的上表面切齐或略高于旁边用来形成栅极结构的凹槽，如此后续形成于浅沟隔离上方的栅极结构底部便不致低于旁边的栅极结构或字符线，进而可由此降低因电子干扰所产生行列撞击效应的问题。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (17)

1.一种制作半导体元件的方法，包括：
形成一第一凹槽于一基底内；
形成一第一浅沟隔离于该第一凹槽内以及一第二凹槽于该第一凹槽旁，其中该浅沟隔离包含一上半部以及一下半部且该上半部上表面切齐或高于该第二凹槽下表面；以及
形成一导电层于该第一凹槽及该第二凹槽内以形成第一栅极结构以及第二栅极结构；以及
于形成该导电层后形成一硬掩模于各该第一栅极结构及该第二栅极结构上，其中上半部设于第一栅极结构正下方，上半部上表面低于基底上表面，上半部的两个侧壁切齐第一栅极结构的两个侧壁，硬掩模上表面切齐基底上表面，以及导电层设于硬掩模正下方并被功函数金属层包围。
2.如权利要求1所述的方法，另包含：
形成一衬垫层于该第一凹槽内；
形成一介电层于该衬垫层上；
进行一蚀刻制作工艺去除部分该介电层及部分该衬垫层以形成该浅沟隔离。
3.如权利要求2所述的方法，其中进行该蚀刻制作工艺之后剩余的该介电层形成该浅沟隔离的该上半部而剩余的该衬垫层形成该浅沟隔离的该下半部。
4.如权利要求2所述的方法，其中该蚀刻制作工艺的蚀刻剂选自由氟甲烷(CH3F)以及氧气所构成的群组。
5.如权利要求2所述的方法，其中该衬垫层包含氧化硅且该介电层包含氮化硅。
6.如权利要求5所述的方法，其中该氧化硅对氮化硅的蚀刻选择比是20比1。
7.如权利要求1所述的方法，其中该第一栅极结构上表面切齐该第二栅极结构上表面。
8.如权利要求1所述的方法，其中该硬掩模上表面切齐该基底上表面。
9.如权利要求1所述的方法，其中该硬掩模包含氮化硅。
10.一种半导体元件，包含：
第一栅极结构，设于一基底内；
第二栅极结构，设于该第一栅极结构旁的该基底内；以及
浅沟隔离，设于该第一栅极结构下方，其中该浅沟隔离包含上半部以及下半部且该上半部上表面切齐或高于该第二栅极结构下表面；
硬掩模设于各该第一栅极结构及该第二栅极结构上，其中上半部设于第一栅极结构正下方，上半部上表面低于基底上表面，上半部的两个侧壁切齐第一栅极结构的两个侧壁，硬掩模上表面切齐基底上表面；以及
导电层设于硬掩模正下方并被功函数金属层包围。
11.如权利要求10所述的半导体元件，其中该上半部及该下半部包含不同材料。
12.如权利要求10所述的半导体元件，其中该上半部包含氮化硅且该下半部包含氧化硅。
13.如权利要求10所述的半导体元件，其中该第一栅极结构上表面切齐该第二栅极结构上表面。
14.一种半导体元件，包含：
浅沟隔离，设于一基底内，该浅沟隔离包含：
下半部；以及
上半部设于该下半部上方，其中该上半部上表面切齐或高于该基底上表面且该下半部上表面低于该基底上表面，该上半部上表面包含下凹曲面，且设于该上半部两侧的下半部上表面低于上半部高度的一半以下。
15.如权利要求14所述的半导体元件，其中该上半部及该下半部包含不同材料。
16.如权利要求14所述的半导体元件，其中该上半部包含氮化硅且该下半部包含氧化硅。
17.如权利要求14所述的半导体元件，其中该上半部下表面低于该下半部上表面。
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