CN108736897A - Parallel-to-serial converter and device applied to high-speed interface physical chip - Google Patents
Parallel-to-serial converter and device applied to high-speed interface physical chip Download PDFInfo
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- CN108736897A CN108736897A CN201810385685.4A CN201810385685A CN108736897A CN 108736897 A CN108736897 A CN 108736897A CN 201810385685 A CN201810385685 A CN 201810385685A CN 108736897 A CN108736897 A CN 108736897A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention belongs to high speed parallel-serial conversion design fields, provide a kind of parallel-to-serial converter applied to high-speed interface physical chip comprising：Phaselocked loop, parallel data sampling unit, data select and distribute control unit, the first serial register, the second serial register and differential serial data generation unit.According to the first clock and second clock, parallel data is sampled by parallel data sampling unit, generate odd number channel parallel data and even number channel parallel data, it selects by data and distributes control unit that odd number channel parallel data and even number channel parallel data are converted to odd number road serial data and even number road serial data, and it is handled by differential serial data generation unit, the differential serial data of final output.Chip interior frequency of use is reduced by the circuit structure design on odd even road using the design method of totally digital circuit, can preferably realize the IP reuse of the parallel-to-serial converter of the high-speed interface physical layer under different process.
Description
Technical field
The invention belongs to high speed parallel-serial conversion design fields, more particularly to one kind being applied to high-speed interface physical layer core
The parallel-to-serial converter and device of piece.
Background technology
Currently, the use of high-speed interface is more and more extensive, the physics of many agreements (such as PCIe, USB, SATA, SRIO)
Layer interface is realized with (Serializer-Deserializer, SerDes) technology is serially unstringed.But for high-speed interface
Physical layer realize due to need carry out hybrid digital analog circuit design, always industry design problem.And it goes here and there and turns
An important link of the circuit as SerDes circuit designs is changed, the differential data for sending serialization.Its design is good and bad
The performance of SerDes sending ports will be directly affected.Existing parallel-to-serial converter mostly use by analog circuit custom design and
At, and the design of analog circuit can not be multiplexed under manufacturing process, and many limitations are brought to the use of circuit, and circuit is multiple
Miscellaneous, the differential signal of output is susceptible to delay difference, is influenced on the normal work of entire SerDes circuits very big.
Invention content
The purpose of the present invention is to provide a kind of parallel-to-serial converter applied to high-speed interface physical chip and dresses
It sets, it is intended to solve the complexity of circuit present in traditional technical solution, easy to produce internal noise and the differential signal appearance of output
Easily there is the problem of delay difference.
A kind of parallel-to-serial converter applied to high-speed interface physical chip, including：
Phaselocked loop, for generating the first clock and second clock, first clock is identical with the second clock frequency,
Opposite in phase；
Parallel data sampling unit generates odd number channel parallel data and even number road simultaneously for being sampled to parallel data
Row data simultaneously store；
Data select and distribute control unit, connects respectively with the parallel data sampling unit, are used for according to described the
It is serial that the odd number channel parallel data and the even number channel parallel data are converted to odd number road by one clock and the second clock
Data and even number road serial data；
First serial register and the second serial register select with the data and distribute control unit and connect, distinguish
For storing odd number road serial data and even number road serial data；
Differential serial data generation unit connects with first serial register and second serial register respectively
It connects, for being handled odd number road serial data and even number road serial data according to the first clock and second clock
And generate differential serial data.
In addition, a kind of parallel-serial conversion device applied to high-speed interface physical chip is additionally provided, including：Above-mentioned answers
Parallel-to-serial converter for high-speed interface physical chip.
Above-mentioned a kind of parallel-to-serial converter applied to high-speed interface physical chip, when generating first by phaselocked loop
Clock and second clock, and according to the first clock and second clock, parallel data is sampled by parallel data sampling unit,
Odd number channel parallel data and even number channel parallel data are generated, selected by data and distributes control unit by odd number channel parallel data
Odd number road serial data and even number road serial data are converted to even number channel parallel data, finally, by differential serial data
Generation unit is handled and is generated differential serial data to odd number road serial data and even number road serial data, uses pure digi-tal
Circuit design, circuit is simple, realizes the parallel-serial conversion function of high speed, can be used for different manufacturing process and realizes, expands
The use scope of circuit, differential serial data generation unit combine phase clock and carry out selection output, effective solution difference
The problem of dividing the delay difference of serial data.
Description of the drawings
Fig. 1 is the structure for the parallel-to-serial converter applied to high-speed interface physical chip that one embodiment of the invention provides
Schematic diagram；
Fig. 2 is the knot for the parallel-to-serial converter applied to high-speed interface physical chip that another embodiment of the present invention provides
Structure schematic diagram；
Fig. 3 is that parallel data sampling is single in the parallel-to-serial converter shown in FIG. 1 applied to high-speed interface physical chip
Member and data selection and the exemplary circuit schematic diagram for distributing control unit；
Fig. 4 is the exemplary circuit shown in FIG. 1 applied to the generation circuit of selective signal in high-speed interface physical chip
Schematic diagram；
Fig. 5 is that differential serial data is given birth in the parallel-to-serial converter shown in FIG. 1 applied to high-speed interface physical chip
At the exemplary circuit schematic diagram of unit.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Please refer to Fig.1 to Fig. 5, an embodiment of the present invention provides it is a kind of applied to high-speed interface physical chip and go here and there turn
Circuit is changed, for converting parallel data into differential serial data, which includes：Phaselocked loop 10, parallel data
Sampling unit 20, data select and distribute control unit 30, the first serial register 40, the second serial register 50 and difference string
Row data generating unit 60.
It is worth noting that, as shown in Figure 1, the embodiment of the present invention is differed using the same frequency of phase-locked loop pll generation as 180 degree
The first clock CLK_0 and second clock CLK_180：It is required according to the serial baud rate of output, generates two identical frequencies, frequency
Rate is the half of serial baud rate, and the first clock CLK_0 and second clock CLK_180 of opposite in phase.Below with this two
A clock is illustrated, and can exchange CLK_0 and CLK_180 in practice.
Please refer to Fig.1,2 and 3, the parallel data of input carries out sampling processing by parallel data sampling unit 20, obtains
Odd number channel parallel data and even number channel parallel data simultaneously store, and parallel data sampling unit 20 includes the first parallel register group 21
With the second parallel register group 22, it is respectively used to storage odd number channel parallel data and even number channel parallel data.Specifically implementing
In example, the frequency of parallel data is 2CLK_0/N, and total bit wide is N, is divided for odd number road simultaneously by parallel data sampling unit 20
Row data are cached to N the first parallel register groups 21 and N the second parallel registers respectively with even number channel parallel data
In group 22, wherein the clock of odd number channel parallel data is CLK_0/N, and the clock of even number channel parallel data is~CLK_0/N.In reality
It is embodied in the circuit of border, parallel data is stored in N initial parallel register groups, and initial parallel register group is touched
The input clock of originator is 2CLK_0/N, and the input terminal of the first parallel register group 21 connects with initial parallel register group output end
It connects, and the triggering end input clock of the register in the first parallel register group 21 is CLK_0/N, in the first parallel register
The odd number channel parallel data that the clock that device group 21 obtains N is CLK_0/N, equally, the input terminal of the second parallel register group 22
It is connect with initial parallel register group output end, and the triggering end input clock of the register in the second parallel register group 22 is
~CLK_0/N, to obtain N clocks in the second parallel register group 22 as the even number channel parallel data of~CLK_0/N.
Please refer to Fig.1,2 and 3, in order to convert parallel data to serial data, the embodiment of the present invention first will be above-mentioned strange
Number channel parallel datas and even number channel parallel data are converted to odd number road serial data and even number road serial data, and data selection with
It distributes control unit 30 and exactly realizes this function.Specifically, data selection with distribute control unit 30 respectively with parallel data
Sampling unit 20 connects, and is specifically connect respectively with the first parallel register group 21 and the second parallel register group 22, and being used for will
Odd number channel parallel data and even number channel parallel data are converted to odd number road serial data and even number road serial data；Data select with
It includes generation circuit of selective signal 31, first selector MUX1 and first selector MUX2 to distribute control unit 30；First choice
The first input end of device MUX1 is connect with the first parallel register group 21, and the second input terminal of first selector MUX1 and second is simultaneously
Row register group 22 connects, and the selection signal end of first selector MUX1 is connect with generation circuit of selective signal, first selector
The output end of MUX1 is connect with the first serial register 40；The first input end of first selector MUX2 and the first parallel register
21 connection of group, the second input terminal of first selector MUX2 are connect with the second parallel register group 22, first selector MUX2's
Selection signal end is connect with generation circuit of selective signal, and the output end of first selector MUX2 and the second serial register 50 connect
It connects.
Please refer to Fig. 2 and 3, wherein generation circuit of selective signal 31 include shift register 311, it is multiple with door 312 and/or
Door 313；It is identical as the quantity of the register in shift register 311 as the quantity of door, register in shift register 311
The input terminal of input the first clock CLK_0 of triggering end, the register in shift register 311 per level-one connect one and door
312 output end, each first input end input data enable signal with door 312, each the second input terminal with door 312 connect
Connect the output end of upper level register in shift register, the last one first input end with door 312 with or door 313 output
End connection or the first input end input data enable signal of door 313 or the second input terminal of door 313, input reset signal,
The selection signal end at the selection signal end and second selector of the output end connection first selector of shift register register, it is defeated
Go out the effective selection signal SEL of cyclic shift that a cycle frequency is second clock CLK_180, then enabled by corresponding odd number road
The enabled control signal of signal and even number road is controlled, in the way of odd bits and even bit, will respectively be sent per parallel data all the way
Enter into odd number road serial register group and even number road serial register group, to which odd number channel parallel data and even number road is parallel
Data are converted to odd number road serial data and even number road serial data.
Please refer to Fig.1,2 and 3, the first serial register 40 and the second serial register 50 and data selection with distribute control
Unit 30 connects, and is respectively used to keep in an odd number road serial data and an even number road serial data；First serial register
40 input terminal is connect with the output end of first selector MUX1, keeps in an odd number road serial data, the first serial register
40 output end is connect with differential serial data generation unit 60, and on latter position odd number road, serial data enters the first serial register
When device 40, an odd number road serial data being currently stored in the first serial register 40 is exported and is given birth to differential serial data
At unit 60, equally, the input terminal of the second serial register 50 is connect with the output end of first selector MUX2, keeps in an idol
Number road serial data, the output end of the second serial register 50 are connect with differential serial data generation unit 60, in latter position idol
When number road serial datas enter the second serial register 50, an even number road will being currently stored in the second serial register 50
Serial data is exported to differential serial data generation unit 60.
Figure 4 and 5 are please referred to, differential serial data generation unit 60 is serial with the first serial register 40 and second respectively
Register 50 connects, for being handled odd number road serial data and even number road serial data and generating differential serial data.
Differential serial data generation unit 60 includes third selector MUX3, the 4th selector MUX4, the first phase inverter N1, the second reverse phase
Device N2, the first prefix register 61, the first postposition register 62, the second prefix register 63 and the second postposition register 64；The
The input terminal of one prefix register 61 is connect with the first serial register 40, after the output end and first of the first prefix register 61
The input terminal connection of register 62 is set, the input terminal of the second prefix register 63 is connect with the second serial register 50, before second
The output end for setting register 63 is connect with the input terminal of the second postposition register 64, the triggering end input of the first prefix register 61
Clock, the first postposition register 62 input the first clock CLK_0, the triggering end of the second prefix register 63 and the deposit of the second postposition
The triggering end of device 64 inputs second clock CLK_180；The first input end of third selector MUX3 and the first postposition register
62 output end connection, the second input terminal of third selector MUX3 are connect with the output end of the second postposition register 64, third
The control terminal of selector MUX3 inputs the first clock CLK_0, and the output end of third selector MUX3 exports the first serial differential number
According to, the first input end of the 4th selector MUX4 is connect by the first phase inverter N1 with the output end of the first postposition register 62,
The second input terminal of 4th selector MUX4 is connect by the second phase inverter N2 with the output end of the second postposition register 64, and the 4th
The output end that the control terminal of selector MUX4 inputs the first clock CLK_0, the 4th selector MUX4 exports the second serial differential number
According to；Wherein, the first serial differential data and the second serial differential data form serial differential data.
Processing to odd number road serial data：The input clock of the triggering end of first prefix register 61 is second clock
CLK_180, the input clock of the triggering end of the first postposition register 62 are the first clock CLK_0, the one of odd number road serial data
Group data by after this two-stage register enter third selector MUX3 first input end, another group of odd number road serial data
Data enter the first input end of the 4th selector MUX4 after the first phase inverter N1.
The processing of dual numbers road serial data：The triggering end of second prefix register 63 and the second postposition register 64 touch
The input clock of originator is second clock CLK_180, and even number circuit-switched data enters number by this two-stage register later group data
According to the second input terminal of third selector MUX3, another group of data are after the second phase inverter N2 into the 4th selector MUX4's
Second input terminal；The output end of third selector MUX3 is exported as final serial data TX, the 4th selector MUX4's
The output of output end forms serial differential data as final serial data NTX.The output of MUX0 is as final serial number
According to TX, the output of MUX1 is as final serial data NTX.The first clock CLK_0 and second clock CLK_ is cleverly used
180 phase complements characteristic carries out effectively selection to odd even road serial data and is alternately sent to realize, reaches high frequency output
Purpose.In conjunction with the first clock CLK_0 and second clock CLK_180 carry out selection output, prolonging for differential signal of effective solution
When difference problem.
As shown in figure 5, the first above-mentioned clock CLK_0 and second clock CLK_180 are generated using phaselocked loop 10, first
Clock CLK_0 identical, opposite in phase with second clock CLK_180 frequencies, and the first clock CLK_0 and second clock CLK_180
Frequency be serial differential data frequency half, specifically, phaselocked loop 10 is according to differential serial data generation unit 60
Output signal obtain the first clock CLK_0 and second clock CLK_180, using phaselocked loop 10 generate with frequency, differ as 180 degree
Two output clocks：According to the differential serial data of output, two identical frequencies are generated, frequency is the difference string line number of output
According to frequency half, and the first clock CLK_0 and second clock CLK_180 of opposite in phase, circuit structure is simple, is easy to
It realizes, used highest frequency is the half of the frequency of differential serial data, effectively reduces the frequency of its interior design,
To reduce the internal noise of entire chip.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention made by within refreshing and principle.
Claims (10)
1. a kind of parallel-to-serial converter applied to high-speed interface physical chip, which is characterized in that including：
Phaselocked loop, for generating the first clock and second clock, first clock identical, phase with the second clock frequency
On the contrary；
Parallel data sampling unit generates odd number channel parallel data and even number road and line number for being sampled to parallel data
According to；
Data select and distribute control unit, are connect respectively with the parallel data sampling unit, when for according to described first
The odd number channel parallel data and the even number channel parallel data are converted to odd number road serial data by clock and the second clock
With even number road serial data；
First serial register and the second serial register, with data selection with distribute control unit and connect, be respectively used to
Store odd number road serial data and even number road serial data；
Differential serial data generation unit is connect with first serial register and second serial register respectively, is used
Odd number road serial data and even number road serial data are handled and given birth to according to the first clock and second clock
At differential serial data.
2. as described in claim 1 be applied to high-speed interface physical chip parallel-to-serial converter, which is characterized in that it is described simultaneously
Row data sampling unit includes the first parallel register group and the second parallel register group, the first parallel register group and institute
The second parallel register group is stated to connect with the parallel data sampling unit, be respectively used to store the odd number channel parallel data and
The even number channel parallel data.
3. being applied to the parallel-to-serial converter of high-speed interface physical chip as claimed in claim 2, which is characterized in that described the
The triggering end input clock of register in one parallel register group is the half of the parallel data, second parallel register
When the triggering end input clock of register in device group is the triggering end input of the register in the first parallel register group
Clock negates.
4. being applied to the parallel-to-serial converter of high-speed interface physical chip as described in claim 1, which is characterized in that the number
According to selection with to distribute control unit include generation circuit of selective signal, first selector and second selector；
The first input end of the first selector is connect with the first parallel register group, and the second of the first selector
Input terminal is connect with the second parallel register group, and selection signal end and the selection signal of the first selector generate
Circuit connects, and the output end of the first selector is connect with first serial register；
The first input end of the second selector is connect with the first parallel register group, and the second of the second selector
Input terminal is connect with the second parallel register group, and selection signal end and the selection signal of the second selector generate
Circuit connects, and the output end of the second selector is connect with second serial register.
5. being applied to the parallel-to-serial converter of high-speed interface physical chip as claimed in claim 4, which is characterized in that described
Generation circuit of selective signal includes shift register, multiple with door and/or door；
It is described identical as the quantity of the register in the shift register as the quantity of door, the deposit in the shift register
The first clock of input of the triggering end of device, the input terminal of the register in the shift register per level-one connect one described in
The output end of door, each first input end input data enable signal with door, each second input terminal with door
Connect the output end of upper level register in the shift register, the last one described first input end with door with it is described or
The output end connection of door, described or door first input end input data enable signal, described or door the second input terminal, input
The output end of reset signal, the shift register register connects selection signal end and the second selection of the first selector
The selection signal end of device.
6. being applied to the parallel-to-serial converter of high-speed interface physical chip as described in claim 1, which is characterized in that described
Differential serial data generation unit includes third selector, the 4th selector, the first phase inverter, the second phase inverter, first preposition
Register, the first postposition register, the second prefix register and the second postposition register；
The input terminal of first prefix register is connect with first serial register, first prefix register it is defeated
Outlet is connect with the input terminal of the first postposition register, and the input terminal of second prefix register is serial with described second
Register connects, and the output end of second prefix register connect with the input terminal of the second postposition register, and described the
The triggering end input clock of one prefix register, the first postposition register input first clock, described second
The triggering end of prefix register and the triggering end of the second postposition register input the second clock；
The first input end of the third selector is connect with the output end of the first postposition register, the third selector
The second input terminal connect with the output end of the second postposition register, the control terminal of third selector input described the
The output end of one clock, the third selector exports the first serial differential data, the first input end of the 4th selector
It is connect with the output end of the first postposition register by the first phase inverter, the second input terminal of the 4th selector passes through
Second phase inverter is connect with the output end of the second postposition register, the control terminal input described first of the 4th selector
The output end of clock, the 4th selector exports the second serial differential data；
Wherein, first serial differential data and the second serial differential data form the serial differential data.
7. being applied to the parallel-to-serial converter of high-speed interface physical chip as described in claim 1, which is characterized in that first
The input terminal of serial register and the output end of first selector connect, and keep in an odd number road serial data, first serially posts
The output end of storage is connect with differential serial data generation unit, the input terminal of the second serial register and second selector it is defeated
Outlet connects, and keeps in an even number road serial data, output end and the differential serial data generation unit of the second serial register
Connection.
8. being applied to the parallel-to-serial converter of high-speed interface physical chip as described in claim 1, which is characterized in that described
The quantity of first parallel register group is identical as the quantity of the second register group.
9. being applied to the parallel-to-serial converter of high-speed interface physical chip as described in claim 1, which is characterized in that described
The frequency of first clock and the frequency of the second clock are the half of the frequency of the differential serial data.
10. a kind of parallel-serial conversion device applied to high-speed interface physical chip, which is characterized in that including：Such as claim 1
To the parallel-to-serial converter described in 9.
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| CN201810385685.4A CN108736897B (en) | 2018-04-26 | 2018-04-26 | Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110061738A (en) * | 2019-04-26 | 2019-07-26 | 海光信息技术有限公司 | A kind of all-digital phase-locked loop circuit |
| CN111157881A (en) * | 2020-01-03 | 2020-05-15 | 深圳市紫光同创电子有限公司 | Test circuit and circuit test method |
| CN111290987A (en) * | 2020-03-04 | 2020-06-16 | 武汉精立电子技术有限公司 | Device and method for realizing ultra-high-speed SPI (Serial peripheral interface) |
| CN111507054A (en) * | 2019-01-31 | 2020-08-07 | 株式会社村田制作所 | Digital output monitoring circuit and high-frequency front-end circuit |
| CN111865330A (en) * | 2020-08-05 | 2020-10-30 | 中国电子科技集团公司第二十四研究所 | High-speed parallel-serial conversion circuit suitable for JESD204B protocol standard |
| CN115982078A (en) * | 2023-01-19 | 2023-04-18 | 北京超弦存储器研究院 | CXL memory module and memory storage system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1610891A (en) * | 2001-11-21 | 2005-04-27 | 美商内数位科技公司 | Base station having a hybrid parallel/serial bus interface |
| US20070073943A1 (en) * | 2005-07-28 | 2007-03-29 | Nec Electronics Corporation | Serial-to-parallel conversion/parallel-to-serial conversion/ FIFO unified circuit |
| CN102355270A (en) * | 2005-08-03 | 2012-02-15 | 阿尔特拉公司 | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits |
| CN106464267A (en) * | 2014-05-21 | 2017-02-22 | 高通股份有限公司 | Serializer and deserializer for odd ratio parallel data bus |
-
2018
- 2018-04-26 CN CN201810385685.4A patent/CN108736897B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1610891A (en) * | 2001-11-21 | 2005-04-27 | 美商内数位科技公司 | Base station having a hybrid parallel/serial bus interface |
| US20070073943A1 (en) * | 2005-07-28 | 2007-03-29 | Nec Electronics Corporation | Serial-to-parallel conversion/parallel-to-serial conversion/ FIFO unified circuit |
| CN102355270A (en) * | 2005-08-03 | 2012-02-15 | 阿尔特拉公司 | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits |
| CN106464267A (en) * | 2014-05-21 | 2017-02-22 | 高通股份有限公司 | Serializer and deserializer for odd ratio parallel data bus |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111507054A (en) * | 2019-01-31 | 2020-08-07 | 株式会社村田制作所 | Digital output monitoring circuit and high-frequency front-end circuit |
| CN111507054B (en) * | 2019-01-31 | 2023-11-03 | 株式会社村田制作所 | Digital output monitoring circuit and high frequency front-end circuit |
| CN110061738A (en) * | 2019-04-26 | 2019-07-26 | 海光信息技术有限公司 | A kind of all-digital phase-locked loop circuit |
| CN111157881A (en) * | 2020-01-03 | 2020-05-15 | 深圳市紫光同创电子有限公司 | Test circuit and circuit test method |
| CN111157881B (en) * | 2020-01-03 | 2022-05-31 | 深圳市紫光同创电子有限公司 | Test circuit and circuit test method |
| CN111290987A (en) * | 2020-03-04 | 2020-06-16 | 武汉精立电子技术有限公司 | Device and method for realizing ultra-high-speed SPI (Serial peripheral interface) |
| CN111865330A (en) * | 2020-08-05 | 2020-10-30 | 中国电子科技集团公司第二十四研究所 | High-speed parallel-serial conversion circuit suitable for JESD204B protocol standard |
| CN111865330B (en) * | 2020-08-05 | 2023-08-08 | 中国电子科技集团公司第二十四研究所 | High-speed parallel-serial conversion circuit suitable for JESD204B protocol standard |
| CN115982078A (en) * | 2023-01-19 | 2023-04-18 | 北京超弦存储器研究院 | CXL memory module and memory storage system |
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