CN111157881B - Test circuit and circuit test method - Google Patents
Test circuit and circuit test method Download PDFInfo
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- CN111157881B CN111157881B CN202010008115.0A CN202010008115A CN111157881B CN 111157881 B CN111157881 B CN 111157881B CN 202010008115 A CN202010008115 A CN 202010008115A CN 111157881 B CN111157881 B CN 111157881B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
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Abstract
The present invention provides a test circuit, comprising: the D end of the first latch is in communication connection with a test signal source, and the D ends of the latches except the first latch are in communication connection with the Q end of the previous-stage latch; the Q end of each latch is in communication connection with a test interface of the circuit to be tested; each of the latches uses the same clock signal, clock enable signal, and reset signal. The circuit testing method is also provided, the testing circuit is adopted to control the reset signal to change from high level to low level, and each latch is reset; controlling an enabling signal source to output a high level; controlling the test signal source to output a predetermined signal; controlling an enabling signal source to output a low level and locking the Q end of each latch; and inputting the Q-locked value of each latch into a circuit to be tested for testing. The test circuit and the circuit test method of the invention avoid the process of power-on configuration and improve the test efficiency.
Description
Technical Field
The invention relates to the technical field of FPGA devices, in particular to a test circuit and a circuit test method.
Background
Testing as part of circuit design is increasingly important in modern designs where the process is more and more advanced. In digital circuit design, even additional circuit structures specially designed For testing are required For testing, which are called dft (design For test) circuits.
In FPGA design, each module can implement multiple functions, and implementing a specific function requires configuring a static configuration signal through a configurable register, i.e., CRAM, as shown in fig. 1. Each time the CRAM is reconfigured, the power-on reset is required, which brings inconvenience to the test, causes the test of the jump of the static configuration signal function to be extremely troublesome, and the change of the value of each configuration bit requires the power-on reconfiguration.
Disclosure of Invention
In view of the above problems, the test circuit and the circuit test method provided by the invention can avoid the process of power-on configuration and improve the test efficiency.
In a first aspect, the present invention provides a test circuit comprising:
the D end of the first latch is in communication connection with a test signal source, and the D ends of the latches except the first latch are in communication connection with the Q end of the previous-stage latch; the Q end of each latch is in communication connection with the test interface of the circuit to be tested;
each of the latches uses the same clock signal, clock enable signal and reset signal.
Also includes the same number of selectors as the latches;
and the Q end of the latch is in communication connection with the circuit to be tested through the selector.
Optionally, the selector is an alternative selector; one input end of the alternative selector is connected with the Q end of the latch in a communication mode, and the output end of the alternative selector is connected with the circuit to be tested in a communication mode.
Optionally, the system further comprises the same number of static registers as the latches;
the other input of the selector is communicatively coupled to the output of the static register.
Optionally, the test signal source is triggered by a rising edge of the clock signal.
The test circuit latches the test signal through the latching function of the latch, and the latched signal is used as a static configuration parameter during testing without a process of power-on configuration again, so that the test efficiency is greatly improved. Therefore, the test coverage can be greatly improved within the same test time, and a great deal of time can be saved for the same test coverage.
In a second aspect, the present invention provides a circuit testing method, using any one of the above-mentioned test circuits, wherein a reset signal is controlled to change from a high level to a low level, and each latch is reset;
controlling an enabling signal source to output a high level;
controlling the test signal source to output a predetermined signal;
controlling an enabling signal source to output a low level and locking the Q end of each latch;
and inputting the Q-locked value of each latch into a circuit to be tested for testing.
Optionally, before the reset signal is controlled to change from high level to low level and each latch is reset, the method further includes a signal selection step:
and inputting a selection signal to a selection end of each selector, wherein the selection signal controls the selector to output the signal output by the latch.
Optionally, the selector is an alternative selector.
Optionally, the method further comprises the working state: and inputting a selection signal to a selection end of each selector, wherein the selection signal controls the selector to output a signal output by the static register.
Optionally, the test signal source triggers the output of a high frequency or a low level of the test signal by a rising edge of the clock signal.
The circuit testing method latches the testing signal through the latching function of the latch, the latched signal is used as a static configuration parameter during testing, the process of power-on configuration is not needed again, and the testing efficiency is greatly improved. Therefore, the test coverage can be greatly improved within the same test time, and a great deal of time can be saved for the same test coverage.
Drawings
FIG. 1 is a prior art block diagram of a test circuit and circuit test method of the present invention;
FIG. 2 is a block diagram of a test circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of the test circuit and the circuit testing method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
As shown in fig. 2, the present embodiment provides a test circuit, including:
the D end of the first latch is in communication connection with a test signal source, and the D ends of the latches except the first latch are in communication connection with the Q end of the previous-stage latch; the Q end of each latch is in communication connection with a test interface of the circuit to be tested;
each of the latches uses the same clock signal, clock enable signal, and reset signal.
Specifically, for the circuit to be tested with four terminals as an example, the timing diagram is shown in fig. 3 when four-bit static allocation values Q3, Q2, Q1, and Q0 are 0110. TEST _ CLK is always active. TEST _ RST is first pulled high to low, resetting all latches, and bringing all outputs Q0, Q1, Q2, Q3 to 0. TEST _ SI gives the value of 0110 sequentially the first four rising edges of clk when RST is low. The TEST _ SE needs to be 1 all the time when the TEST _ SI has a valid value, and after the valid value of the TEST _ SI is given, the TEST _ SE is pulled down to 0, so that the value of the Q terminal of the latch is locked. Finally, it has stabilized that the value of Q3 comes from step 0's 0, the value of Q2 comes from step 1's 1, the value of Q1 comes from step 2's 1, and the value of Q0 comes from step 3's 0. After the desired values of the static configuration parameters are obtained, the relevant test work can be performed.
Thus, without needing to perform power-on reset of CRAM again, the jump of the change static configuration signal can be directly realized through reset of the port, TEST _ SI, the clock TEST _ CLK and the control signal TEST _ SE.
The number of the selectors is the same as that of the latches;
and the Q end of the latch is in communication connection with the circuit to be tested through the selector.
For the circuit to be tested, obviously, it is not possible to use only the test signal as the input signal, so the latch and the circuit to be tested can be connected through the selector, and the selector can select the signal, so the other input interfaces of the selector can be connected with other signal sources according to specific needs, and an appropriate signal can be selected through the selection function of the selector to be input.
Optionally, the selector is an alternative selector; one input end of the alternative selector is connected with the Q end of the latch in a communication mode, and the output end of the alternative selector is connected with the circuit to be tested in a communication mode.
Optionally, the system further comprises the same number of static registers as the latches;
the other input of the selector is communicatively coupled to the output of the static register.
The static register is used as an input in normal operation, and when the selector selects the static register as an input, the operation state of the whole circuit is the same as that in fig. 1.
Optionally, the test signal source is triggered by a rising edge of the clock signal.
The test circuit of the embodiment latches the test signal through the latching function of the latch, and the latched signal is used as a static configuration parameter during testing, so that the process of power-on configuration is not required to be carried out again, and the test efficiency is greatly improved. Therefore, the test coverage can be greatly improved within the same test time, and a great deal of time can be saved for the same test coverage.
The embodiment of the invention also provides a circuit testing method, which adopts any one of the testing circuits to control the reset signal to change from high level to low level and reset each latch;
controlling an enabling signal source to output a high level;
controlling the test signal source to output a predetermined signal;
controlling an enabling signal source to output a low level and locking the Q end of each latch;
and inputting the Q-locked value of each latch into a circuit to be tested for testing.
The specific process is as follows:
taking the example of a circuit to be tested having four terminals, a timing diagram of four static allocation values Q3, Q2, Q1, Q0 being 0110 is shown in fig. 3. TEST _ CLK is always active. TEST _ RST is first pulled high to low, resetting all latches, and bringing all outputs Q0, Q1, Q2, Q3 to 0. TEST _ SI gives the value of 0110 sequentially the first four rising edges of clk when RST is low. The TEST _ SE needs to be 1 all the time when the TEST _ SI is given a valid value, and after the valid value of the TEST _ SI is given, the TEST _ SE is pulled down to 0, so that the value of the Q end of the latch is locked. Finally, it has stabilized that the value of Q3 comes from step 0's 0, the value of Q2 comes from step 1's 1, the value of Q1 comes from step 2's 1, and the value of Q0 comes from step 3's 0. After the desired values of the static configuration parameters are obtained, the relevant test work can be performed.
Thus, without needing to perform power-on reset of CRAM again, the jump of the change static configuration signal can be directly realized through reset of the port, TEST _ SI, the clock TEST _ CLK and the control signal TEST _ SE.
Optionally, before the reset signal is controlled to change from high level to low level and each latch is reset, the method further includes a signal selection step:
and inputting a selection signal to a selection end of each selector, wherein the selection signal controls the selector to output the signal output by the latch.
For the circuit to be tested, obviously, the test signal cannot be used as the input signal, so the latch and the circuit to be tested can be connected through the selector, and the selector can select the signal, so other input interfaces of the selector can be connected with other signal sources according to specific needs, and an appropriate signal can be selected through the selection function of the selector for inputting.
Optionally, the selector is an alternative selector.
In the normal operation MODE, TEST _ MODE is 0, mux0, mux1 … … muxM-1, and mux selects the 0 terminal, and inputs SC _0, SC _1 … … SC _ M-1, SC _ M from CRAM, and the function of this time is the same as that in fig. 1.
In TEST MODE, TEST _ MODE is 1, mux1 … … muxM-1, muxM all select the 1 terminal, the input coming from the Q terminal output of each latch.
Optionally, the method further comprises the working state: and inputting a selection signal to a selection end of each selector, wherein the selection signal controls the selector to output a signal output by the static register.
The static register is used as an input in normal operation, and when the selector selects the static register as an input, the operation state of the whole circuit is the same as that in fig. 1.
Optionally, the test signal source triggers the output of a high frequency or a low level of the test signal by a rising edge of the clock signal.
According to the circuit testing method, the testing signal is latched through the latching function of the latch, the latched signal is used as a static configuration parameter during testing, the process of power-on configuration is not needed, and the testing efficiency is greatly improved. Therefore, the test coverage can be greatly improved within the same test time, and a great deal of time can be saved for the same test coverage.
Example 3
The present embodiment provides a specific TEST circuit and a specific TEST method thereof, as shown in fig. 2-3, Reg0, Reg1, … … regM-1, regM are all general latches, and the CLK ports of the latches are all connected to TEST _ CLK. The RST ends of the latches are all connected with TEST _ RST, and when the TEST _ RST is 1, Q is reset to be 0. When the clock enable signal CE end of the latch is connected with TEST _ SE, when the TEST _ SE is 1, when the TEST _ CLK is a rising edge, the output Q is equal to D, and when the TEST _ SE is 0, the value of the output Q is latched. The D end of Reg0 is connected with TEST _ SI, Reg1, Reg2 … … regM-1, and the D port of regM is connected with the Q end of the upper-level register.
Mux0, Mux1 … … muxM-1, muxM is an alternative selector, and the selection terminals are all connected with TEST _ MODE. Select input 0 is connected to the static configuration value from CRAM and select input 1 is connected to the Q output from reg0, reg1 … … regM-1, regM.
In the normal operation MODE, TEST _ MODE is 0, mux0, mux1 … … muxM-1, and mux selects the 0 terminal, and inputs SC _0, SC _1 … … SC _ M-1, SC _ M from CRAM, and the function of this time is the same as that in fig. 1.
In TEST MODE, TEST _ MODE is 1, mux1 … … muxM-1, muxM all select the 1 terminal, the input coming from the Q terminal output of each latch. When four-bit static allocation values Q3, Q2, Q1, Q0 are set to 0110, the timing diagram is shown in fig. 3. TEST _ CLK is always active. TEST _ RST is first pulled high to low, resetting all latches, and bringing all outputs Q0, Q1, Q2, Q3 to 0. TEST _ SI gives the value of 0110 sequentially the first four rising edges of clk when RST is low. The TEST _ SE needs to be 1 all the time when the TEST _ SI is given a valid value, and after the valid value of the TEST _ SI is given, the TEST _ SE is pulled down to 0, so that the value of the Q end of the latch is locked. Finally, it has stabilized that the value of Q3 comes from step 0's 0, the value of Q2 comes from step 1's 1, the value of Q1 comes from step 2's 1, and the value of Q0 comes from step 3's 0. After the desired values of the static configuration parameters are obtained, the relevant test work can be performed.
Thus, without needing to perform power-on reset of CRAM again, the jump of the change static configuration signal can be directly realized through reset of the port, TEST _ SI, the clock TEST _ CLK and the control signal TEST _ SE.
According to the circuit testing method, the testing signal is latched through the latching function of the latch, the latched signal is used as a static configuration parameter during testing, the process of power-on configuration is not needed, and the testing efficiency is greatly improved. Therefore, the test coverage can be greatly improved within the same test time, and a great deal of time can be saved for the same test coverage.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A test circuit, characterized by: the method comprises the following steps:
the D end of the first latch is in communication connection with a test signal source, and the D ends of the latches except the first latch are in communication connection with the Q end of the previous-stage latch; the Q end of each latch is in communication connection with a test interface of the circuit to be tested;
each of the latches uses the same clock signal, clock enable signal, and reset signal.
2. The test circuit of claim 1, wherein: also includes the same number of selectors as the latches;
and the Q end of the latch is in communication connection with the circuit to be tested through the selector.
3. The test circuit of claim 2, wherein: the selector is an alternative selector; one input end of the alternative selector is connected with the Q end of the latch in a communication mode, and the output end of the alternative selector is connected with the circuit to be tested in a communication mode.
4. The test circuit of claim 3, wherein: the static registers with the same number as the latches are also included;
the other input of the selector is communicatively coupled to the output of the static register.
5. The test circuit of claim 1, wherein: the test signal source is triggered by a rising edge of the clock signal.
6. A circuit testing method using the test circuit according to any one of claims 1 to 5, characterized in that: the reset signal is controlled to be changed from high level to low level, and each latch is reset;
controlling an enabling signal source to output a high level;
controlling the test signal source to output a predetermined signal;
controlling an enabling signal source to output a low level and locking the Q end of each latch;
and inputting the Q-locked value of each latch into a circuit to be tested for testing.
7. The circuit testing method of claim 6, wherein: before the reset signal is controlled to be changed from high level to low level and each latch is reset, the method also comprises a signal selection step:
and inputting a selection signal to a selection end of each selector, wherein the selection signal controls the selector to output the signal output by the latch.
8. The circuit testing method of claim 7, wherein: the selector is an alternative selector.
9. The circuit testing method of claim 8, wherein: the method also comprises the following working states: and inputting a selection signal to a selection end of each selector, wherein the selection signal controls the selector to output a signal output by the static register.
10. The circuit testing method of claim 6, wherein: and the test signal source triggers and outputs the high level or the low level of the test signal by the rising edge of the clock signal.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766721A (en) * | 1993-08-30 | 1995-03-10 | Hitachi Ltd | Frequency divider and digital signal processor |
| US6591371B1 (en) * | 2000-01-18 | 2003-07-08 | Hewlett Packard Development Company, L.P. | System for counting a number of clock cycles such that a count signal is diverted from a cascaded series of write latches to a cascaded series of erase latches |
| CN102970013A (en) * | 2012-11-28 | 2013-03-13 | 中国人民解放军国防科学技术大学 | Resetting method and resetting control device of register inside chip based on scanning chain |
| CN105185339A (en) * | 2015-10-08 | 2015-12-23 | 京东方科技集团股份有限公司 | Shift register unit, grid line drive unit and drive method |
| CN105335105A (en) * | 2015-12-22 | 2016-02-17 | 信阳师范学院 | QDR IV ultrahigh-speed storage controller suitable for FPGA |
| CN106486047A (en) * | 2017-01-03 | 2017-03-08 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driver circuit and display device |
| CN107871468A (en) * | 2016-09-28 | 2018-04-03 | 合肥鑫晟光电科技有限公司 | Export reset circuit, grid integrated drive electronics, driving method and display device |
| CN108736897A (en) * | 2018-04-26 | 2018-11-02 | 深圳市国微电子有限公司 | Parallel-to-serial converter and device applied to high-speed interface physical chip |
| CN108877721A (en) * | 2018-07-26 | 2018-11-23 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit, display device and driving method |
-
2020
- 2020-01-03 CN CN202010008115.0A patent/CN111157881B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766721A (en) * | 1993-08-30 | 1995-03-10 | Hitachi Ltd | Frequency divider and digital signal processor |
| US6591371B1 (en) * | 2000-01-18 | 2003-07-08 | Hewlett Packard Development Company, L.P. | System for counting a number of clock cycles such that a count signal is diverted from a cascaded series of write latches to a cascaded series of erase latches |
| CN102970013A (en) * | 2012-11-28 | 2013-03-13 | 中国人民解放军国防科学技术大学 | Resetting method and resetting control device of register inside chip based on scanning chain |
| CN105185339A (en) * | 2015-10-08 | 2015-12-23 | 京东方科技集团股份有限公司 | Shift register unit, grid line drive unit and drive method |
| CN105335105A (en) * | 2015-12-22 | 2016-02-17 | 信阳师范学院 | QDR IV ultrahigh-speed storage controller suitable for FPGA |
| CN107871468A (en) * | 2016-09-28 | 2018-04-03 | 合肥鑫晟光电科技有限公司 | Export reset circuit, grid integrated drive electronics, driving method and display device |
| CN106486047A (en) * | 2017-01-03 | 2017-03-08 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driver circuit and display device |
| CN108736897A (en) * | 2018-04-26 | 2018-11-02 | 深圳市国微电子有限公司 | Parallel-to-serial converter and device applied to high-speed interface physical chip |
| CN108877721A (en) * | 2018-07-26 | 2018-11-23 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit, display device and driving method |
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