CN102055465A - Frequency divider capable of configuring any integer and half-integer and method using same - Google Patents
Frequency divider capable of configuring any integer and half-integer and method using same Download PDFInfo
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Abstract
The invention provides a frequency divider capable of configuring any integer and half-integer and a method using the same, belonging to the technical field of digital frequency division. The frequency divider comprises a mode selection and output part, a configuration data latching part and a frequency division counter part, and is characterized in that the mode selection and output part is connected with the configuration data latching part and the frequency division counter part respectively. The method by using the frequency divider comprises the following steps: 1, starting; 2, inputting frequency division coefficients and mode selection signals; 3, applying effective reset signals, and latching the frequency division coefficients and the mode selection signals; 4, inputting signals to be subjected to frequency division, running the frequency divider, and outputting the frequency division signals; and 5, judging whether the frequency division coefficients or the frequency division modes need to be changed. According to the invention, a frequency division function of any integer or half-integer can be realized; when the integer is subjected to frequency division, equal duty ratio frequency division signals and unequal duty ratio frequency division signals can be output in accordance with requirements; and the frequency division coefficients of the frequency divider and the duty ratio of the output signals can be adjusted based on conditions, thus improving the flexibility of the frequency divider and expanding applicable range of the frequency divider.
Description
Technical field
The present invention relates to microelectronics digital frequency division technical field, be meant a kind of configurable arbitrary integer half integer frequency divider device and method especially.
Background technology
Microelectric technique is one of key technology of information age 21 century, is the basis of computer technology, automatic control, the communication technology.The application of integrated circuit now has been penetrated into each field of engineering technology, and frequency divider is the basis of integrated circuit and FPGA design, is widely used in the design of various digital systems and integrated circuit.Thereby frequency divider is a kind of high-frequency signal with input handles the device of exporting required low frequency signal, in different designs, the designer can run into various frequency division requirement, as even frequency division, frequency division by odd integers, half-integer frequency division etc., duty ratio such as requirement requires duty ratios such as non-sometimes sometimes.
Even frequency division and odd number do not wait the realization of duty ratio frequency division more or less freely, can utilize the cascade of counter or counter to realize, duties such as odd number when the half-integer frequency division realization then comparatively the difficulty.In addition, the divide ratio of general frequency divider and duty ratio major part all can not be regulated, and inconvenience is arranged in actual applications more.As the patent No. is that CN200580007593.3, denomination of invention promptly belong to these row for the patent of " frequency divider ".
Summary of the invention
For overcoming the defective of prior art, the invention provides a kind of configurable arbitrary integer half integer frequency divider device and method, to realize arbitrary integer or half integral division function, duty ratio such as when integral frequency divisioil, can export according to demand and not wait two kinds of fractional frequency signals of duty ratio, the divide ratio of frequency divider and the duty ratio of output signal can according to circumstances be regulated, thereby improve the flexibility of frequency divider, enlarge its scope of application.
Technical scheme of the present invention is as follows:
A kind of configurable arbitrary integer half integer frequency divider device, comprise that model selection and output, configuration data latch part and frequency division counter part, it is characterized in that model selection and output latch part with configuration data respectively and partly be connected with frequency division counter; Wherein external reset signal (rst_n) is input to configuration data and latchs part and frequency division counter part, divide ratio input signal (n_in) and frequency division mode input signal (mod_in) are input to configuration data and latch part, treat that sub-frequency clock signal (clk_in) is input to model selection and output, model selection and output output frequency division output signal (clk_out); Configuration data latchs part and is connected to model selection and output by signal n and mod, and model selection and output are connected to the frequency division counter part by signal N, x, y, z;
Frequency division counter partly comprises 8 up counters, 8 bit comparators, 1 d type flip flop, 1 T trigger, its inner annexation is: signal x receives the input end of clock of 8 up counters and 1 d type flip flop, the numerical value output and the signal N of 8 up counters connect 8 bit comparators, the input of 1 d type flip flop of output termination of 8 bit comparators, the input end of clock of 1 T trigger of output termination of 1 d type flip flop, reset signal (rst_n) connects the reset terminal of 8 up counters, 1 d type flip flop, 1 T trigger, 1 T trigger output signal z.8 up counters carry out plus coujnt to counting clock signal x, 8 bit comparators are judged its count value, output useful signal to 1 d type flip flop when numerical value equals N, thereby counting clock x is realized the function of Fractional-N frequency, 1 T trigger carries out 2 frequency divisions to input signal y, thereby obtains the signal z of duty ratio 50%.When reset signal rst_n is effective, 8 up counters, 1 d type flip flop and 1 T trigger all will reset.
Configuration data latchs part and mainly comprises one 8 latchs (latch1) and one 3 latchs (latch2), its inner annexation is: divide ratio input signal (n_in) is input to the value input of 8 latchs (latch1), frequency division mode input signal (mod_in) is input to the value input of 3 latchs (latch2), 8 latchs (latch1) output signal n, 3 latchs (latch2) output signal mod, reset signal (rst_n) also connects 8 latchs (latch1) and the Enable Pin of 3 latchs (latch2).When reset signal (rst_n) is effective, 8 latchs (latch1) latch the divide ratio (n_in) of input, 3 latchs (latch2) latch frequency division mode signal (mod_in), keep the value of divide ratio and frequency division mode signal constant when the rst_n invalidating signal.
Model selection and output comprise that mainly 2 select 1 data selector MUX1, MUX2,3 select 1 data selector MUX3, XOR gate, logic with shift moves to right, from one adder, its inner annexation is: clk_in and z signal connect the input of XOR gate, the output of XOR gate, clk_in connects 2 value inputs that select 1 data selector MUX1, y, z connects 2 value inputs that select 1 data selector MUX2, the n signal connects the input from the one adder and the logic with shift that moves to right, n, n1, n2 connects 3 value inputs that select 1 data selector MUX3, the mod signal also is connected to 2 and selects 1 data selector MUX1, MUX2,3 select the address input end of 1 data selector MUX3,2 select 1 data selector MUX1 output x signal, 2 select 1 data selector MUX2 output clk_out signal, and 3 select 1 data selector MUX3 output n-signal.MUX1, MUX2, MUX3 select different signals to separately output according to the value of mod signal.Wherein the system of selection of x signal is: when the value of mod signal was 000,010,100, the value of x was a, otherwise the value of x is clk_in; Wherein a is clk_in and z XOR gained signal mutually.Wherein the system of selection of clk_out signal is: when the value of mod signal was 000,010, the value of clk_out was z, otherwise the value of clk_out signal is y.Wherein the system of selection of n-signal is: when the value of mod signal is 000, the value of N is n1, when the value of mod signal is 010, the value of N is n2, otherwise the value of N is n, wherein n1 be by the n signal through the move to right signal of 1 gained of the logic with shift that moves to right, n2 be by the n signal through moving to right logic with shift and after one adder the signal of gained.
Reset signal described in the present invention (rst_n), treat that frequency-dividing clock input signal (clk_in), frequency division output signal (clk_out), x, y, z signal are 1 signal, frequency division mode input signal (mod_in), mod signal are tribute signal; It is 8 signals that the signal figure place of divide ratio input signal (n_in), n, N and configuration data latch in the part.
A kind of method of using said apparatus to carry out configurable arbitrary integer half-integer frequency division, step is as follows:
1): beginning;
2): input divide ratio (n_in) and mode select signal (mod_in), select signal promptly according to frequency division demand input divide ratio, and according to frequency division demand preference pattern, the frequency division pattern has 5 kinds, when n was the fractional frequency signal of duty ratios such as odd number and needs output, the mod value should be 000; When n is an odd number and when needing output not wait the fractional frequency signal of duty ratio, the mod value should be 001; When n was the fractional frequency signal of duty ratios such as even number and needs output, the mod value should be 010; When n is an even number and when needing output not wait the fractional frequency signal of duty ratio, the mod value should be 011; When needs output n-0.5 fractional frequency signal, promptly during the half-integer fractional frequency signal, the mod value should be 100;
3): apply effective reset signal (rst_n), low level is effective, the part that latchs configuration data will latch the divide ratio (n_in) and the mode signal (mod_in) of input in the step 2, according to mode select signal mod, data selector MUX1 in model selection and the output, MUX2, MUX3 will select the input signal N of corresponding signal as the frequency division counter part, x, thereby produce corresponding frequency-dividing clock x, y feeds back to model selection and output, and by model selection and output according to mod signal output frequency division clock clk_out, whole model selection and output are pure combinational logic; After resetting, reset signal (rst_n) becomes disarmed state, is reduced to high level;
4): sub-frequency clock signal (clk_in) is treated in input, frequency divider begins operate as normal, according to step 2) middle divide ratio (n_in) and the mode select signal of importing (mod_in), model selection and output will be exported corresponding signal N and x to the frequency division counter part, simultaneously output frequency division output signal (clk_out);
5): judge whether to need to change divide ratio or frequency division pattern, if then return step 2) re-enter divide ratio (n_in) and mode select signal (mod_in), otherwise change step 4) over to, frequency divider continues output frequency division output signal (clk_out) according to last time setting.
The present invention adopts easy circuit to realize duty ratio division function such as arbitrary integer, duty ratio such as half integral be non-, and can adjust divide ratio and duty ratio situation according to demand at any time.Circuit of the present invention can be configured in the effect that realizes frequency division in the FPGA/CPLD chip, can realize on the cheap FPGA/CPLD of the overwhelming majority, also can be used as a kind of IP kernel and is widely used among the integrated circuit (IC) design of various scales.
Description of drawings
Fig. 1 is a configurable arbitrary integer half integer frequency divider apparatus structure block diagram of the present invention;
Wherein: 1, configuration data latchs part, and 2, the frequency division counter part, 3, model selection and output.
Fig. 2 latchs the structural representation of part for configuration data of the present invention;
Wherein: 4,8 bit data latchs (latch1), 5,3 bit data latchs (latch2).
Fig. 3 is the structural representation of frequency division counter part of the present invention;
Wherein: 6,8 up counters, 7,8 bit comparators, 8,1 d type flip flops, 9,1 T triggers.
Fig. 4 is the structural representation of model selection of the present invention and output;
Wherein: 10, XOR gate, 11,2 select 1 data selector (MUX1), and 12,2 select 1 data selector (MUX2), and 13, the logic with shift that moves to right, 14, from one adder, 15, the logic with shift that moves to right, 16,3 select 1 data selector (MUX3).
Fig. 5 is the flow chart of the inventive method; Wherein 1) be its each step-5).
Embodiment
The present invention will be further described below in conjunction with drawings and Examples, but be not limited thereto.
Embodiment 1:
The embodiment of the invention 1 comprises that model selection and output 3, configuration data latch part 1 and frequency division counter part 2 shown in Fig. 1-4, it is characterized in that model selection and output 3 latch part 1 with configuration data respectively and be connected with frequency division counter part 2; Wherein external reset signal (rst_n) is input to configuration data and latchs part 1 and frequency division counter part 2, divide ratio input signal (n_in) and frequency division mode input signal (mod_in) are input to configuration data and latch part 1, treat that sub-frequency clock signal (clk_in) is input to model selection and output 3, model selection and output 3 output frequency division output signals (clk_out); Configuration data latchs part 1 and is connected to model selection and output by signal n and mod, and model selection and output 3 are connected to frequency division counter part 2 by signal N, x, y, z;
Frequency division counter part 2 comprises 8 up counters 6,8 bit comparators 7,1 d type flip flop 8,1 T trigger 9, its inner annexation is: signal x receives the input end of clock of 8 up counters 6 and 1 d type flip flop 8, the numerical value output of 8 up counters 6 and signal N connect 8 bit comparators 7, the input of 1 d type flip flop 8 of output termination of 8 bit comparators 7, the input end of clock of 1 T trigger 9 of numerical value output termination of 1 d type flip flop 8, reset signal (rst_n) connects 8 up counters 6,1 d type flip flop 8, the reset terminal of 1 T trigger 9,1 T trigger 9 output signal z.6 couples of counting clock signal x of 8 up counters carry out plus coujnt, 8 bit comparators 7 are judged its count value, output useful signal to 1 d type flip flop 8 when numerical value equals N, thereby counting clock x is realized the function of Fractional-N frequency, 9 couples of input signal y of 1 T trigger carry out 2 frequency divisions, thereby obtain the signal z of duty ratio 50%.When reset signal rst_n is effective, 6,1 d type flip flop 8 of 8 up counters and 1 T trigger 9 all will reset.
Configuration data latchs part 1 and mainly comprises 4 and one 3 latchs of one 8 latchs (latch1) (latch2) 5, its inner annexation is: divide ratio input signal (n_in) is input to the value input of 8 latchs (latch1) 4, frequency division mode input signal (mod_in) is input to the value input of 3 latchs (latch2) 5,8 latchs (latch1), 4 output signal n, 3 latchs (latch2), 5 output signal mod, reset signal (rst_n) also connects the Enable Pin of 4 and 3 latchs of 8 latchs (latch1) (latch2) 5.When reset signal (rst_n) is effective, 8 latchs (latch1) 4 latch the divide ratio (n_in) of input, 3 latchs (latch2) 5 latch frequency division mode signal (mod_in), keep the value of divide ratio and frequency division mode signal constant when the rst_n invalidating signal.
Model selection and output 3 comprise that mainly 2 select 1 data selector (MUX1) 11, (MUX2) 12,3 select 1 data selector (MUX3) 16, XOR gate 10, logic with shift 13 moves to right, from one adder 14, its inner annexation is: clk_in and z signal connect the input of XOR gate 10, the output of XOR gate 10, clk_in connects 2 value inputs that select 1 data selector 11, y, z connects 2 value inputs that select 1 data selector 12, the n signal connects the input from the one adder 14 and the logic with shift 13 that moves to right, n, n1, n2 connects 3 value inputs that select 1 data selector 16, the mod signal also is connected to 2 and selects 1 data selector 11,2 select 1 data selector 12,3 select the address input end of 1 data selector 16,2 select 1 data selector, 11 output x signals, 2 select 1 data selector, 12 output clk_out signals, and 3 select 1 data selector, 16 output n-signals.
Embodiment 2:
A kind of method of using said apparatus to carry out configurable arbitrary integer half-integer frequency division, as shown in Figure 5, step is as follows:
1): beginning;
2): input divide ratio (n_in) and mode select signal (mod_in), select signal promptly according to frequency division demand input divide ratio n, and according to frequency division demand preference pattern, the frequency division pattern has 5 kinds, when n was the fractional frequency signal of duty ratios such as odd number and needs output, the mod value should be 000; When n is an odd number and when needing output not wait the fractional frequency signal of duty ratio, the mod value should be 001; When n was the fractional frequency signal of duty ratios such as even number and needs output, the mod value should be 010; When n is an even number and when needing output not wait the fractional frequency signal of duty ratio, the mod value should be 011; When needs output n-0.5 fractional frequency signal, promptly during the half-integer fractional frequency signal, the mod value should be 100;
3): apply effective reset signal (rst_n), low level is effective, the part that latchs configuration data will latch the divide ratio (n_in) and the mode signal (mod_in) of input in the step 2, according to mode select signal mod, data selector MUX1 in model selection and the output, MUX2, MUX3 will select the input signal N of corresponding signal as the frequency division counter part, x, thereby produce corresponding frequency-dividing clock x, y feeds back to model selection and output, and by model selection and output according to mod signal output frequency division clock clk_out, whole model selection and output are pure combinational logic; After resetting, reset signal (rst_n) becomes disarmed state, is reduced to high level;
4): input sub-frequency signal (clk_in), frequency divider begins operate as normal, according to step 2) middle divide ratio (n_in) and the mode select signal of importing (mod_in), model selection and output will be exported corresponding signal N and x to the frequency division counter part, simultaneously output frequency division output signal (clk_out);
5): judge whether to need to change divide ratio or frequency division pattern, if then return step 2) re-enter divide ratio (n_in) and mode select signal (mod_in), otherwise change step 4) over to, frequency divider continues output frequency division output signal clk_out signal according to last time setting.
Claims (2)
1. configurable arbitrary integer half integer frequency divider device, comprise that model selection and output, configuration data latch part and frequency division counter part, it is characterized in that model selection and output latch part with configuration data respectively and partly be connected with frequency division counter; Wherein external reset signal is input to configuration data and latchs part and frequency division counter part, divide ratio input signal and frequency division mode input signal are input to configuration data and latch part, treat that sub-frequency clock signal is input to model selection and output, model selection and output output frequency division output signal; Configuration data latchs part and is connected to model selection and output by signal n and mod, and model selection and output are connected to the frequency division counter part by signal N, x, y, z;
Frequency division counter partly comprises 8 up counters, 8 bit comparators, 1 d type flip flop, 1 T trigger, its inner annexation is: signal x receives the input end of clock of 8 up counters and 1 d type flip flop, the numerical value output and the signal N of 8 up counters connect 8 bit comparators, the input of 1 d type flip flop of output termination of 8 bit comparators, the input end of clock of 1 T trigger of output termination of 1 d type flip flop, reset signal connects the reset terminal of 8 up counters, 1 d type flip flop, 1 T trigger, 1 T trigger output signal z;
Configuration data latchs part and mainly comprises 8 latchs and 3 latchs, its inner annexation is: the divide ratio input signal is input to the value input of 8 latchs, the frequency division mode input signal is input to the value input of 3 latchs, 8 latch output signal n, 3 latch output signal mod, reset signal also connects the Enable Pin of 8 latchs and 3 latchs;
Model selection and output comprise that mainly 2 select 1 data selector MUX1,2 select 1 data selector MUX2,3 select 1 data selector MUX3, XOR gate, logic with shift moves to right, from one adder, its inner annexation is: clk_in and z signal connect the input of XOR gate, the output of XOR gate, clk_in connects 2 value inputs that select 1 data selector MUX1, y, z connects 2 value inputs that select 1 data selector MUX2, the n signal connects the input from the one adder and the logic with shift that moves to right, n, n1, n2 connects 3 value inputs that select 1 data selector MUX3, the mod signal also is connected to 2 and selects 1 data selector MUX1,2 select 1 data selector MUX2,3 select the address input end of 1 data selector MUX3,2 select 1 data selector MUX1 output x signal, 2 select 1 data selector MUX2 output clk_out signal, and 3 select 1 data selector MUX3 output n-signal.
2. method of using the described device of claim 1 to carry out configurable arbitrary integer half-integer frequency division, step is as follows:
1): beginning;
2): input divide ratio (n_in) and mode select signal (mod_in), select signal promptly according to frequency division demand input divide ratio, and according to frequency division demand preference pattern, the frequency division pattern has 5 kinds, when n was the fractional frequency signal of duty ratios such as odd number and needs output, the mod value should be 000; When n is an odd number and when needing output not wait the fractional frequency signal of duty ratio, the mod value should be 001; When n was the fractional frequency signal of duty ratios such as even number and needs output, the mod value should be 010; When n is an even number and when needing output not wait the fractional frequency signal of duty ratio, the mod value should be 011; When needs output n-0.5 fractional frequency signal, promptly during the half-integer fractional frequency signal, the mod value should be 100;
3): apply effective reset signal (rst_n), low level is effective, the part that latchs configuration data will latch the divide ratio (n_in) and the mode signal (mod_in) of input in the step 2, according to mode select signal mod, data selector MUX1 in model selection and the output, MUX2, MUX3 will select the input signal N of corresponding signal as the frequency division counter part, x, thereby produce corresponding frequency-dividing clock x, y feeds back to model selection and output, and by model selection and output according to mod signal output frequency division clock clk_out, whole model selection and output are pure combinational logic; After resetting, reset signal (rst_n) becomes disarmed state, is reduced to high level;
4): sub-frequency clock signal (clk_in) is treated in input, frequency divider begins operate as normal, according to step 2) middle divide ratio (n_in) and the mode select signal of importing (mod_in), model selection and output will be exported corresponding signal N and x to the frequency division counter part, simultaneously output frequency division output signal (clk_out);
5): judge whether to need to change divide ratio or frequency division pattern, if then return step 2) re-enter divide ratio (n_in) and mode select signal (mod_in), otherwise change step 4) over to, frequency divider continues output frequency division output signal clk_out signal according to last time setting.
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| CN107666302A (en) * | 2016-07-27 | 2018-02-06 | 株式会社索思未来 | Frequency dividing amendment circuit, receiving circuit and integrated circuit |
| CN108028656A (en) * | 2015-09-15 | 2018-05-11 | 高通股份有限公司 | High-speed programmable Clock dividers |
| CN108834431A (en) * | 2016-03-16 | 2018-11-16 | 三菱电机株式会社 | Variable frequency divider |
| CN108880532A (en) * | 2018-06-25 | 2018-11-23 | 复旦大学 | A kind of integer and half integer frequency divider based on significant condition feedback |
| CN109217867A (en) * | 2017-07-07 | 2019-01-15 | 安徽爱科森齐微电子科技有限公司 | A kind of arbitrary integer frequency divider |
| CN109495107A (en) * | 2018-12-29 | 2019-03-19 | 湖南国科微电子股份有限公司 | A kind of dividing method, shift register and system on chip |
| CN110750129A (en) * | 2019-10-11 | 2020-02-04 | 北京智芯微电子科技有限公司 | Frequency dividing circuit |
| CN113381752A (en) * | 2021-06-24 | 2021-09-10 | 成都纳能微电子有限公司 | Half-frequency dividing circuit and method |
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| CN108028656A (en) * | 2015-09-15 | 2018-05-11 | 高通股份有限公司 | High-speed programmable Clock dividers |
| CN108834431A (en) * | 2016-03-16 | 2018-11-16 | 三菱电机株式会社 | Variable frequency divider |
| CN107666302A (en) * | 2016-07-27 | 2018-02-06 | 株式会社索思未来 | Frequency dividing amendment circuit, receiving circuit and integrated circuit |
| CN109217867A (en) * | 2017-07-07 | 2019-01-15 | 安徽爱科森齐微电子科技有限公司 | A kind of arbitrary integer frequency divider |
| CN108880532A (en) * | 2018-06-25 | 2018-11-23 | 复旦大学 | A kind of integer and half integer frequency divider based on significant condition feedback |
| CN109495107A (en) * | 2018-12-29 | 2019-03-19 | 湖南国科微电子股份有限公司 | A kind of dividing method, shift register and system on chip |
| CN109495107B (en) * | 2018-12-29 | 2023-03-14 | 湖南国科微电子股份有限公司 | Frequency division method, shift register and system on chip |
| CN110750129A (en) * | 2019-10-11 | 2020-02-04 | 北京智芯微电子科技有限公司 | Frequency dividing circuit |
| CN113381752A (en) * | 2021-06-24 | 2021-09-10 | 成都纳能微电子有限公司 | Half-frequency dividing circuit and method |
| CN113381752B (en) * | 2021-06-24 | 2023-02-28 | 成都纳能微电子有限公司 | Half-frequency dividing circuit and method |
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Application publication date: 20110511 |