CN113381752A - Half-frequency dividing circuit and method - Google Patents
Half-frequency dividing circuit and method Download PDFInfo
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- CN113381752A CN113381752A CN202110704005.2A CN202110704005A CN113381752A CN 113381752 A CN113381752 A CN 113381752A CN 202110704005 A CN202110704005 A CN 202110704005A CN 113381752 A CN113381752 A CN 113381752A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
Abstract
The application discloses half frequency division circuit and method, including: the dual-mode frequency division module is used for carrying out N frequency division or N +1 frequency division on the first clock signal based on the selection signal to obtain a first frequency division signal; wherein N is an integer greater than 0; the frequency division module is used for carrying out frequency division on the first frequency division signal to obtain a selection signal; the delay module is used for responding to a second clock signal to delay the first frequency division signal for half a clock cycle of the first clock signal to obtain a second frequency division signal, wherein the second clock signal is a differential clock of the first clock signal; a selection module for selectively outputting the first frequency-divided signal or the second frequency-divided signal based on a selection signal. The circuit adopts an analog circuit design mode, utilizes a differential clock and a simplified circuit structure, and can realize accurate half frequency division under ultrahigh frequency.
Description
Technical Field
The present application relates to frequency division technology, and more particularly, to a half-frequency division circuit and method.
Background
The frequency dividers are generally of two types, one is a frequency divider with pulse waveforms uniformly distributed, namely a conventional frequency divider; another class is frequency dividers where the pulse shape is not uniformly distributed. The conventional frequency divider can only perform integer-multiple frequency division generally, and the frequency division multiple needs to be even. However, in some cases, the clock source and the required frequency are not in even multiple relationship, and at this time, a frequency divider with uneven waveform is needed, and the frequency divider can perform not only integral multiple frequency division but also fractional frequency division, so that relatively continuous frequency output can be obtained. While fractional division is basically implemented in a digitally coded manner by inserting or swallowing pulses. This frequency division is complex in design and is limited by the process size, which is difficult to implement at ultra-high frequencies.
Disclosure of Invention
The purpose of this application lies in: a circuit and a method for realizing accurate half-frequency division under ultra-high frequency are provided.
The application is realized by the following technical scheme:
a half-divide circuit comprising:
the dual-mode frequency division module is used for carrying out N frequency division or N +1 frequency division on the first clock signal based on the selection signal to obtain a first frequency division signal; wherein N is an integer greater than 0;
the frequency division module is used for carrying out frequency division on the first frequency division signal to obtain a selection signal;
the delay module is used for responding to a second clock signal to delay the first frequency division signal for half a clock cycle of the first clock signal to obtain a second frequency division signal, wherein the second clock signal is a differential clock of the first clock signal;
a selection module for selectively outputting the first frequency-divided signal or the second frequency-divided signal based on a selection signal.
When the selection signal is at a high level, the dual-mode frequency division module performs N frequency division on the first clock signal to obtain a first frequency division signal, and the selection module outputs the first frequency division signal.
When the selection signal is at a low level, the dual-mode frequency division module performs N +1 frequency division on the first clock signal to obtain a first frequency division signal, and the selection module outputs a second frequency division signal.
The delay module is a D trigger.
The D trigger is a rising edge D trigger.
A method of half-dividing a frequency, comprising the steps of:
performing N frequency division or N +1 frequency division on the first clock signal based on the selection signal to obtain a first frequency division signal; wherein N is an integer greater than 0;
performing frequency division on the first frequency division signal to obtain a selection signal;
delaying the first frequency-divided signal by half a clock cycle of the first clock signal in response to a second clock signal to obtain a second frequency-divided signal, wherein the first clock signal and the second clock signal are mutually differential clocks;
selectively outputting the first frequency-divided signal or the second frequency-divided signal based on the selection signal.
When the selection signal is at a high level, the first clock signal is subjected to N frequency division to obtain a first frequency division signal, and the first frequency division signal is selectively output based on the selection signal.
When the selection signal is at a low level, the first clock signal is subjected to N +1 frequency division to obtain a first frequency division signal, and a second frequency division signal is selectively output based on the selection signal.
Compared with the prior art, the method has the following beneficial technical effects:
the application adopts an analog circuit design mode, utilizes a differential clock and a simplified circuit structure, and can realize accurate half frequency division under ultrahigh frequency.
Drawings
Fig. 1 is a schematic structural diagram of the circuit of the present application.
Fig. 2 is a timing diagram of the present application.
Detailed Description
All of the features disclosed in this specification, or all of the steps of any method or process so disclosed, may be combined in any combination, except features and/or steps which are mutually exclusive, unless expressly stated otherwise, with other alternative features which are equivalent or similar in purpose, i.e. each feature is an embodiment of a range of equivalent or similar features, unless expressly stated otherwise.
Referring to fig. 1, a half-divide circuit in many embodiments of the present application includes a dual-mode frequency-dividing module 1, a frequency-dividing module 2, a delay module 3, and a selection module 4.
Dual-mode frequency-dividing module 1 includes a clock signal input port Clk, a control port Sel1, and an output port. The first clock signal Clkp is input from the clock signal input port Clk of the dual-mode frequency division module 1, and the output port of the dual-mode frequency division module 1 is electrically connected with the input port in of the halving frequency division module 2, the input port of the delay module 3, and one of the input ports of the selection module 4, respectively. The output port out1 of the frequency dividing module 2 is electrically connected to the control port Sel1 of the dual-mode frequency dividing module 1 and the control port Sel2 of the selecting module 4, respectively. The second clock signal Clkn is input from the clock signal input port of the delay module 3, and the output port of the delay module 3 is electrically connected to the other input port of the selection module 4. Finally, the third frequency-divided signal Out is output from the output port of the selection module 4. The second clock signal Clkn is a differential clock of the first clock signal Clkp.
The dual-mode frequency division module 1 is configured to perform frequency division by N or frequency division by N +1 on the first clock signal Clkp based on the selection signal Sel to obtain a first frequency-divided signal Outp. N is an integer greater than 0.
The frequency halving module 2 is configured to frequency halve the first frequency-divided signal Outp to obtain the selection signal Sel.
The delay module 3 is configured to delay the first divided signal Sel by half a clock cycle of the first clock signal Clkp in response to the second clock signal Clkn to obtain a second divided signal Outn.
The selection module 4 is configured to selectively output the first frequency-divided signal Outp or the second frequency-divided signal Outn based on the selection signal Sel.
For example, when the selection signal is at a high level, the dual-mode frequency division module 1 divides the first clock signal by N to obtain a first frequency division signal, and the selection module 4 outputs the first frequency division signal. When the selection signal is at a low level, the dual-mode frequency division module 1 performs N +1 frequency division on the first clock signal to obtain a first frequency division signal, and the selection module 4 outputs a second frequency division signal.
The delay module 3 may be, but is not limited to, a D flip-flop. The D flip-flop is a rising edge D flip-flop.
The invention relates to a half frequency division method, which comprises the following steps:
performing N frequency division or N +1 frequency division on the first clock signal Clkp based on the selection signal Sel to obtain a first frequency division signal Outp;
performing frequency division on the first frequency division signal Clkp to obtain a selection signal;
delaying the first frequency-divided signal Sel by half a clock cycle of the first clock signal Clkp in response to a second clock signal Clkn to obtain a second frequency-divided signal Outn, wherein the second clock signal Clkn is a differential clock of the first clock signal Clkp;
selectively outputting the first frequency-divided signal or the second frequency-divided signal based on the selection signal Sel.
When the selection signal is at a high level, the first clock signal is subjected to N frequency division to obtain a first frequency division signal, and the first frequency division signal is selectively output based on the selection signal. When the selection signal is at a low level, the first clock signal is subjected to N +1 frequency division to obtain a first frequency division signal, and a second frequency division signal is selectively output based on the selection signal.
As shown in fig. 1 and 2, the input second clock signal Clkn is a differential clock of the first clock signal Clkp. The first clock signal Clkp is a clock signal of the dual-mode frequency division module 1, the selection signal Sel initially output by the binary frequency division module 2 is 1 or 0, the dual-mode frequency division module 1 is controlled to perform N frequency division or N +1 frequency division, and a first frequency division signal Outp is output. The first frequency-divided signal Outp is supplied to the frequency-dividing module 2 as an input signal of the frequency-dividing module 2, the first frequency-divided signal Outp is divided by two, and at the end of one period of the first frequency-divided signal Outp, a selection signal Sel output by the frequency-dividing module 2 generates a jump from 1 to 0 or from 0 to 1. The jump of the selection signal Sel switches the frequency dividing ratio of the dual-mode frequency dividing module 1, and the whole process is repeated. The final first divided signal Outp is shown as a clock signal that alternates between divide-by-N or divide-by-N +1 with the first clock signal Clkp.
The first frequency-divided signal Outp is sampled by a rising edge of the second clock signal Clkn through the delay module 3, i.e. the D flip-flop, the rising edge time of the second clock signal Clkn corresponds to the falling edge time of the first frequency-divided signal Outp, and the second frequency-divided signal Outn is delayed by half the clock period of the first clock signal clkp relative to the first frequency-divided signal Outp.
The selection signal Sel output by the frequency division module 2 is also used as a selection signal of the selection module 4, when the selection signal is at a high level, the dual-mode frequency division module 1 performs N frequency division on the first clock signal to obtain a first frequency division signal, and the selection module 4 outputs the first frequency division signal; when the selection signal is at a low level, the dual-mode frequency division module 1 performs N +1 frequency division on the first clock signal to obtain a first frequency division signal, and the selection module 4 outputs a second frequency division signal. As can be seen, the finally obtained third frequency-divided signal Out is obtained by dividing the first clock signal by N, i.e., the first frequency-divided signal is divided by N +0.5, and the first clock signal is divided by N +1 to 0.5, so that the two signals delayed by 1/2clk clock cycles are successfully integrated into the divided-by-N +0.5 clock signal.
In the structure, all modules are designed in an analog circuit mode, and compared with a digital design mode, the working speed has great advantage, so that the structure can be used for dividing the frequency of a clock signal by half at a super-high speed.
The foregoing is directed to embodiments of the present invention, which are not limited thereto, and any simple modifications and equivalents thereof according to the technical spirit of the present invention may be made within the scope of the present invention.
Claims (8)
1. A half-divide circuit, comprising:
the dual-mode frequency division module is used for carrying out N frequency division or N +1 frequency division on the first clock signal based on the selection signal to obtain a first frequency division signal; wherein N is an integer greater than 0;
the frequency division module is used for carrying out frequency division on the first frequency division signal to obtain a selection signal;
the delay module is used for responding to a second clock signal to delay the first frequency division signal for half a clock cycle of the first clock signal to obtain a second frequency division signal, wherein the second clock signal is a differential clock of the first clock signal;
a selection module for selectively outputting the first frequency-divided signal or the second frequency-divided signal based on a selection signal.
2. The circuit of claim 1, wherein the dual-mode divider module divides the first clock signal by N to obtain a first divided signal when the selection signal is at a high level, and the selection module outputs the first divided signal.
3. The circuit of claim 1, wherein the dual-mode divider module divides the first clock signal by N +1 to obtain a first divided signal and the selection module outputs a second divided signal when the selection signal is at a low level.
4. The divide-by-half circuit of claim 1, wherein the delay module is a D flip-flop.
5. The divide-by-half circuit of claim 1, wherein the D flip-flop is a rising edge D flip-flop.
6. A method of half-dividing a frequency, comprising the steps of:
performing N frequency division or N +1 frequency division on the first clock signal based on the selection signal to obtain a first frequency division signal; wherein N is an integer greater than 0;
performing frequency division on the first frequency division signal to obtain a selection signal;
delaying the first frequency-divided signal by half a clock cycle of the first clock signal in response to a second clock signal to obtain a second frequency-divided signal, wherein the first clock signal and the second clock signal are mutually differential clocks;
selectively outputting the first frequency-divided signal or the second frequency-divided signal based on the selection signal.
7. The half-dividing method as claimed in claim 6, wherein when the selection signal is high, the first clock signal is divided by N to obtain a first divided signal, and the first divided signal is selectively outputted based on the selection signal.
8. The half-division method according to claim 6, wherein when the selection signal is at a low level, the first clock signal is divided by N +1 to obtain a first divided signal, and the second divided signal is selectively output based on the selection signal.
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Address after: Building 4, 5th Floor, No. 1858 Yizhou Avenue Middle Section, Chengdu High tech Zone, China (Sichuan) Pilot Free Trade Zone, Chengdu City, Sichuan Province, 610095 Patentee after: Nano Microelectronics (Chengdu) Co.,Ltd. Country or region after: Zhong Guo Address before: 610041 No. 704, floor 7, building 1, No. 1800, middle section of Yizhou Avenue, Chengdu hi tech Zone, China (Sichuan) pilot Free Trade Zone, Chengdu, Sichuan Patentee before: Chengdu Naneng Microelectronics Co.,Ltd. Country or region before: Zhong Guo |
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