CN105335105A

CN105335105A - QDR IV ultrahigh-speed storage controller suitable for FPGA

Info

Publication number: CN105335105A
Application number: CN201510966465.7A
Authority: CN
Inventors: 王鹏; 龚克; 涂友超; 连帅彬; 孙秋菊; 黄文霞
Original assignee: Xinyang Normal University
Current assignee: Xinyang Normal University
Priority date: 2015-12-22
Filing date: 2015-12-22
Publication date: 2016-02-17
Anticipated expiration: 2035-12-22
Also published as: CN105335105B

Abstract

The invention discloses a QDR IV ultrahigh-speed storage controller suitable for an FPGA. The QDR IV ultrahigh-speed storage controller is composed of a clock tree, an overall reset module, a high-speed input/output interface module, a user low-speed read-write access module and a master control module. The clock tree mainly receives QKB clock signals output by an external 125MHz clock and a QDR chip, and after being subjected to phase locking through a PLL, the QKB clock signals are transmitted to an overall clock network to drive various programmable resources in the FPGA. The overall reset module is used for resetting necessary registers in the master control module and the high-speed input/output interface module. The master control module mainly finishes initialization and read-write testing on the whole controller. The high-speed input/output interface module and the user low-speed read-write access module are used for finishing reliable conversion of high-speed and low-speed clock signals. Ultrahigh-speed reliable read-write under the 500MHz double data rate is achieved, other modules in the FPGA only need to have access to external ports of the controller under drive of a single 125MHz clock rising edge, and seamless connection of all QDR IV chips on the current market is supported.

Description

A kind of QDR IV hypervelocity memory controller being applicable to FPGA

Technical field

The present invention relates to Highspeed Data Transmission Technology and FPGA application and development, particularly relate to a kind of QDRIV hypervelocity memory controller being applicable to FPGA.

Background technology

QDRIV be the 4th generation quad data rate storer English abbreviation, it has high opportunistic transmission speed, can be used in many occasions such as Radar Signal Processing, network route switching.FPGA is then the English abbreviation of field programmable gate array, carries the function of arithmetic core in many signal processing platforms.

In order to promote storage capacity, usually need in FPGA design to adopt QDRIV as the outer mass storage of sheet, but due to the inner structure of complexity and cabling strategy, the frequency of operation of FPGA internal logic is difficult to obtain essence and improves, this causes the frequency of operation of many FPGA system and peripheral chip to there is larger difference, is difficult to the over-all properties giving full play to peripheral chip.At present, although there are some to design QDR, QDRII read-write controller achieved based on FPGA, QDR, QDRII etc. all belong to the early production of QDR, and its frequency of operation is generally lower and read-write sequence simple, and corresponding FPGA design difficulty is less.And after QDR memory operation speed is more than 200MHz, FPGA design difficulty based on prior art just increases greatly, be difficult to ensure the static timing convergence of design and the accuracy of different operating temperature down-sampling clock phase, and then cause read-write to occur mistake, many designs adopt the scheme of the multiple clock strategy of manual testing to revise this problem, but not there is universality, and also very easily there is various problem in a large amount of manual debuggings.

In sum, at present for up-to-date QDRIV storer, because its frequency of operation is high, accessing time sequence is complicated, not yet there is corresponding FPGA hypervelocity read-write controller solution.

Summary of the invention

Be difficult to the defects such as the stability reaching high frequency of operation and ensure sampling clock phase when utilizing FPGA to complete the design of QDRIV memory controller for existing correlation technique, the technical problem to be solved in the present invention is to provide a kind of complete QDRIV hypervelocity Implementing Memory Controllers strategy, by rational clock tree design and accurate path delay control strategy, the maximum operation frequency of whole controller and QDRIV chip is made to reach 500MHz, equivalence opportunistic transmission speed reaches 2GT/s, support the seamless link with current all QDRIV chips on the market, and enough sequential allowances are all had under the full operating temperature range of FPGA, the correctness of data sampling can be ensured without the need to manual search optimum phase.It is process core and need in the digital information processing system of high throughput with FPGA that the present invention is applicable to various.

For solving the problems of the technologies described above, the present invention by the following technical solutions:

Be applicable to a QDRIV hypervelocity memory controller of FPGA, it is characterized in that: be made up of Clock Tree, Global reset module, high speed input/output interface module, user's low speed read and write access module and main control module, wherein:

Clock Tree, the data of the reference frequency clock and the output of QDRIV chip that receive outside input are with road clock, and complete clock regeneration and process of frequency multiplication, regeneration time clock and input clock have the phase relation known, the clock signal that Clock Tree exports is for Global reset module, high speed input/output interface module, user's low speed read and write access module and main control module.

Global reset module, the asynchronous reset signal of the outside input of reception, exports after synchronously process, as the global reset signal of the necessary register of reset main control module and high speed input/output interface module inside.

High speed input/output interface module, receives QDRIV chip high speed signal and is converted to speed parallel signals, and delivering to main control module and user's low speed read and write access module; Export the work clock of QDRIV chip; Receive user's low speed read and write access module speed parallel signals and be converted to high speed signal and export QDRIV chip to.

User's low speed read and write access module, the test data produce main control module or controller outside port data deliver to high speed input/output interface module; The QDRIV retaking of a year or grade low-speed parallel data exported by high speed input/output interface module is delivered to after depositing the outside port of main control module and controller.

Main control module, realizes the switching of QDRIV chip reset pattern, readwrite tests pattern and normal mode of operation; Produce test signal, and complete through user's low speed read and write access module and high speed input/output interface module test operation is write to QDRIV chip; Under readwrite tests pattern, verify that whether QDRIV chip write data are consistent with back read data, normal mode of operation is switched to when completely the same, receive controller exterior read-write port signal by user's low speed read and write access module, complete QDRIV chip high speed read-write operation.

Described Global reset module, comprise the first register of mutual cascade, the second register and the 3rd register, asynchronous reset signal for being inputted outside is converted to the synchronous reset signal under FPGA local clock territory, the register of reset main control module and the inner necessity of high speed input/output interface module and programmable resource.

Described high speed input/output interface module, comprises input path chronotron array, deserializer array, transitional slide device array I, transitional slide device array II, parallel-to-serial converter array I ~ parallel-to-serial converter array V, outgoing route chronotron array I ~ outgoing route chronotron array III; Wherein:

Input path chronotron array, for applying extra time delay to reading from QDRIV chip the data obtained, style of being alignd at edge is modified to center alignment style, meets the input timing requirement of FPGA high speed serial parallel exchange device array, then exports deserializer array to.

Deserializer array, for receiving the QDRIV chip high speed signal exported through the conversion of input path chronotron array, serioparallel exchange is export slip shifter array I to after low speed signal.

Transitional slide device array I, receives the shift control signal of main control module, reorders, to realize the correct alignment of data to the output data of deserializer array.

Parallel-to-serial converter array I, for exporting QDRIV chip operation clock and data input clock signal.

Parallel-to-serial converter array II, for exporting the complementary inversion signal of QDRIV chip operation clock and data input clock signal.

Parallel-to-serial converter array III, for the read-write control signal from user's low speed read and write access module is converted to high speed signal, exports QDRIV chip to after the time delay of outgoing route chronotron array I.

Transitional slide device array II, for the data of writing from user's low speed read and write access module are reordered, and be converted to high speed signal through parallel-to-serial converter array IV, after the time delay of outgoing route chronotron array II, export QDRIV chip to successively, the data of writing finally realized under high speed clock domain postpone 5 clock period than write address and control signal.

Parallel-to-serial converter array IV, is converted to high speed signal for the data of writing exported by transitional slide device array II, and exports QDRIV chip to after the time delay of outgoing route chronotron array II.

Outgoing route chronotron array II, carries out time delay for the high speed signal exported parallel-to-serial converter array IV, to meet the timing requirements of QDRIV chip.

Parallel-to-serial converter array V, for the read/write address from user's low speed read and write access module is converted to high speed signal, exports QDRIV chip to after the time delay of outgoing route chronotron array III.

Outgoing route chronotron array III, carries out time delay for the high speed signal exported parallel-to-serial converter array V, to meet the timing requirements of QDRIV chip.

In described transitional slide device array I and transitional slide device array II, transitional slide device input signal comprises 8 Bit data DIN, operating clock signals CLK, and 3 Bit datas select port SEL signals; DIN exports and obtains DIN_d1 after D register is deposited, the relative DIN of DIN_d1 has the time delay of a CLK clock period, then by signal DIN and DIN_d1, through position, splicing obtains 16 new bit width variablees, then therefrom sequentially 8 Bit datas are chosen respectively by 8 rearrangement device, the output of these 8 rearrangement device is delivered to 8 simultaneously and is selected 1 data selector, is determined the data of which group rearrangement device to export by the value of data selector data selection port SEL signal; In transitional slide device array I, the data selection port SEL signal of data selector is produced by main control module and variable, in transitional slide device array II, the data selection port SEL signal of data selector then fixedly connects 3 bits 101, low literary sketch data to be misplaced 5 bits than write address and control signal, reach high speed clock domain after parallel-serial conversion under, exports the object comparing 5 clock period of input delay.

Described user's low speed read and write access module, comprises data selector array I ~ data selector array III, and register array I ~ register array IV; Wherein:

Data selector array I, receives the data select signal of main control module, the test writing data or main control module of controller outside is read and write data and export register array I to.

Data selector array II, receives the data select signal of main control module, by the write address array of controller outside, read address array, or the test reading address array of main control module exports register array II to.

Data selector array III, receives the data select signal of main control module, by the write enable signal of controller outside, reads enable signal, or the test write enable signal of main control module, reads enable signal and export register array III to.

Register array I ~ register array III, for the signal that registered data selector switch array I ~ data selector array III exports, and is sent to the reading-writing port of QDRIV chip through high speed input/output interface module.

Register array IV, delivers to main control module and controller outside port for after the QDRIV chip read-back data register that exported by high speed input/output interface module.

When main control module is under readwrite tests pattern, the test data that main control module produces is utilized data selector array I ~ data selector array III, and register array I ~ register array III delivers to high speed input/output interface module and the final reading-writing port arriving QDRIV chip; When main control module in the normal mode of operation time, then controller exterior read-write port signal is utilized data selector array I ~ data selector array III, register array I ~ register array III delivers to high speed input/output interface module and the final reading-writing port arriving QDRIV chip, also the QDRIV chip read-back data exported by high speed input/output interface module is delivered to main control module and controller outside port after register array IV is deposited simultaneously.

Described main control module comprises reset timing generator, pseudorandom number generator, readwrite tests module, transitional slide data recorder, major state machine; Wherein:

Reset timing generator, the enable and reset timing produced needed for QDRIV chip by major state machine.

Pseudorandom number generator, for generation of pseudo-random data, exports test through readwrite tests module and reads and writes data.

Transitional slide data recorder, the shift index value of the transitional slide device of record high speed input/output interface module, exports the data selection port of data selector in shift control signal to the transitional slide device array I of high speed input/output interface module.

Readwrite tests module, receive pseudo-random data that pseudorandom number generator exports and export test and read and write data, produce and test write address, test write enable signal accordingly, and finally complete through user's low speed read and write access module and high speed input/output interface module test operation is write to QDRIV chip; The data utilizing pseudorandom number generator to export carry out the comparison writing data and back read data, look out for mistakes, regulate transitional slide data recorder with the data selection port of data selector in the transitional slide device array I upgrading high speed input/output interface module.

Major state machine, control reset timing generator, pseudorandom number generator, readwrite tests module, transitional slide data recorder works in order, QDRIV chip reset pattern is realized by state machine, the switching of readwrite tests pattern and normal mode of operation, under readwrite tests pattern, the reading-writing port of QDRIV chip is taken by main control module, QDRIV chip is write and retaking of a year or grade by pseudorandom number generator, then progressively regulate transitional slide data recorder with the data selection port of data selector in the transitional slide device array I upgrading high speed input/output interface module, finally prove that readwrite tests passes through when writing data and being identical with back read data, normal mode of operation can be proceeded to, and the reading-writing port control of QDRIV chip is gone to controller exterior read-write port.

Described Clock Tree, comprises Clock management module I, Clock management module II, Clock management module III, and 8 global routing's resources, wherein, the reference frequency clock of outside input is through global clock resource I, 3 road clocks are exported after Clock management module I, described 3 road clocks export separately after the process of a global clock resource: the output of global clock resource IV is used for the low-speed clock logic of driving governor, the work clock of main control module and user's low speed read and write access module is provided, the output of global clock resource V is used for input path chronotron in high speed input/output interface module, the operating reference clock of outgoing route chronotron, the output of global clock resource VI is used for high speed input/output interface module, the high-frequency clock logic of driving governor, QDRIV chip export one group of data output clock signal through global clock resource II, Clock management module II, global routing's resource VII export after for driving the deserializer array of high speed input/output interface module, another of QDRIV chip output organizes data output clock signal after global clock resource III, Clock management module III, global routing's resource VIII export for driving the deserializer array of high speed input/output interface module.

The present invention is by rational clock tree design and specialized high-speed serial data and the use of modular converter, the external pin interface transfer clock of FPGA is made to reach 500MHz, support Double Data Rate transmission (DoubleDataRate, DDR), and adopt input path chronotron and outgoing route chronotron to carry out extra time delay to key signal, the edge alignment formatted data that QDRIV chip can be exported is modified to center alignment form and then carries out data receiver, show after the static timing tool analysis of specialty, whole design still reaches good timing Design allowance under 500MHz high-frequency clock frequency, and the stability of Signal transmissions is not by the impact of high/low temperature change, the highest equivalent opportunistic transmission speed of this controller support is 2GT/s, super existing all kinds of QDR memory controller design far away.Use the present invention greatly can improve read-write efficiency and the handling capacity of FPGA access chip external memory, and then improve system performance.

Accompanying drawing explanation

Fig. 1 is structural principle block diagram of the present invention.

Fig. 2 is Clock Tree cut-away view of the present invention.

Fig. 3 is Global reset inside modules structural drawing of the present invention.

Fig. 4 is parallel-to-serial converter external interface figure of the present invention.

Fig. 5 is parallel-to-serial converter working timing figure of the present invention.

Fig. 6 is deserializer external interface figure of the present invention.

Fig. 7 is deserializer working timing figure of the present invention.

Fig. 8 is transitional slide device cut-away view of the present invention.

Fig. 9 is that edge alignment is modified to center alignment working timing figure by input path chronotron of the present invention.

Figure 10 is high speed input/output interface module cut-away view of the present invention.

Figure 11 is user's low speed read and write access inside modules structural drawing of the present invention.

Figure 12 is main control module inner structure of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

Current QDRIV storer mainly contains 72Mbit and 144Mbit two kinds of specifications, without loss of generality, the QDRIV storer CY7C4142 that the present embodiment is maximum with current capacity, data bit width the is maximum and XCKU060-FFVA1156-2 type FPGA of Xilinx company is representative, describes the technical scheme of memory controller of the present invention.In the specific embodiment of the present invention, refer to that at a high speed signal intensity frequency is 500MHz, low speed is then 1/4th of this high speed signal frequency, i.e. 125MHz, but be not limited to this characteristic frequency in practical application, usual fast frequency interval is signal frequency 200 ~ 500MHz, and low speed frequency interval is 50 ~ 125MHz.

1, overall construction design

QDRIV has 2 groups of real independently reading and writing data and control buss simultaneously, only use single-chip also can realize dual-port read-write operation, but the external interface signal of QDRIV chip is also more simultaneously, table 1 lists the key signal and explanation thereof that need in the present invention's design.

The list of table 1QDRIV chip key signal

In the signal that table 1 is listed, except RST_ is LVCMOS level, all the other signals all support HSTL and POD two kinds of level by exterior arrangement, but consider that the FPGA device of support POD level is at present still less, and HSTL level therefore can be adopted to carry out respective design.In addition, although DQA, DQB of QDRIV chip are bidirectional port, but the simple dual port RAM scheme of many employings in practical application, namely one of them port is only for read operation, another port is only for write operation, the present invention also uses this strategy, and DQA is used for realizing write operation, and DQB is used for realizing read operation.

The one-piece construction block diagram of QDRIV controller of the present invention as shown in Figure 1.

This controller is primarily of Clock Tree, Global reset module, main control module, high speed input/output interface module, these 5 module compositions of user's low speed read and write access module, the QDR chip of its peripheral is mainly connected with high speed input/output interface module with Clock Tree, in addition, in order to make whole system normally work, its exterior provides reset signal and work clock.The present invention adopts the effective asynchronous reset signal of high level and 125MHz crystal oscillator clock, because crystal oscillator clock frequency is higher, LVDS differential level form can be adopted to export this clock.

In Fig. 1, the QKB clock signal that the outside 125MHz clock of Clock Tree primary recipient and QDR chip export, completes after PGC demodulation through PLL and delivers to global clock network to drive the inner various programmable resource of FPGA; Global reset module is for main control module and the inner necessary register of high speed input/output interface module of resetting; Main control module inside comprises again a complex state machine and a series of submodule, mainly completes initialization and the readwrite tests of whole controller; High speed input/output interface module and user's low speed read and write access module are then for completing the reliable conversion of high-speed clock signal and low-speed clock signal, and the frequency of operation of other this controller of module accesses of FPGA is only 125MHz, and only access at the rising edge time of clock, significantly reduce the timing Design pressure of FPGA all the other modules inner.

Below introduce the detailed design implementation strategy of each module.

2, clock tree design

Clock Tree, comprises Clock management module I, Clock management module II, Clock management module III, and 8 global routing's resources; Wherein, the reference frequency clock of outside input exports 3 road clocks after global clock resource I, Clock management module I, described 3 road clocks export separately after the process of a global clock resource: the output of global clock resource IV is used for the low-speed clock logic of driving governor, provides the work clock of main control module and user's low speed read and write access module; The output of global clock resource V is used for the operating reference clock of input, outgoing route chronotron array in high speed input/output interface module; The output of global clock resource VI is used for high speed input/output interface module, the high-frequency clock logic of driving governor.QDRIV chip export one group of data output clock signal through global clock resource II, Clock management module II, global routing's resource VII export after for driving the deserializer array of high speed input/output interface module; Another of QDRIV chip output organizes data output clock signal after global clock resource III, Clock management module III, global routing's resource VIII export for driving the deserializer array of high speed input/output interface module.

The Clock Tree input clock of the present embodiment comprises following three groups of signals:

(1) its exterior input 125MHz clock CLK_EXT, level form is LVDS;

(2) QKB [0] of QDRIV chip output, level form is HSTL;

(3) QKB [1] of QDRIV chip output, level form is HSTL.

Above-mentioned three groups of signals all need global clock pin (hereinafter referred to as the GC pin) pin through FPGA is special to deliver to FPGA inside, then separately complete clock regeneration and process of frequency multiplication through global clock resource and Clock management module, whole Clock Tree structural drawing as shown in Figure 2.

In Fig. 2, global clock resource is a kind of specific resource in FPGA, for strengthening the driving force of clock and improving the inconsistency that clock arrives each programmable resource; Clock management module is a kind of programmable resource of FPGA, can complete various clock division, frequency multiplication operation.The present invention uses 3 groups of Clock management modules altogether, wherein Clock management module I regenerates and frequency multiplication CLK_EXT, export 3 tunnel clock signals and export through global clock resource, this 3 road clock sources frequency is respectively 125MHz, 250MHz, 500MHz, therefore be denoted as CLK_125M separately, CLK_250M, and CLK_500M.

CLK_125M frequency is minimum, and be applicable to the inner General Logic of FPGA and timing component use, it is mainly used in the work clock providing main control module and user's low speed read and write access module in the present invention.CLK_250M is then the operating reference clock for providing FPGA inner input and output programmable delay module.CLK_500M frequency is the highest, mainly for the high speed input/output interface module of FPGA.CLK_QKB0 and CLK_QKB1 derives from QKB [0] and QKB [1] respectively, and frequency of operation is also 500MHz, but and there is certain phase differential between CLK_500M, mainly for the high speed input/output interface module of FPGA.

It should be noted that, because CLK_QKB0 and CLK_QKB1 frequency of operation is very high, and QDR chip is simultaneously in rising edge and the negative edge transmission data of clock, cause actual effective data capture window very limited, therefore the time delay relativeness of this two-way clock and DQB data routing must accurately ensure, for this reason, Clock management module 2 and necessary its phase alignment function enable of Clock management module 3 module, to make CLK_QKB0/CLK_QKB1 clock and QKB [0]/QKB [1] the clock phase Accurate align of output.So just can reach the correct object catching data by rational data routing planning in subsequent designs.

3, Global reset modular design

Reseting module is used under system electrification or external reset state, resetting relevant register to eliminate its indefinite state, and many FPGA designs use reset signal with all registers and other programmable resource of resetting usually in a large number.But the fan leaves coefficient that this reposition strategy can cause global reset signal high, and then significantly increase reset signal cabling complexity and path delay, ultimately limit the maximum operation frequency of whole design.In fact, the object of most reset signal has been only used for initialization of register, and this can realize simply by variable initialize, register and the programmable resource of therefore only tackling some necessity carry out resetting, to simplify the sequential of reset path, thus reach the object of improving SNR, reduction face sum reduction power consumption on the whole.

Because reset signal derives from outside port input, a typical asynchronous signal to FPGA internal work clock, therefore need to carry out synchronization to it, as shown in Figure 3, Global reset inside modules is provided with the first register of mutual cascade, second register and the 3rd register, make asynchronous signal through multistage synchronous after the global reset signal finally become under FPGA local clock territory export, the register of reset main control module and the inner necessity of high speed input/output interface module and programmable resource, wherein RST is input signal, RST_D1 ~ RST_D3 is the signal after D register synchronization, RST_D3 is the output of whole module, this signal have passed through 3 grades of register synchronization, metastable probability can be made to be reduced to can ignore.And the comparable asynchronous reset strategy of synchronous reset strategy that the present invention adopts makes the maximum operation frequency of comprehensive rear circuit improve, and static timing analysis efficiency also greatly improves.

4, high speed input/output interface module design

High speed input/output interface module, comprises input path chronotron array, deserializer array, transitional slide device array I, transitional slide device array II, parallel-to-serial converter array I ~ parallel-to-serial converter array V, outgoing route chronotron array I ~ outgoing route chronotron array III; Wherein:

Input path chronotron array, for applying extra time delay to reading from QDRIV chip the data obtained, style of being alignd at edge is modified to center alignment style, meets the input timing requirement of FPGA high speed serial parallel exchange device array, then exports deserializer array to;

Deserializer array, for receiving the QDRIV chip high speed signal exported through the conversion of input path chronotron array, serioparallel exchange is export slip shifter array I to after low speed signal;

Transitional slide device array I, receives the shift control signal of main control module, reorders, to realize the correct alignment of data to the output data of deserializer array;

Parallel-to-serial converter array I, for exporting QDRIV chip operation clock and data input clock signal;

Parallel-to-serial converter array II, for exporting the complementary inversion signal of QDRIV chip operation clock and data input clock signal;

Parallel-to-serial converter array III, for the read-write control signal from user's low speed read and write access module is converted to high speed signal, exports QDRIV chip to after the time delay of outgoing route chronotron array I;

Transitional slide device array II, for the data of writing from user's low speed read and write access module are reordered, and be converted to high speed signal through parallel-to-serial converter array IV, after the time delay of outgoing route chronotron array II, export QDRIV chip to successively, the data of writing finally realized under high speed clock domain postpone 5 clock period than write address and control signal;

Parallel-to-serial converter array IV, is converted to high speed signal for the data of writing exported by transitional slide device array II, and exports QDRIV chip to after the time delay of outgoing route chronotron array II;

Outgoing route chronotron array II, carries out time delay for the high speed signal exported parallel-to-serial converter array IV, to meet the timing requirements of QDRIV chip;

Parallel-to-serial converter array V, for the read/write address from user's low speed read and write access module is converted to high speed signal, exports QDRIV chip to after the time delay of outgoing route chronotron array III;

QDR chip uses rising edge clock and negative edge transmission data simultaneously, i.e. so-called ddr mode, and the work clock of QDR chip can reach 500MHz in the present invention, therefore in fact real effective data hold time length only have about 1ns, so high message transmission rate is the register of FPGA inside, the conventional resource such as look-up table is difficult to bear, for this reason, the present invention adopts the high speed parallel-to-serial converter in FPGA and deserializer hardware primitive to complete the switching in high speed clock domain and low-speed clock territory, its conversion is than reaching 1:8, therefore, the data to be written of QDRIV chip only need with the single data speed (SingleDataRate of 125MHz, SDR) high speed parallel-to-serial converter assembly is write, then through 8:1 parallel-serial conversion, the frequency of operation exporting data is increased to 500MHz, and switch to ddr mode by SDR pattern.Similarly, the ddr mode 500MHz frequency data that QDR chip exports also obtain SDR mode data under 125MHz by deserializer assembly after 1:8 serioparallel exchange.

The external interface of high speed parallel-to-serial converter assembly and work schedule are as shown in Figure 4 and Figure 5.High speed parallel-to-serial converter assembly can receive at most 8 channel parallel data inputs under the driving of CLK_DIV, and is converted into 1 road high-speed serial data DQ, and then under the driving of high-frequency clock CLK, DQ exports the data of D1 ~ D8 successively.

Deserializer assembly can be regarded as the inverse transformation of parallel-to-serial converter, it can by the high speed data conversion that receives to low-speed clock territory, the deserializer component interface signal of different FPGA device is slightly different, for the XCKU060-FFVA1156-2 type FPGA of Xilinx company, its external interface and work schedule are respectively as shown in Figure 6 and Figure 7.Wherein D and CLK is input high-speed data and with road synchronous clock respectively, FIFO_RD_CLK is that FIFO reads clock, at 1:8DDR string and than under pattern, its frequency is 1/4 of CLK, FIFO_RD_EN is that FIFO reads enable signal, FIFO_EMPTY is FIFO sky mark, high level is effective, Q1 ~ Q8 is for exporting parallel data, it drives clock to be FIFO_RD_CLK, therefore only need when detecting that FIFO_EMPTY is low level, putting FIFO_RD_EN is high level, can obtain the data after unstringing in the next FIFO_RD_CLK clock period from Q1 ~ Q8 port.

But, needs explicitly point out, due to the phase difference between CLK and CLK_DIV, and deserializer has needed clock-domain crossing data process, work schedule shown in Fig. 7 is only one of multiple sequential that possible occur, during CLK1 in the figure 7, it is likely also XABCDEFG that Q1 ~ Q8 exports data, BCDEFGHI, CDEFGHIJ etc.Shifted relationship is there is between this multiple sequential, identical in order to ensure that the Q1 ~ Q8 of all deserializer assemblies exports data style, wish that Q1 always exports D port first data after FIFO_RD_CLK rising edge, and by that analogy.For this reason, need to export data slip shift function for deserializer increases, below introduce the realization of data slip shift function.

As shown in Figure 8, in transitional slide device array I and transitional slide device array II, the input signal of transitional slide device comprises 8 Bit data DIN, operating clock signals CLK, and 3 Bit datas select port SEL signals.DIN holds output to obtain DIN_d1 from Q in transitional slide device inside after D register is deposited, and the relative DIN of this signal has the time delay of a CLK clock period.Then by DIN and DIN_d1, through position, splicing obtains 16 new bit width variablees, and then therefrom sequentially choose 8 Bit datas by 8 rearrangement device, if 16 bit width variablees are ABCDEFGHIJKLMNOP, then the output of 8 rearrangement device is respectively:

Rearrangement device I:ABCDEFGH;

Rearrangement device II:BCDEFGHI;

Rearrangement device III:CDEFGHIJ;

Rearrangement device IV:DEFGHIJK;

Rearrangement device V:EFGHIJKL;

Rearrangement device VI:FGHIJKLM;

Rearrangement device VII:GHIJKLMN;

Rearrangement device VIII:HIJKLMNO;

The output of these 8 rearrangement device is delivered to 8 simultaneously and is selected 1 data selector, is determined the data of which group rearrangement device to export by the value of data selector data selection port SEL signal.After using this transitional slide device, no matter deserializer exports Q1 ~ Q8 data and how to misplace, and always can find out one group of correct output pattern by the value (Binary Zero 00-111, the i.e. decimal system 0 ~ 7) of traversal SEL.Transitional slide device array I is substantially identical with the inner structure of transitional slide device array II, but the former data selector data selection port SEL signal comes from main control module and variable, the QDR alignment of data obtained is read for realizing, and the data selector data selection port SEL signal of the latter is fixed as 3 bits 101, low literary sketch data to be misplaced 5 bits than write address and control signal, after parallel-serial conversion, reaches the object that high speed output data compares input 5 clock period of data delay.

In addition, the input and output of QDRIV all have employed the source method of synchronization, need ensure QDRIV input signal change all with CK clock stringent synchronization, and data grid technology alignment style, as CY7C4142 requires Time Created and retention time to be not less than 0.125ns, and require to write the time delay that the relative write address of data and control signal have 5 CK cycles.

Retention time requirement is set up in order to reach, CK signal can directly be exported by parallel-to-serial converter, other data and control signal then need export pin to rear the increasing after outgoing route chronotron (FPGA private resource can be used to realize) completes the delay operation of about 0.5ns of parallel-to-serial converter output signal again, can under the frequency of operation of 500MHz, make the retention time of setting up of the relative CK clock of these signals all can reach about 0.5ns, beyond databook requirement, also ensure that larger sequential allowance simultaneously.

The retention time of setting up adopting outgoing route chronotron to complete output signal requires it is the improvement of the relatively many existing designs of the present invention, many designs reach same object by adjustment PLL output clock phase, but this method can take valuable Clock management module and global routing's resource, and outgoing route chronotron all has distribution in each FPGAIO pin, and do not take any register and LUT resource, can the time delay of auto-compensation high/low temperature change, also can not reduce quality of output signals, adopt under being extremely adapted at high-speed high frequency occasion.

In order to meet QDRIV sequential, need to ensure to write the delay effect that the relative write address of data DQA and control signal have 5 CK cycles, because 5 CK cycles have exceeded the maximum delay length 1.25ns of outgoing route chronotron, therefore outgoing route chronotron can not be re-used, but before DQA data enter parallel-to-serial converter, also can add a transitional slide device assembly same as shown in Figure 8, and utilize this assembly to remain to export data all the time than input data shift right 5 bit.

Similarly, according to the requirement of QDRIV databook, the 36 bit width data bus DQB of QDRIV output signal change then with QKB clock stringent synchronization, and data are edge alignment style, are no more than 0.1ns as CY7C4142 exports DQB data relative QKB clocks along front and back maximum jitter.But, the deserializer of FPGA can only the data of receiving center alignment style, the present invention uses input signal time delay assembly input path chronotron on DQB data routing, add the extra time delay of about 0.5ns for this reason, input path chronotron function and outgoing route chronotron similar, just be mainly used in input signal time delay, after using input path chronotron, edge can be made to align and to be modified to center alignment, below this strategy is explained in detail:

Fig. 9 gives the situation of change of the phase place between QKB and DQB, and at FPGA pin place, the two is edge alignment style.As as described in clock tree design part, the Clock management module II ~ Clock management module III in Clock Tree delivered to by QKB clock after the input of global clock pin, and produce the same frequency clock signal clk _ QKB0/1 with its phase place close alignment, this signal delivers to the CLK port of deserializer through FPGA cabling resource, namely the ISERDES_CLK in Fig. 8, DQB enters FPGA inside by common IO pin, namely the DQB_d1 in Fig. 9, the two is basically identical in the cabling time delay of FPGA inside, therefore DQB_d1 and ISERDES_CLK is still edge alignment style, then because the present invention inserts input path chronotron assembly to DQB_d1, its time delay is made to adds additional 0.5ns, just it is 1/4 CLK_QKB clock period, the signal of real arrival deserializer data D port is ISERDES_D, can see, the change moment of ISERDES_D signal is just in time in the centre of ISERDES_CLK rising edge clock and negative edge, alignment style in edge is so just made to be modified to center alignment style, thus meet deserializer input signal and set up retention time requirement, reach the object of correct input data.

Whole high speed input/output interface module need receive the following signal of QDRIV chip:

Port B data bus signal DQB [35:0], arrives the D end of deserializer, then exports the parallel data after reduction of speed by deserializer after input path chronotron time delay 0.5ns by totally 36.

Similarly, whole module need to QDR chip signal output:

QDR chip operation clock CK, CK_, is directly exported by parallel-to-serial converter,

Address bus A [21:0], totally 22, parallel-to-serial converter coordinates with outgoing route chronotron and realizes 0.5ns time delay and export;

Port A data clock DKA [1:0], DKA_ [1:0], is directly exported by parallel-to-serial converter totally by 4,

Port A data bus DQA [35:0], totally 36, parallel-to-serial converter coordinates with outgoing route chronotron and realizes 0.5ns time delay and export;

Port A/B operates enable signal LDA_, LDB_, totally 2, and parallel-to-serial converter coordinates with outgoing route chronotron and realizes 0.5ns time delay and export;

Port A/B reads and writes indicator signal RWA_, RWB_, totally 2, and parallel-to-serial converter coordinates with outgoing route chronotron and realizes 0.5ns time delay and export;

In sum, the structure of whole high speed input/output interface module can (note: all parallel-to-serial converter work clocks in figure all derive from CLK_500M and CLK_125M that Clock Tree provides as shown in Figure 10, all outgoing route chronotrons and input path chronotron work clock then derive from the CLK_250M that Clock Tree provides, because structure is more complicated, Gu Tuzhong does not mark).

Can see, high speed input/output interface module completes following work:

(1) QDR chip high speed data-signal DQB [35:0] (500MHz is received, DDR transmission mode), and low-speed clock territory signal DQB_150M [287:0] (125MHz is converted to after input path chronotron array, deserializer array and transitional slide device array I, SDR transmission mode, data width becomes original 8 times simultaneously), this signal delivers to main control module and user's low speed read and write access module simultaneously, transitional slide device array I accepts the shift control signal from main control module simultaneously, exports pattern with the displacement of determination data.

(2) 8 bit parallel binary data 10101010 are converted into speedy carding process by parallel-to-serial converter array I, thus obtain CK, DKA [1:0] clock signal of QDRIV chip, this clock frequency is 500MHz, utilize parallel-to-serial converter array II that 8 bit parallel binary data 01010101 are converted into speedy carding process equally, thus obtain CK_, DKA_ [1:0] signal of QDRIV chip, this clock frequency is 500MHz, but phase place just in time differs 180 degree with CK, DKA [1:0].

(3) data of writing of user's low speed read and write access module (write data for 8 groups in Figure 10, often group is write data width and is 36), read/write address (4 groups of write addresses in Figure 10 and 4 groups read address), 125MHz, SDR transmission mode read-write control signal (the low-speed port A write control signal in Figure 10, and low-speed port B read control signal) be converted to 500MHz, the DDR transmission mode high speed signal (DQA [35:0] in Figure 10, A [21:0], LDA_ [1:0], RWA_ [1:0], LDB_ [1:0], RWB_ [1:0]) and export QDRIV chip to.

Whole high speed input/output interface module needs 66 parallel-to-serial converter assemblies, 36 deserializer assemblies, 60 outgoing route chronotron assemblies, 36 input path chronotron assemblies, and 2 transitional slide device arrays.

5, user's low speed read and write access module

User's low speed read and write access module, comprises data selector array I ~ data selector array III, and register array I ~ register array IV; Wherein:

Data selector array I, receives the data select signal of main control module, the test writing data or main control module of controller outside is read and write data and export register array I to;

Data selector array II, receives the data select signal of main control module, by the write address array of controller outside, read address array, or the test reading address array of main control module exports register array II to;

Data selector array III, receives the data select signal of main control module, by the write enable signal of controller outside, reads enable signal, or the test write enable signal of main control module, reads enable signal and export register array III to;

Register array I ~ register array III, for the signal that registered data selector switch array I ~ data selector array III exports, and is sent to the reading-writing port of QDRIV chip through high speed input/output interface module;

The function of this module is relatively simple, it is mainly at 125MHz, to complete under the low frequency of operation of SDR pattern with the information interaction of main control module, memory controller other module outside and through selecting and being forwarded to high speed input/output interface module after depositing, and the DQB_150M [143:0] received from high speed input/output interface module, export through controller external data port after depositing process.The structured flowchart of this module as shown in figure 11.

The input signal of this module mainly contains:

A, come self-controller outside write FPDP WRDAT_EXT [287:0];

B, read and write data from the test of main control module TEST_DAT [287:0];

C, carry out the write address array WRADDR_ARRAY_EXT [87:0] (comprising 4 groups of QDRIV write addresses) of self-controller outside, and read address array RDADDR_ARRAY_EXT [87:0] (comprise 4 groups of QDRIV and read address);

D, test write address array WRADDR_ARRAY_EXT [87:0] (comprising 4 groups of QDRIV write addresses) from main control module, and test reading address array RDADDR_ARRAY_EXT [87:0] (comprise 4 groups of QDRIV and read address);

E, carry out the write enable signal WREN_EXT of self-controller outside, read enable RDEN_EXT;

F, test write enable signal TEST_WREN from main control module, read enable TEST_RDEN;

G, data selection end DAT_SEL from main control module;

H, low-speed port B read data DQB_150M [287:0] from high speed input/output interface module.

A and b in above-mentioned user's low speed read and write access module input signal, c and d, e and f is each via data selector array I ~ data selector array III, wherein the data selection end of data selector array I ~ data selector array III is input signal g, the signal of self-controller outside is in the future selected to export when this signal is low level, for then the test signal from main control module being exported during high level, after this output signal of three groups of data selector arrays exports separately after register array is deposited, output signal is respectively 8 groups and writes data, 4 groups of write addresses of cross arrangement and 4 groups read address, low-speed port A write control signal, and low-speed port B read control signal, these signals finally all deliver to high speed input/output interface module.This module also receives low-speed port B read data DQB_150M [287:0] from high speed input/output interface module simultaneously, and after depositing process, exports controller outside port to equally.

Can see, all output signal of whole user's low speed read and write access module all adopts register array to export, and this is equivalent to additionally insert a level production line, thus improves static timing analysis performance, and improves the maximum operation frequency of system.

6, main control module design

Main control module is the central control portion of whole controller, mainly realizes QDRIV chip electrification reset sequential and basic readwrite tests.The switching of specific implementation QDRIV chip reset pattern, readwrite tests pattern and normal mode of operation; Produce test signal, and complete through user's low speed read and write access module and high speed input/output interface module test operation is write to QDRIV chip; Under readwrite tests pattern, verify that whether QDRIV chip write data are consistent with back read data, normal mode of operation is switched to when completely the same, receive controller exterior read-write port signal by user's low speed read and write access module, complete QDRIV chip high speed read-write operation.Its inner structure as shown in figure 12.

Main control module comprises reset timing generator, pseudorandom number generator, readwrite tests module, transitional slide data recorder, major state machine; Wherein:

Reset timing generator, the enable and reset timing produced needed for QDRIV chip by major state machine;

Pseudorandom number generator, for generation of pseudo-random data, exports test through readwrite tests module and reads and writes data;

Transitional slide data recorder, the shift index value of the transitional slide device of record high speed input/output interface module, exports the data selection port SEL of data selector in shift control signal to the transitional slide device array I of high speed input/output interface module;

Readwrite tests module, receive pseudo-random data that pseudorandom number generator exports and export test and read and write data, produce and test write address, test write enable signal accordingly, and finally complete through user's low speed read and write access module and high speed input/output interface module test operation is write to QDRIV chip; The data utilizing pseudorandom number generator to export carry out the comparison writing data and back read data, look out for mistakes, regulate transitional slide data recorder with the data selection port SEL of data selector in the transitional slide device array I upgrading high speed input/output interface module;

Major state machine, control reset timing generator, pseudorandom number generator, readwrite tests module, transitional slide data recorder works in order, QDRIV chip reset pattern is realized by state machine, the switching of readwrite tests pattern and normal mode of operation, under readwrite tests pattern, the reading-writing port of QDRIV chip is taken by main control module, QDRIV chip is write and retaking of a year or grade by pseudorandom number generator, then progressively regulate transitional slide data recorder with the data selection port SEL of data selector in the transitional slide device array I upgrading high speed input/output interface module, finally prove that readwrite tests passes through when writing data and being identical with back read data, normal mode of operation can be proceeded to, and the reading-writing port control of QDRIV chip is gone to controller exterior read-write port.

The main control module course of work is described in detail in detail below:

(1) after system electrification, DAT_SEL put by major state machine is high level, enable reset timing generator, and produce the reset timing needed for chip RST_, CFG_ pin, resetted rear forbidding reset timing generator, enters and write test mode;

(2) transitional slide data recorder is reset, putting pseudorandom number generator is original state, pseudorandom number generator produces one group of 288 pseudo-random data every a clock period, exported through TEST_DAT [287:0] by readwrite tests module, produce corresponding test write address TEST_WRADDR_ARRAY [87:0], test and write enable TEST_WREN signal, and finally complete through user's low speed read and write access module and high speed input/output interface module test operation is write to QDRIV chip, after this proceed to and read test operation;

(3) test operation is being read, again putting pseudorandom number generator is original state, and exported data after register array is deposited, contrast in readwrite tests module with low-speed port B read data DQB_150M [287:0], look out for mistakes, if had, prove that transitional slide device data selection SEL [2:0] of high speed input/output interface module needs to upgrade, do to add 1 operation to revise shift control signal to the value of transitional slide data recorder, and then get back to and write test mode.Under normal circumstances, at most through continuous 8 readwrite tests, a kind of correct shift control signal can be found out, otherwise should consider to check the hardware problem such as chip sole mass and welding.If contrast inerrancy, jumps directly to normal operating conditions.

(4) in normal operating conditions, putting DAT_SEL is low level, release main control module taking QDRIV reading-writing port, after this controller can receive exterior read-write port signal by user's low speed read and write access module, completes the high-speed read-write operation under QDRIV chip 500MHz clock.

In sum, the present invention is by above-mentioned layout strategy, efficiently solve the hypervelocity reliable read write problem under 500MHz Double Data Rate, other module of FPGA inside only need under single 125MHz rising edge clock drives the outside port of access controller, then completed by controller and the high-speed data of QDRIV chip is exchanged, and ensure that sufficient sequential allowance and the accuracy of each clock sampling phase place from design, developer is made no longer to need the optimum sampling moment of each clock of manual test, transfer rate is also significantly improved than existing QDR Controller gain variations.

Above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.

Claims

1. be applicable to a QDRIV hypervelocity memory controller of FPGA, it is characterized in that: be made up of Clock Tree, Global reset module, high speed input/output interface module, user's low speed read and write access module and main control module, wherein:

Clock Tree, the data of the reference frequency clock and the output of QDRIV chip that receive outside input are with road clock, and complete clock regeneration and process of frequency multiplication, regeneration time clock and input clock have the phase relation known, the clock signal that Clock Tree exports is for Global reset module, high speed input/output interface module, user's low speed read and write access module and main control module;

Global reset module, the asynchronous reset signal of the outside input of reception, exports after synchronously process, as the global reset signal of the necessary register of reset main control module and high speed input/output interface module inside;

High speed input/output interface module, receives QDRIV chip high speed signal and is converted to speed parallel signals, and delivering to main control module and user's low speed read and write access module; Export the work clock of QDRIV chip; Receive user's low speed read and write access module speed parallel signals and be converted to high speed signal and export QDRIV chip to;

User's low speed read and write access module, the test data produce main control module or controller outside port data deliver to high speed input/output interface module; The QDRIV retaking of a year or grade low-speed parallel data exported by high speed input/output interface module is delivered to after depositing the outside port of main control module and controller;

2. the QDRIV hypervelocity memory controller being applicable to FPGA according to claim 1, it is characterized in that: described Global reset module, comprise the first register of mutual cascade, the second register and the 3rd register, asynchronous reset signal for being inputted outside is converted to the synchronous reset signal under FPGA local clock territory, the register of reset main control module and the inner necessity of high speed input/output interface module and programmable resource.

3. the QDRIV hypervelocity memory controller being applicable to FPGA according to claim 1, it is characterized in that: described high speed input/output interface module, comprise input path chronotron array, deserializer array, transitional slide device array I, transitional slide device array II, parallel-to-serial converter array I ~ parallel-to-serial converter array V, outgoing route chronotron array I ~ outgoing route chronotron array III; Wherein:

4. the QDRIV hypervelocity memory controller being applicable to FPGA according to claim 3, it is characterized in that: in described transitional slide device array I and transitional slide device array II, transitional slide device input signal comprises 8 Bit data DIN, operating clock signals CLK, and 3 Bit datas select port SEL signal; DIN exports and obtains DIN_d1 after D register is deposited, the relative DIN of DIN_d1 has the time delay of a CLK clock period, then by signal DIN and DIN_d1, through position, splicing obtains 16 new bit width variablees, then therefrom sequentially 8 Bit datas are chosen respectively by 8 rearrangement device, the output of these 8 rearrangement device is delivered to 8 simultaneously and is selected 1 data selector, is determined the data of which group rearrangement device to export by the value of data selector data selection port SEL signal; In transitional slide device array I, the data selection port SEL signal of data selector is produced by main control module and variable, reads for realizing the QDR alignment of data obtained; In transitional slide device array II, the data selection port SEL signal of data selector is then fixed as 3 bits 101, low literary sketch data to be misplaced 5 bits than write address and control signal, reach high speed clock domain after parallel-serial conversion under, exports the object comparing 5 clock period of input delay.

5. the QDRIV hypervelocity memory controller being applicable to FPGA according to claim 1, it is characterized in that: described user's low speed read and write access module, comprise data selector array I ~ data selector array III, and register array I ~ register array IV; Wherein:

6. the QDRIV hypervelocity memory controller being applicable to FPGA according to claim 5, it is characterized in that: when main control module is under readwrite tests pattern, the test data that main control module produces is utilized data selector array I ~ data selector array III, and register array I ~ register array III delivers to high speed input/output interface module and the final reading-writing port arriving QDRIV chip; When main control module in the normal mode of operation time, then controller exterior read-write port signal is utilized data selector array I ~ data selector array III, register array I ~ register array III delivers to high speed input/output interface module and the final reading-writing port arriving QDRIV chip, also the QDRIV chip read-back data exported by high speed input/output interface module is delivered to main control module and controller outside port after register array IV is deposited simultaneously.

7. the QDRIV hypervelocity memory controller being applicable to FPGA according to claim 4, is characterized in that: described main control module comprises reset timing generator, pseudorandom number generator, readwrite tests module, transitional slide data recorder, major state machine; Wherein:

Transitional slide data recorder, the shift index value of the transitional slide device of record high speed input/output interface module, exports the data selection port of data selector in shift control signal to the transitional slide device array I of high speed input/output interface module;

Readwrite tests module, receive pseudo-random data that pseudorandom number generator exports and export test and read and write data, produce and test write address, test write enable signal accordingly, and finally complete through user's low speed read and write access module and high speed input/output interface module test operation is write to QDRIV chip; The data utilizing pseudorandom number generator to export carry out the comparison writing data and back read data, look out for mistakes, regulate transitional slide data recorder with the data selection port of data selector in the transitional slide device array I upgrading high speed input/output interface module;

8. the QDRIV hypervelocity memory controller being applicable to FPGA according to claim 3, is characterized in that: described Clock Tree, comprises Clock management module I, Clock management module II, Clock management module III, and 8 global routing's resources, wherein, the reference frequency clock of outside input is through global clock resource I, 3 road clocks are exported after Clock management module I, described 3 road clocks export separately after the process of a global clock resource: the output of global clock resource IV is used for the low-speed clock logic of driving governor, the work clock of main control module and user's low speed read and write access module is provided, the output of global clock resource V is used for input path chronotron in high speed input/output interface module, the operating reference clock of outgoing route chronotron, the output of global clock resource VI is used for high speed input/output interface module, the high-frequency clock logic of driving governor, QDRIV chip export one group of data output clock signal through global clock resource II, Clock management module II, global routing's resource VII export after for driving the deserializer array of high speed input/output interface module, another of QDRIV chip output organizes data output clock signal after global clock resource III, Clock management module III, global routing's resource VIII export for driving the deserializer array of high speed input/output interface module.