CN106650128B - A kind of method of graphic software platform timing topology and timing dependence - Google Patents
A kind of method of graphic software platform timing topology and timing dependence Download PDFInfo
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- CN106650128B CN106650128B CN201611234289.9A CN201611234289A CN106650128B CN 106650128 B CN106650128 B CN 106650128B CN 201611234289 A CN201611234289 A CN 201611234289A CN 106650128 B CN106650128 B CN 106650128B
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
A kind of method of graphic software platform timing topology and timing dependence, comprising the following steps: reading record has timing topology figure information needed file, opens the timing topology figure by abstraction module encapsulation.Timing dependence analysis is carried out to module, by analysis as the result is shown in graphical window.The method of graphic software platform timing topology and timing dependence of the invention, it can clearly show the structure of complicated clock system, effectively analyze the timing dependence between synchronization unit, auxiliary clock tree synthesis tool is to improve comprehensive quality, manufacture and design the period so as to shorten chip, improves design efficiency.
Description
Technical field
The present invention relates to Electronic Design Automation Technology fields, more particularly to a kind of graphic software platform timing topology
And the method for timing dependence.
Background technique
The back-end physical design of super large-scale integration is increasingly dependent on the auxiliary of electronic design automation tool
It helps.Clock signal controls the work of all synchronization units in circuit；Ultrahigh speed, low-power consumption, high performance integrated circuit development
Higher design requirement is proposed to clock system, has become the key that chip successfully throws piece production.A usual clock
Structure includes clock defining point, combinatorial logic unit (such as with door/or gate cell), gate controlled clock unit (such as ICG unit),
Synchronization unit (such as flip-flop element), divider unit etc..
Clock system under the conditions of current deep-submicron can be very huge: clock number is more and more, and each clock wraps
Respective gate control logic and ten hundreds of synchronization units are included, the sequential relationship between synchronization unit is also sufficiently complex.It faces
Such numerous and jumbled clock system, how simple and clear read clock structure, how to protrude expression clock feature, and such as
What combines clock information and timing information, shows the sequential correlation relationship between synchronization unit, convenient for front end engineer and
Rear end engineer's communication exchange, and instruct the effective synthesis of clock tree synthesis tool progress to become industry focus of attention and ask
Topic.
A kind of method of graphic software platform timing topology has been disclosed in patent of invention CN103425804A.This method is one
The overall structure of read clock system in a graphical window filters out secondary information by the processing of modularization and symbolism, right
Key structural feature is grabbed, and in conjunction with timing information and logical level, clearly shows clock system internal structure.
However, have analysis and display that some eda tools carry out clock system currently on the market, but all there is one
A little defects and upper inconvenience is used, such as: it can not read clock structure and temporal characteristics simultaneously；For grandfather clock system,
The details of display is excessive and loses readability；It is poor with the interactivity of user, can not to existing clock system carry out validity,
Correctness checking.
Summary of the invention
In order to solve the shortcomings of the prior art, the purpose of the present invention is to provide a kind of graphic software platform timing topologies
And the method for timing dependence can filter out secondary information by modularization and the processing of symbolism, carry out to characteristic information
Crawl clearly shows timing topology, and can be by the Time-Series analysis of synchronization unit as a result, highlighted aobvious using connection mode
Show the timing dependence connection between module.
To achieve the above object, graphic software platform timing topology provided by the invention and the method for timing dependence, including
Following steps:
1) reading record has timing topology figure information needed file, opens the timing topology by abstraction module encapsulation
Figure.
2) timing dependence analysis is carried out to module, by analysis as the result is shown in graphical window.
Further, message file described in the step 1), including, design the unit library file of circuit, writing circuit
The net meter file of connection relationship defines the file of clock and delay constraint.
Further, timing topology figure described in step 1) is to synchronize list with identical connection relationship in clock circuit
Member, gate controlled clock unit, the combinatorial logic unit of same type, divider unit have all carried out abstract encapsulation, with module side
Formula is shown.
Further, timing topology figure described in step 1), different type module are shown by different particular colors.
Further, timing dependence analysis is carried out to module described in step 2, further included steps of
Finding synchronization unit in synchronization unit and all and module in the module of user's selection has sequential relationship
Other synchronization units, said module, be labeled with the connection mode of Flyline；
Module where module where distinguishing data transmission unit with two different colors and data receipt unit, and highlight
It is shown in graphical window；
Clock Tree is adjusted according to the ratio that the number of timing connection and connection number account for unit sum in module；
It obtains timing dependence and analyzes result.
Further, it will be analyzed as the result is shown in graphical window described in step 2, and be that will analyze result with line shape
Formula is shown in graphical window, is highlighted the unit for having sequential relationship with the synchronization unit in module or module.
The present invention provides graphic software platform timing topology and timing dependence in Electronic Design Automation Technology field
Method, it is by the Time-Series analysis result of the processing and synchronization unit of modularization and symbolism and highlighted using connection mode
Timing dependence connection between display module, can clearly show the structure of complicated clock system, effectively analysis synchronizes
Timing dependence between unit, auxiliary clock tree synthesis tool manufacture and design week to improve comprehensive quality, so as to shorten chip
Phase improves design efficiency.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, and with it is of the invention
Embodiment together, is used to explain the present invention, and is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the method flow diagram of graphic software platform timing topology according to the present invention and timing dependence；
Fig. 2 is graphic software platform timing topology according to the present invention and timing dependency diagram；
Fig. 3 is the abstraction module encapsulation schematic diagram of synchronization unit according to the present invention；
Fig. 4 is the abstraction module encapsulation schematic diagram of gate controlled clock unit according to the present invention；
Fig. 5 is the abstraction module encapsulation schematic diagram of combinatorial logic unit according to the present invention；
Fig. 6 is the abstraction module encapsulation schematic diagram of divider unit according to the present invention.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein
Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
Fig. 1 is the method flow diagram of graphic software platform timing topology according to the present invention and timing dependence, below will ginseng
Fig. 1 is examined, the method for graphic software platform timing topology and timing dependence of the invention is described in detail.
Firstly, reading the file that record has timing topology figure information needed in step 101.Wherein, including design circuit
Unit library file (such as timing lib format), the net meter file (such as verilog format) of writing circuit connection relationship are fixed
The file (such as sdc format) of adopted clock and delay constraint.
The timing topology figure by abstraction module encapsulation is opened according to the file that step 101 is read in step 102.Figure
2 be graphic software platform timing topology according to the present invention and timing dependency diagram, as shown in Fig. 2, by abstraction module
Timing topology after encapsulation, the synchronization in clock network on same gauze (or same group of gauze of same module output)
Unit, gate controlled clock unit, same type combinatorial logic unit, divider unit are encapsulated into each generic module such as F/G/C/N respectively
In the middle.Wherein, for the ease of distinguishing, above-mentioned different type module can be shown by different colours.
Fig. 3 is the abstraction module encapsulation schematic diagram of synchronization unit according to the present invention, and Fig. 4 is gate according to the present invention
The abstraction module encapsulation schematic diagram of clock unit, Fig. 5 are that the abstraction module of combinatorial logic unit according to the present invention encapsulates
Schematic diagram, Fig. 6 are the abstraction module encapsulation schematic diagram of divider unit according to the present invention, as seen in figures 3-6, Fig. 3 to Fig. 6
Show synchronization unit F module, gate controlled clock unit G module, combinatorial logic unit C module and divider unit N-module
Packaging method structure, wherein connection relationship having the same can be considered for according to a plurality of output gauze of same module, it is same
Unit on same group of gauze of module output can all carry out abstract encapsulation.As shown in figure 3, gate controlled clock unit G module packet
Containing there are three ICG unit, 32 synchronization units are connected to after each ICG unit, therefore 96 synchronization units connected can quilt
It is encapsulated into a synchronization unit F module, i.e. FF_96.
After abstraction module encapsulation, the information content in display window has obtained reducing significantly timing topology, but still
It clearly can effectively show the component units and main body connection relationship of the clock.If user wants to further appreciate that in module
Particular content, inside modules can be entered with double click, graphical window can unit connection inside display module.
In step 103, receive the module that user selects in such a way that mouse is clicked, including synchronization unit module,
Gate controlled clock unit module or divider unit module, and start to carry out timing phase after user is selected by right-click menu
The analysis of closing property.When in step 104, finding the synchronization unit in the module, and finding that synchronization unit has in all and module
The other synchronization units and said module of order relation, and be labeled with the connection mode of Flyline, obtain timing dependence point
Analyse result.In order to distinguish the direction (data are sent or data receiver) of timing path, data are distinguished with two different colors
Module where module where transmission unit and data receipt unit, and be highlighted in graphical window.User can basis
The number and connection number of timing connection account for the strategy of the ratio adjustment clock tree synthesis of unit sum in module.For example,
100 synchronization units are shared in " ratio:1/100 " representation module, wherein having 1 synchronization unit and selected module sometimes
The connection of sequence correlation.If the case where for connecting between module there is only a small number of timing, being grouped again for clock can be carried out,
Or setting excluded time constraints etc., avoid clock tree synthesis from being inserted into the buffer unit of excessive redundancy.
After step 104, timing dependence analysis, analysis result is shown in graphical window in the form of line, and
And it is highlighted the unit for having sequential relationship with the synchronization unit in the module or module.
In order to distinguish the direction (data are sent or data receiver) of timing path, data are distinguished with two different colors
Module where module where transmission unit and data receipt unit.
The function of removing and be highlighted is additionally provided, user is for inessential or unconcerned module timing dependence
Connection, can choose cancellation and is highlighted.
For the ease of being searched and located in complicated clock system structure, clock display window is also supported to module, line
Net, unit, pin etc. are according to keyword query function.Erasing that the timing dependence line being highlighted can be convenient carry out or
It hides, the main body component part that will not influence timing topology is shown.
The method of graphic software platform timing topology and timing dependence of the invention, passes through modularization and the processing of symbolism
And synchronization unit Time-Series analysis result and using connection mode be highlighted the timing dependence between module contact, can
Clearly to show the structure of complicated clock system, the timing dependence between synchronization unit, auxiliary clock tree are effectively analyzed
Synthesis tool manufactures and designs the period to improve comprehensive quality, so as to shorten chip, improves design efficiency.
Those of ordinary skill in the art will appreciate that: the foregoing is only a preferred embodiment of the present invention, and does not have to
In the limitation present invention, although the present invention is described in detail referring to the foregoing embodiments, for those skilled in the art
For, still can to foregoing embodiments record technical solution modify, or to part of technical characteristic into
Row equivalent replacement.All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should all include
Within protection scope of the present invention.
Claims (5)
1. a kind of method of graphic software platform timing topology and timing dependence, comprising the following steps:
1) reading record has timing topology figure information needed file, opens the timing topology figure by abstraction module encapsulation；
2) timing dependence analysis is carried out to module, by analysis as the result is shown in graphical window；
Wherein, described that timing dependence analysis is carried out to module, it further includes steps of
Find the synchronization unit and its all with synchronization unit in the module with sequential relationship in the module of user's selection
Its synchronization unit, said module are labeled with the connection mode of Flyline；
Module where module where distinguishing data transmission unit with two different colors and data receipt unit, and be highlighted
In graphical window；
Clock Tree is adjusted according to the ratio that the number of timing connection and connection number account for unit sum in module；
It obtains timing dependence and analyzes result.
2. the method for graphic software platform timing topology according to claim 1 and timing dependence, which is characterized in that described
Message file described in step 1), including, the unit library file of circuit is designed, the net meter file of writing circuit connection relationship is fixed
The file of adopted clock and delay constraint.
3. the method for graphic software platform timing topology according to claim 1 and timing dependence, which is characterized in that step
Rapid 1) the described timing topology figure is to synchronization unit, the gate controlled clock unit, phase in clock circuit with identical connection relationship
The combinatorial logic unit of same type, divider unit have all carried out abstract encapsulation, show in a modular way.
4. the method for graphic software platform timing topology according to claim 1 and timing dependence, which is characterized in that step
1) the timing topology figure, different type module are shown by different particular colors.
5. the method for graphic software platform timing topology according to claim 1 and timing dependence, which is characterized in that step
2) described to analyze as the result is shown in graphical window, it is that will analyze result to show in graphical window in the form of line, highlights
Display has the unit or module of sequential relationship with the synchronization unit in module.
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111881645B (en) * | 2020-07-03 | 2021-05-04 | 广芯微电子（广州）股份有限公司 | Clock tree anti-interference method and device based on noise timing sequence |
| CN112100970B (en) * | 2020-11-17 | 2021-05-11 | 南京芯驰半导体科技有限公司 | Method and system for graphically displaying clock structure |
| CN114896941B (en) * | 2022-07-15 | 2022-10-25 | 飞腾信息技术有限公司 | Layout optimization method, optimization device and related equipment of clock tree |
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| CN103425804A (en) * | 2012-05-15 | 2013-12-04 | 北京华大九天软件有限公司 | Method for graphically displaying structure of clock system |
| CN104468072A (en) * | 2014-12-04 | 2015-03-25 | 中国航空工业集团公司第六三一研究所 | IMA platform clock synchronization method |
| CN104715095A (en) * | 2013-12-17 | 2015-06-17 | 北京华大九天软件有限公司 | Graphical clock quality detecting and analyzing method |
| WO2015197720A1 (en) * | 2014-06-25 | 2015-12-30 | Koninklijke Philips N.V. | Mri system with wireless synchronization of a wireless rf coil portion using a double sideband suppressed carrier signal |
| CN105550400A (en) * | 2015-12-04 | 2016-05-04 | 西安泛华科技开发有限公司 | Modeling method of system time sequence |
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| CN103425804A (en) * | 2012-05-15 | 2013-12-04 | 北京华大九天软件有限公司 | Method for graphically displaying structure of clock system |
| CN104715095A (en) * | 2013-12-17 | 2015-06-17 | 北京华大九天软件有限公司 | Graphical clock quality detecting and analyzing method |
| WO2015197720A1 (en) * | 2014-06-25 | 2015-12-30 | Koninklijke Philips N.V. | Mri system with wireless synchronization of a wireless rf coil portion using a double sideband suppressed carrier signal |
| CN104468072A (en) * | 2014-12-04 | 2015-03-25 | 中国航空工业集团公司第六三一研究所 | IMA platform clock synchronization method |
| CN105550400A (en) * | 2015-12-04 | 2016-05-04 | 西安泛华科技开发有限公司 | Modeling method of system time sequence |
Non-Patent Citations (1)
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Address after: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee after: Beijing Huada Jiutian Technology Co.,Ltd. Address before: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee before: HUADA EMPYREAN SOFTWARE Co.,Ltd. |