CN105550459B - A kind of ASIC design clock network extraction system - Google Patents
A kind of ASIC design clock network extraction system Download PDFInfo
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- CN105550459B CN105550459B CN201511005377.7A CN201511005377A CN105550459B CN 105550459 B CN105550459 B CN 105550459B CN 201511005377 A CN201511005377 A CN 201511005377A CN 105550459 B CN105550459 B CN 105550459B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The present invention discloses a kind of ASIC design clock network extraction system, is related to chip design field, which is based on eda tool, completes the analysis of large-scale complex clock network in ASIC design by the parser that TCL script is realized and extracts task；The system consists of three parts: clock module analytical unit, clock domain analytical unit, original clock network output unit.With the application of the invention, completing the analysis and extraction of ASIC design clock network increasingly automatedly, tradition can be greatly lowered by manual analysis method bring error rate, while can also greatly improve working efficiency.
Description
Technical field
The present invention relates to chip design field, specifically a kind of ASIC design clock network extraction system.
Background technique
Usually at the initial stage of the rear end ASIC design, need to carry out front end netlist multi-faceted analysis.Particularly, at that time
Accurately understanding is to guarantee the premise of chip rear end design performance quality to clock network structure in detail.In the rear end ASIC design cycle
In, either system design for Measurability or automatic placement and routing require to carry out the clock network framework of original design careful
Analysis and building.Especially numerous, the timing topology complicated situation in face of functional mode in super large-scale integration now,
How accurately and efficiently to be completed from ASIC Front-end Design netlist the analysis of clock network with extract work be known as one it is important
Link.
The analysis of conventional ASIC design clock network is by being accomplished manually with extraction work.With chip technology size
Reduction, chip design scale constantly expands.The function that chip is realized becomes increasingly complex, under different working modes clock network
The scale of network constantly increases with structural complexity.Therefore, the accuracy of manual analysis large-scale complex ASIC design clock network
All there is great limitation with timeliness.
Summary of the invention
The shortcoming that the present invention develops for current needs and the prior art, provides a kind of pair of ASIC design front end net
The system that clock network in table is analyzed and extracted.
A kind of ASIC design clock network extraction system of the present invention solves the technical solution that above-mentioned technical problem uses
As follows: the ASIC design clock network extraction system is based on eda tool, is completed by the parser that TCL script is realized
The analysis and extraction task of large-scale complex clock network in ASIC design；The system consists of three parts: clock module analysis
Unit, clock domain analytical unit, original clock network output unit.
Preferably, the input file of Xiang Suoshu ASIC design clock network extraction system input, including the front end ASIC netlist,
Schema constraint file；From the ASIC design clock network extraction system export output file, including original clock file and
Reconstruct two class of template file.
Preferably, the clock module analytical unit generates ASIC design in difference according to the schema constraint file of input
Various parameters under operating mode for clock network analysis, and pass to clock domain analytical unit；The clock domain analysis list
Member, according to clock module analytical unit generate parameter, analysis ASIC design respectively under different working modes each clock domain and
Whole clock network various aspects indication information；The original clock network output unit, what composite clock domain analysis unit extracted
Clock network indication information generates various output documents.
Preferably, the extraction that single clock domain information is completed by the clock domain analytical unit successively includes: clock leaf
Node extracts, gated clock extracts, clock generation logic extracts, clock source extracts this 4 steps；Single clock domain is from its clock
Source forms tree structure, clock port of the clock domain analytical unit from each timing unit leaf node to each timing unit
It sets out, carries out reverse phase search along clock path to clock source direction.
Preferably, the timing unit leaf node information of clock domain is identified first, completes the work that clock leaf node extracts；So
Afterwards, respectively from the clock port of each leaf node to the root of Clock Tree, when there is gate controlled clock unit, according to different cell type point
It indescribably takes its pathname and quantity and sets up the connection of clock network front stage；Then, along clock path inverse analysis front end
Network mark, if occurring clock generation logic on clock path, analysis and extraction clock division unit, clock selecting unit clock letter
Breath；Finally, search reaches the root of Clock Tree, completes the identification of clock source.
A kind of ASIC design clock network extraction system of the present invention has the beneficial effect that compared with prior art
The present invention can provide a kind of implementation of precise and high efficiency for the analysis and extraction of ASIC design clock network, the ASIC design
Clock network extraction system can be conveniently used in the initial stage of ASIC design rear end process；It is high using system of the invention
Degree, which automatically completes inter-related task, can be greatly lowered tradition by manual analysis method bring error rate, while also can
Greatly improve working efficiency.
Detailed description of the invention
Attached drawing 1 is the structural schematic diagram of the ASIC design clock network extraction system；
Attached drawing 2 is the flow diagram of the clock domain analytical unit；
Attached drawing 3 is a clock network constructive embodiment schematic diagram.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, to a kind of ASIC design clock network extraction system further description of the present invention.
The present invention addresses the above problem proposes a kind of ASIC design clock network extraction system, is a set of couple of ASIC
Design front end netlist carries out clock network analysis and grinds system certainly with what is extracted, based on the eda tool of industry mainstream, by a set of complete
The parser that whole TCL script is realized, can efficiently complete in ASIC design the analysis of large-scale complex clock network and
Extraction task.
Embodiment:
Attached drawing 1 is the structural schematic diagram of ASIC design clock network extraction system described in the present embodiment；As shown in Fig. 1,
Central box region is system of the invention in figure, is input file on the left of system, right side is output file.This is as seen from the figure
System consists of three parts: clock module analytical unit, clock domain analytical unit, original clock network output unit.Left side input
File includes the front end ASIC netlist, schema constraint file；Right side output file includes original clock file and reconstruct template file
Two classes.
ASIC design clock network extraction system described in the present embodiment, the clock module analytical unit, according to input
Schema constraint file generates various parameters of the ASIC design under different working modes for clock network analysis, and when passing to
Clock domain analysis unit；
The clock domain analytical unit, according to the parameter that clock module analytical unit generates, analysis ASIC design exists respectively
Each clock domain and whole clock network various aspects indication information under different working modes, including leaf node number, leaf node gate
Clock number, backbone gate controlled clock unit pathname and type, memory bank and IP kernel unit pathname, clock generation module
Pathname etc.；
The original clock network output unit, the clock network indication information that composite clock domain analysis unit extracts produce
Raw various output documents.
ASIC design clock network extraction system described in the present embodiment, the clock domain analytical unit include in whole system
Most crucial clock domain parser.Attached drawing 2 is the flow diagram of the clock domain analytical unit；As shown in Fig. 2, pass through
Analysis ASIC design front end netlist clock domain parser mainly completes the extraction of single clock domain information through 4 steps.This 4
Step is successively are as follows: clock leaf node extracts, gated clock extracts, clock generation logic extracts, clock source extracts.Single clock domain
Tree structure is formed from its clock source to each timing unit.The work of clock domain analysis is from each timing unit leaf node
Clock port sets out, to clock source direction along the search expansion of clock path reverse phase.
The clock domain analytical unit identifies the timing unit leaf node information of the clock domain first, this includes leaf node
Quantity statistics, leaf node classifying type statistics, leaf node clock port identification etc. information, so i.e. completion clock leaf node
The work of extraction.Then, respectively from the clock port of each leaf node to the root of Clock Tree, i.e. clock source searches for clock path,
In it is possible that gate controlled clock unit.Gate controlled clock unit may be divided into multi-level form, including leaf node gated clock list again
Member, clock backbone network gate controlled clock unit etc..Its pathname and quantity are extracted respectively according to different cell types and are set up
The connection of clock network front stage, completes second step in this way.Then, along clock path inverse analysis front end network mark, on clock road
It is possible that clock generation logic on diameter, such as clock division unit, clock selecting unit, the analysis of these clock informations and
It extracts and constitutes third step.Finally, search reaches the root of Clock Tree, completes the identification of clock source, terminates clock domain analysis unit
Step 4 it is rapid.
ASIC design clock network extraction system described in the present embodiment is selected by the mode of schema constraint file configuration first
It selects, generates various parameters of the ASIC design under different working modes for clock network analysis.The clock domain analysis list of system
Member receives the parameter, and is analyzed for the clock network structure under each functional mode ASIC Front-end Design netlist.Entirely
Analytic process is divided by clock domain.The execution of clock domain analytical unit terminates, and system completion exists to entire ASIC Front-end Design netlist
The extraction of each clock domain and entire clock network structure details under various functional modes.Original clock network in system
Output unit is integrated above-mentioned clock network information and is showed in the form of various reports.It had both included each of textual form presentation
Each clock Domain Details under functional mode also include the clock network structure that block diagram format shows.In addition to above-mentioned clock file
Output, system can also generate clock network reconstruct template, so as to rear end design cycle subsequent processing.
Attached drawing 3 is a clock network constructive embodiment schematic diagram, as shown in Fig. 3, the clock network of the ASIC design
There are 3 clock sources, respectively clock 1, clock 2, clock 3.Clock gating device is distributed on clock path, clock network
Leaf node has two kinds of timing devices of register and memory.The present embodiment is anti-from the clock port of each leaf node timing device
Clock network is extracted to search clock path.On the other hand, under the control of mode select signal, which can be with shape
It is distributed at two kinds of clock, respectively corresponds two kinds of functional modes.The mode of the ASIC design clock network extraction system
Unbound document is capable of providing the mode selecting information of ASIC design.When the mode select signal in embodiment controls 1 He of alternative
When 2 device of alternative selects the port A, 2 two clock domains of clock 1 and clock are presented in the clock network of the design；Work as model selection
When signal controls alternative 1 and 2 device of the alternative selection port B, 3 one clocks of clock are only presented in the clock network of the design
Domain.It can be seen that the clock network of ASIC design may show as different clock domain structures under different functional modes；Institute
Can first ASIC design be analyzed according to the information of schema constraint file by stating clock module analytical unit, generate different function
Parameter under energy mode is supplied to clock domain analytical unit.Then, clock domain analytical unit can be under corresponding functional mode
Each clock domain structure is analyzed, clock network information is extracted.
Above-mentioned specific embodiment is only specific case of the invention, and scope of patent protection of the invention includes but is not limited to
Above-mentioned specific embodiment, any person of an ordinary skill in the technical field that meet claims of the present invention and any
The appropriate change or replacement done to it, all shall fall within the protection scope of the present invention.
Claims (4)
1. a kind of ASIC design clock network extraction system, which is characterized in that be based on eda tool, point realized by TCL script
Algorithm is analysed to complete the analysis of large-scale complex clock network in ASIC design and extract task；The system consists of three parts: when
Clock mode analyzing unit, clock domain analytical unit, original clock network output unit；
The clock module analytical unit generates ASIC design according to the schema constraint file of input and uses under different working modes
In the parameter of clock network analysis, and pass to clock domain analytical unit；
The clock domain analytical unit analyzes ASIC design respectively in difference according to the parameter that clock module analytical unit generates
Each clock domain and whole clock network various aspects indication information under operating mode, including leaf node number, leaf node gated clock
Number, backbone gate controlled clock unit pathname and type, memory bank and IP kernel unit pathname, clock generation module path
Title；
The original clock network output unit, the clock network indication information that composite clock domain analysis unit extracts generate defeated
Document out.
2. a kind of ASIC design clock network extraction system according to claim 1, which is characterized in that Xiang Suoshu ASIC design
The input file of clock network extraction system input, including the front end ASIC netlist, schema constraint file；When from the ASIC design
The output file of clock network extraction system output, including original clock file and reconstruct two class of template file.
3. a kind of ASIC design clock network extraction system according to claim 2, which is characterized in that pass through the clock domain
Analytical unit completes the extraction of single clock domain information, successively includes: that clock leaf node extracts, gated clock extracts, clock produces
Raw extracted, clock source extract this 4 steps；Single clock domain forms tree-like knot from its clock source to each timing unit
Structure, the clock domain analytical unit is from the clock port of each timing unit leaf node, to clock source direction along clock road
Diameter carries out reverse phase search.
4. a kind of ASIC design clock network extraction system according to claim 3, which is characterized in that identification clock domain first
Timing unit leaf node information, complete clock leaf node extract work；Then, respectively from the clock port of each leaf node to
The root of Clock Tree when there is gate controlled clock unit, extracts its pathname and quantity according to different cell types respectively and establishes
Play the connection of clock network front stage；Then, along clock path inverse analysis front end network mark, if occurring clock production on clock path
Raw logic, analysis and extraction clock division unit, clock selecting unit clock information；Finally, search reaches the root of Clock Tree,
Complete the identification of clock source.
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| CN115842615B (en) * | 2023-02-24 | 2023-05-09 | 湖南泛联新安信息科技有限公司 | Clock network extraction method based on RTL netlist |
| CN116341481B (en) * | 2023-05-26 | 2023-08-22 | 南京芯驰半导体科技有限公司 | Clock file confirmation method and device, electronic equipment and storage medium |
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| CN102169515A (en) * | 2010-02-26 | 2011-08-31 | 国际商业机器公司 | Estimation method and system of clock tree delay time in specified integrated circuit |
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| US6550045B1 (en) * | 2001-11-20 | 2003-04-15 | Lsi Logic Corporation | Changing clock delays in an integrated circuit for skew optimization |
| CN101351886A (en) * | 2005-12-29 | 2009-01-21 | 莫塞德技术股份有限公司 | ASIC design using clock and power grid standard cell |
| CN102169515A (en) * | 2010-02-26 | 2011-08-31 | 国际商业机器公司 | Estimation method and system of clock tree delay time in specified integrated circuit |
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