CN112924850A - Parallel test switching method applied to SOC chip of automatic tester - Google Patents
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- 238000012360 testing method Methods 0.000 title claims abstract description 140
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2825—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere in household appliances or professional audio/video equipment
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/004—Diagnosis, testing or measuring for television systems or their details for digital television systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
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Abstract
The invention relates to the technical field of semiconductor testing, in particular to a parallel testing switching method applied to an SOC chip of an automatic tester. The specific process is as follows: s1: the data interface and MCU end on the test carrier board are connected with a group of digital test channels A, the Ethernet interface end on the test carrier board is connected with a group of digital test channels B, and the digital test channels B are connected with a clock domain switching circuit; s2: setting the system clock period to be 250 MHz; setting the period of an analog clock to be 240 MHz; s3: during testing, the digital testing channel group A is used for completing the function test of the MCU on the SOC chip to be tested; the digital testing channel group B is used for completing the function test of the Ethernet kernel on the SOC chip to be tested; s4: after the test is finished, judging whether the test chip passes, and if so, determining that the SOC chip is qualified; otherwise, the SOC chip to be tested is determined to be unqualified. Compared with the prior art, the two ports can start logic test at different frequencies at the same time by switching the clock domain switching circuit to the analog clock domain.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a parallel testing switching method applied to an SOC chip of an automatic tester.
Background
The System-on-Chip (soc) refers to a Chip in which a plurality of cores with different functions are integrated, each core has its own design parameters and test indexes, and the cores realize logic and data interaction through an internal bus. For example: the set-top box processor is a typical SOC chip, and the set-top box processor comprises a powerful microprocessor core, an Ethernet core, an audio signal coding and decoding core, a video signal coding and decoding core, an internal memory core, an external memory control core, a power management core and the like.
The clock speeds at which different functional cores operate are different, for example: the external serial data communication port of the microprocessor operates at 25MHz (clock period 40.0 ns), while its ethernet port operates on a 24MHz basis (clock period 41.667 ns). The audio coding and decoding needs the matching of a digital test channel and an audio analog signal source plus a collector, and the video coding and decoding needs the matching of the digital test channel and a high-frequency analog signal generator plus a collector.
The test of such complex chips requires that the automatic tester firstly has a plurality of test resources, including a programmable power supply (DPS), a direct current Parameter Measurement Unit (PMU), a high-speed digital test channel, at least two high-stability low-jitter programmable clock sources, a high-resolution audio analog signal generator (HR-AWG), a high-resolution audio analog signal collector (HR-DTZ), a high-speed analog signal generator (HS-AWG), a high-speed analog signal collector (HS-DTZ) and the like.
In some of these complex SOC chips, the architecture design allows the cores to be configured to operate and test independently in consideration of test cost and test convenience. This provides feasibility for parallel testing of multiple cores.
For the test of such a complex SOC chip, the conventional automatic tester generally sequences the functions of different cores to be tested, and then the automatic tester serially executes one test item. The main reason is that cores configured in the independent operation test mode may require tester resources corresponding to the core ports to operate in states of different frequencies (or different cycle lengths) due to different functions. For example, the data interface and MCU port need to operate at 25MHz (T1 =40ns period), and this port is used to configure the ethernet core to enter test mode. Meanwhile, the ethernet port requires 24MHz (T2 =41.667ns period). T1 and T2 cannot find the smallest common divisor other than 1, which requires that the two sets of digital test channels of the automatic tester operate separately and in different clock domains. Many automatic test machines cannot realize such functions and can only test serially.
When the operating frequencies of several cores cannot be divided based on the same system clock, serial testing must be performed in stages, each stage of testing having the tester configured to a particular testing frequency requires switching the system clock before the next stage of testing. The parallel test can not be performed, the test time can be prolonged, and the test cost is increased. Serial testing also results in failure to test data communication between two cores, and additional test items must be added to verify inter-core communication.
Disclosure of Invention
The invention provides a parallel test switching method applied to an SOC chip of an automatic testing machine for overcoming the defects of the prior art, and the method is switched to an analog clock domain through a clock domain switching circuit, so that two ports can start logic tests at different frequencies at the same time.
In order to achieve the purpose, the parallel test switching method applied to the SOC chip of the automatic tester is designed, comprises a test carrier plate, a digital test channel and a clock domain switching circuit, and is characterized in that: the specific process is as follows:
s1: the data interface and MCU end on the test carrier board are connected with a group of digital test channels A, the Ethernet interface end on the test carrier board is connected with a group of digital test channels B, and the digital test channels B are connected with a clock domain switching circuit;
s2: setting the system clock period to be 250MHz, and then setting the frequency of the digital test channel group A to be 250 MHz/10=25 MHz; setting the period of the analog clock to be 240MHz, and then setting the frequency of the digital test channel group B to be 240MHz/10=24 MHz;
s3: when the test is started, the digital test channel group A is used for completing the function test of the MCU on the SOC chip to be tested; the digital testing channel group B is used for completing the function test of the Ethernet kernel on the SOC chip to be tested;
s4: after the two tests are finished, judging whether the test is passed, if so, judging that the SOC chip is qualified; otherwise, the SOC chip to be tested is determined to be unqualified.
The clock domain switching circuit can be connected to a digital test channel at the audio core end.
The clock domain switching circuit can be connected to a digital test channel at the video kernel end.
The clock domain switching circuit can be connected to the data interface and the digital test channel of the MCU terminal.
The audio kernel end, the video kernel end, the data interface and the MCU end are arranged on the test carrier plate.
The clock domain switching circuit realizes the clock domain switching through a clock switching chip LMK 01020.
Compared with the prior art, the invention provides the parallel test switching method applied to the SOC chip of the automatic testing machine, and the logic test can be started simultaneously by the two ports under different frequencies by switching the clock domain switching circuit to the analog clock domain.
The automatic tester provides a maximum of 1152 digital test channels, each of which (32-channel group) can be switched freely between two clock domains, which greatly expands the possibility of frequency combination of digital test channel resources.
Drawings
Fig. 1 is a schematic diagram of a conventional test carrier plate structure.
FIG. 2 is a schematic flow chart of the present invention.
Fig. 3 is a clock domain switching circuit diagram.
FIG. 4 is a flow chart of the test of the present invention.
Fig. 5 is a schematic diagram of a test carrier plate structure according to an embodiment of the invention.
Detailed Description
The invention is further illustrated below with reference to the accompanying drawings.
As shown in fig. 1 to 4, a parallel test switching method applied to an SOC chip of an automatic tester includes the following specific processes:
s1: the data interface and MCU end on the test carrier board are connected with a group of digital test channels A, the Ethernet interface end on the test carrier board is connected with a group of digital test channels B, and the digital test channels B are connected with a clock domain switching circuit;
s2: setting the system clock period to be 250MHz, and then setting the frequency of the digital test channel group A to be 250 MHz/10=25 MHz; setting the period of the analog clock to be 240MHz, and then setting the frequency of the digital test channel group B to be 240MHz/10=24 MHz;
s3: when the test is started, the digital test channel group A is used for completing the function test of the MCU on the SOC chip to be tested; the digital testing channel group B is used for completing the function test of the Ethernet kernel on the SOC chip to be tested;
s4: after the two tests are finished, judging whether the test is passed, if so, judging that the SOC chip is qualified; otherwise, the SOC chip to be tested is determined to be unqualified.
The clock domain switching circuit may be coupled to the digital test channel at the audio core side.
The clock domain switching circuit may be connected to the digital test channel at the video core side.
The clock domain switching circuit can be connected to the data interface and the digital test channel of the MCU terminal.
The audio kernel end, the video kernel end, the data interface and the MCU end are arranged on the test carrier plate.
The clock domain switching circuit realizes clock domain switching through a clock switching chip LMK 01020.
The invention connects the clock domain switching circuit on the digital testing channel of the automatic tester, and can switch to the analog clock domain through the clock domain switching circuit according to the testing requirement, so that the two ports can start logic testing at the same time under different frequencies. The automatic tester provides a maximum of 1152 digital test channels, each of which (32-channel group) can be switched freely between two clock domains, which greatly expands the possibility of frequency combination of digital test channel resources. The clock domain switching circuit diagram is realized by using a 2-to-1 clock switching chip LMK 01020.
Example (b):
as shown in fig. 5, the analog signal testing (signal-to-noise ratio, harmonic distortion ratio, gain, etc.) of the audio core requires a different clock frequency than that required for the analog signal testing of the video core. Conventional testers also test both parts serially.
On the automatic testing machine, the high-speed analog signal generator and the high-speed analog signal collector can be configured to a system clock domain through the clock domain switching circuit and shared with a digital testing channel. Because the video core is usually composed of a 16-bit wide high-speed Digital-to-Analog Converter (DAC) and an Analog-to-Digital Converter (ADC), the parallel data bus for operation thereof operates at a refresh rate of 100MHz or more, and the data refresh rate is synchronized with the operating frequency of the DAC and the ADC. Therefore, the digital test resources and the high-speed analog test resources in the system clock domain can complete the test of the video core.
The communication between the audio core and the digital interface is in an asynchronous serial bus mode, and the corresponding digital test channel can be reserved in a system clock domain. The audio core typically has its own built-in fixed frequency generator (PLL) to work with its internal digital filters and digital signal processor. The frequency of the analog signal testing device cannot be strictly synchronous with a testing machine, so that the frequency spectrum of the input and output analog signals is inevitably leaked, and errors are introduced to later software processing and calculation. At this time, the audio analog signal generator and the audio analog signal collector are configured to another clock domain, i.e., an analog clock domain. The frequency of an analog clock domain can be adjusted freely without being limited by the working frequency of a digital test channel, the analog signal sent into a chip is optimized, the lowest frequency spectrum leakage is achieved, and the error of later software operation is reduced.
The audio core and the video core can be tested in parallel by utilizing the reasonable distribution of the two clock domains.
Claims (6)
1. A parallel test switching method applied to an SOC chip of an automatic tester comprises a test carrier plate, a digital test channel and a clock domain switching circuit, and is characterized in that: the specific process is as follows:
s1: the data interface and MCU end on the test carrier board are connected with a group of digital test channels A, the Ethernet interface end on the test carrier board is connected with a group of digital test channels B, and the digital test channels B are connected with a clock domain switching circuit;
s2: setting the system clock period to be 250MHz, and then setting the frequency of the digital test channel group A to be 250 MHz/10=25 MHz; setting the period of the analog clock to be 240MHz, and then setting the frequency of the digital test channel group B to be 240MHz/10=24 MHz;
s3: when the test is started, the digital test channel group A is used for completing the function test of the MCU on the SOC chip to be tested; the digital testing channel group B is used for completing the function test of the Ethernet kernel on the SOC chip to be tested;
s4: after the two tests are finished, judging whether the test is passed, if so, judging that the SOC chip is qualified; otherwise, the SOC chip to be tested is determined to be unqualified.
2. The parallel test switching method applied to the SOC chip of the automatic tester as claimed in claim 1, wherein: the clock domain switching circuit can be connected to a digital test channel at the audio core end.
3. The parallel test switching method applied to the SOC chip of the automatic tester as claimed in claim 1, wherein: the clock domain switching circuit can be connected to a digital test channel at the video kernel end.
4. The parallel test switching method applied to the SOC chip of the automatic tester as claimed in claim 1, wherein: the clock domain switching circuit can be connected to the data interface and the digital test channel of the MCU terminal.
5. The parallel test switching method applied to the SOC chip of the automatic tester as claimed in claim 2, wherein: the audio kernel end, the video kernel end, the data interface and the MCU end are arranged on the test carrier plate.
6. The parallel test switching method applied to the SOC chip of the automatic tester as claimed in claim 1, wherein: the clock domain switching circuit realizes the clock domain switching through a clock switching chip LMK 01020.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110109687.2A CN112924850A (en) | 2021-01-27 | 2021-01-27 | Parallel test switching method applied to SOC chip of automatic tester |
| TW110130141A TWI781726B (en) | 2021-01-27 | 2021-08-16 | Parallel-test switching method for testing system-on-chip by automatic test equipment |
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| CN202110109687.2A CN112924850A (en) | 2021-01-27 | 2021-01-27 | Parallel test switching method applied to SOC chip of automatic tester |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113190394A (en) * | 2021-07-02 | 2021-07-30 | 南京宏泰半导体科技有限公司 | SOC chip-oriented multi-clock-domain concurrent test system and test method thereof |
| CN113704045A (en) * | 2021-07-12 | 2021-11-26 | 新华三半导体技术有限公司 | Clock synchronization test method, system and chip |
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| Publication number | Publication date |
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| TW202229895A (en) | 2022-08-01 |
| TWI781726B (en) | 2022-10-21 |
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