TWI781726B - Parallel-test switching method for testing system-on-chip by automatic test equipment - Google Patents

Abstract

A parallel-switch testing method includes: connecting a first set of digital testing channels to a data interface and a micro-controller unit (MCU) on a testing carrier board, and connecting a second set of digital testing channels to an Ethernet network interface on the testing carrier board, in which the second set of digital testing channels is coupled to a clock domain switching circuit; setting a frequency of a system clock to be 250 MHz, and setting a frequency of an analog clock to be 240 MHz; during a test, performing a microcontroller function test of a system-on-chip (SOC) under test via the first set of channels, and performing a Ethernet core function test of the SOC under test via the second set of channels; after the function tests are completed, verifying whether the test is passed, if the test is passed, determining that the SOC under test is valid, or if the test is not passed, determining that the SOC under test is invalid.

Description

Parallel Test Switching Method for Testing Single Chip System Using Automatic Tester

The invention relates to the technical field of semiconductor testing, in particular to a parallel test switching method for testing a single-chip system by using an automatic testing machine.

Single-chip system (System-on-Chip) refers to the integration of multiple cores with different functions inside the same chip. Each core has its own design parameters and inspection indicators. The logic and data are realized through the internal bus between the cores. exchange. For example, the set-top box processor is a typical SOC chip, which contains a powerful microprocessor core, Ethernet core, audio signal codec core, video signal codec core, internal memory core, and externally expanded memory. body control kernel, power management kernel, etc.

The clock speeds of different functional cores are different. For example, the external serial data communication port of the microprocessor runs at 25 million hertz (MHz) (the clock cycle is 40.0 nanoseconds (ns)), while its Ethernet The Ethernet port runs at 24 MHz (clock cycle is 41.667ns). Audio codec requires the cooperation of digital test channels and audio analog signal sources plus collectors, while video codec requires the cooperation of digital test channels and high-frequency analog signal generators plus collectors.

The testing of such complex chips requires that the automatic tester first have a variety of test resources, including a programmable power supply (DPS), a DC parameter measurement unit (PMU), a high-speed digital test channel, and at least two programmable devices with high stability and low jitter. Design clock source, high-resolution audio analog signal generator (HR-AWG), high-resolution audio analog signal collector (HR-DTZ), high-speed analog signal generator (HS-AWG), high-speed analog signal collector ( HS-DTZ), etc.

The architecture design of some of these complex SOC chips allows the core to be configured as an independent working and testing mode in consideration of testing cost and testing convenience. This provides feasibility for multi-core parallel testing.

The traditional automatic testing machine for this type of complex SOC chip testing generally sorts the functions of different cores that need to be tested, and then the automatic testing machine executes the test items one by one in series. The main reason is that, due to different functions, the core configured as an independent working test mode will require the test machine resources corresponding to the core port to work at different frequencies (or different cycle lengths). For example, the data interface and MCU port need to work at 25MHz (period T1=40 ns), use this port to configure the Ethernet core to enter the test mode. At the same time, the Ethernet port needs to work at 24 MHz (period T2=41.667 ns). Period T1 and period T2 cannot find the least common divisor other than 1, which requires the two groups of digital test channels of the automatic test machine to work with different clock domains respectively. Many automatic testing machines cannot realize such a function, so they can only test in series.

When the operating frequency of several cores cannot be obtained based on the frequency division of the same system clock, it must be serially tested in segments. Each segment of the test allows the tester to configure a specific test frequency. Before the next segment of the test, it needs to Switch system clock. Cannot test in parallel, it will prolong the test time and increase the test cost. The serial test also makes it impossible to test the data communication between the two cores, and additional test items must be added to verify the communication between the cores.

In order to overcome the deficiencies in the prior art, the present invention provides a parallel test switching method that uses an automatic tester to test a single-chip system, and switches to an analog clock domain through a clock domain switching circuit, so that two ports can operate at different frequencies. Simultaneously starts the logic test.

In order to achieve the above purpose, a parallel test switching method using an automatic test machine to test a single-chip system is designed. The specific process includes:

S1: Connect a set of digital test channel A (hereinafter referred to as digital test channel group A) to the data interface and microcontroller (MCU) on the test carrier board, and connect a Group digital test channel B (hereinafter referred to as digital test channel group B), digital test channel group B is connected to a clock domain switching circuit;

S2: Set the system clock frequency to 250 MHz to set the frequency of digital test channel group A to 250MHz/10=25 MHz, and set the analog clock frequency to 240 MHz to set the frequency of digital test channel group B to 240MHz/ 10=24 MHz;

S3: At the beginning of the test, use the digital test channel group A to complete the functional test of the microcontroller on the single-chip system under test, and use the digital test channel group B to complete the functional test of the Ethernet core on the single-chip system under test; and

S4: After the two tests are completed, judge whether the test is passed. If the test is passed, the single-chip system under test is determined to be qualified; if the test is not passed, the single-chip system under test is determined to be qualified.

The clock domain switching circuit can be connected to the digital test channel of the audio core end.

The clock domain switching circuit can be connected to the digital test channel of the video core end.

The clock domain switching circuit can be connected to the data interface and the digital test channel at the MCU end.

The audio core end, the video signal core end, the data interface and the MCU end are arranged on the test carrier board.

The clock domain switching circuit realizes the clock domain switching through the clock switching chip LMK01020.

Compared with the prior art, the present invention provides a parallel test switching method applied to automatic tester SOC chips, switching to the analog clock domain through a clock domain switching circuit, so that two ports can start logic tests simultaneously at different frequencies .

The automatic testing machine provides a maximum of 1152 digital test channels, each group (32 channels in one group) can be switched between two clock domains at will, which greatly expands the possibility of digital test channel resources in frequency combination .

The present invention will be further described below according to the accompanying drawings.

As shown in Figures 1 to 4, a parallel test switching method using an automatic tester to test a single-chip system, the specific process is as follows:

S1: Connect a set of digital test channel A (hereinafter referred to as digital test channel group A) to the data interface and microcontroller (micro controller unit, MCU) on the test carrier board, and connect the Ethernet to the test carrier board. The interface end is connected to a group of digital test channel B (hereinafter referred to as digital test channel group B), and the digital test channel group B is connected to a clock domain switching circuit;

S2: Set the system clock frequency to 250 megahertz (MHz) to set the frequency of digital test channel group A to 250 MHz/10=25 MHz, and set the analog clock frequency to 240 MHz to set digital test channel group B The frequency is 240MHz/10=24 MHz;

S3: At the beginning of the test, use the digital test channel group A to complete the function test of the microcontroller (MCU) on the single-chip system under test; use the digital test channel group B to complete the functional test of the Ethernet core on the single-chip system under test, The single-chip system under test is driven by the voltage AVDD provided by power supply #1 and the voltage VDD provided by power supply #2, and the single-chip system under test further receives the ground voltage AGND (which is the analog signal ground) and the ground voltage GND (which is the signal ground) land);

S4: After the above two tests are completed, judge whether the test is passed. If the test is passed, the single-chip system under test is determined to be qualified; if the test is not passed, the single-chip system under test is determined to be unqualified.

The clock domain switching circuit can be connected to the digital test channel on the audio core side.

The clock domain switching circuit can be connected to the digital test channel on the video core side.

The clock domain switching circuit can be connected to the data interface and the digital test channel on the MCU side.

The audio core side, the video core side, the data interface and the MCU side are set on the test carrier board.

The clock domain switching circuit implements clock domain switching through the clock switching chip LMK01020.

In the present invention, a clock domain switching circuit is connected to the digital test channel of the automatic testing machine. According to the test requirements, the clock domain switching circuit can be switched to the analog clock domain, so that the two ports can simultaneously start logic at different frequencies. test. The automatic testing machine provides a maximum of 1152 digital test channels, each group (32 channels in one group) can be switched between two clock domains at will, which greatly expands the possibility of digital test channel resources in frequency combination . The clock domain switching circuit diagram realized by using the 2-to-1 clock switching chip LMK01020 (the system circuit diagram is shown in Figure 3A and Figure 3B, where the leftmost nodes in Figure 3A (marked as 12, 14, 17, 18 , 20, 21, 23, 24, 38, 39, 41, 42, 44, 45, 47, 48) are respectively the same as the rightmost nodes in Figure 3B; in other words, Figure 3B is an extension of Figure 3A, and 3A and 3B jointly present a clock domain switching circuit).

Example:

As shown in Figure 5, the clock frequency required for analog signal tests (SNR, HDR, gain, etc.) of audio cores is different from that required for analog signal tests of video cores. The traditional testing machine also tests these two parts in series.

On the automatic testing machine of the present invention, both the high-speed analog signal generator and the high-speed analog signal collector can be configured in the system clock domain through the clock domain switching circuit, and shared with the digital test channel. Because the video core usually consists of a 16-bit high-speed digital-to-analog converter (DAC, Digital-to-Analog Converter) and a high-speed analog-to-digital converter (ADC, Analog-to-Digital Converter), its working parallel data bus Work at an update rate above 100 MHz, and the data update rate is synchronized with the operating frequency of DAC and ADC. In this way, the digital test resources and high-speed analog test resources in the system clock domain can complete the test of the video core.

The communication between the audio core and the digital interface is an asynchronous serial bus mode, which can keep its corresponding digital test channel in the system clock domain. The audio core usually has its own built-in fixed frequency generator (such as PLL) to cooperate with its internal digital filter and digital signal processor. Its frequency cannot be strictly synchronized with the testing machine, which will inevitably lead to spectrum leakage of input and output analog signals, and introduce errors into later software processing and calculation. At this time, configure the audio analog signal generator and the audio analog signal collector to another clock domain, namely the analog clock domain. The frequency of the analog clock domain can be adjusted arbitrarily without being limited by the operating frequency of the digital test channel, and the analog signal sent to the chip can be optimized to achieve the lowest spectrum leakage and reduce the error of later software calculations.

Using the reasonable distribution of the two clock domains, the audio core and video core can be tested in parallel.

AVDD, VDD: voltage AGND, GND: ground voltage

[Figure 1] is a schematic diagram of the structure of the existing test carrier board; [Fig. 2] is a schematic flow chart of the present invention; [Figure 3A] and [Figure 3B] are clock domain switching circuit diagrams; [Fig. 4] is a test flow chart of the present invention; and [Fig. 5] is a schematic diagram of the structure of the test carrier board according to the embodiment of the present invention.

AVDD, VDD: voltage AGND, GND: ground voltage

Claims (6)

A parallel test switching method, which is applied to an automatic tester to test a single-chip system, the parallel test switching method includes: S1: Connect a first group of digital test channels to a data interface and a microcontroller end on a test carrier board, and connect a second group of digital test channels to an Ethernet interface end on the test carrier board, A clock domain switching circuit is connected to the second group of digital test channels; S2: set a system clock frequency to 250 million hertz (MHz), so that the frequency of the first group of digital test channels is set to 25 million hertz, and set an analog clock frequency to 240 million hertz, so that The frequency of the second set of digital test channels is set to 24 megahertz; S3: When the test starts, use the first group of digital test channels to complete a first functional test of the microcontroller on a single-chip system under test, and use the second group of digital test channels to complete the first functional test of the single-chip system under test. a second functional test of the Ethernet core; and S4: After the first functional test and the second functional test are completed, determine whether the test is passed. If the test is passed, the single-chip system under test is determined to be qualified; if the test fails, the single-chip system under test is determined to be unqualified. qualified. The parallel test switching method as claimed in item 1, wherein the clock domain switching circuit is connected to a digital test channel of an audio core end. The parallel test switching method as claimed in item 1, wherein the clock domain switching circuit is connected to a digital test channel of a video core side. As the parallel test switching method of claim item 1, wherein the clock domain switching circuit is connected to the data interface and the digital test channel on the microcontroller side. As the parallel test switching method of claim item 1, wherein the clock domain switching circuit is connected to a digital test channel of at least one of an audio core end or a video core end, and the audio core end and the video core end are arranged on on the test carrier board. The parallel test switching method as claimed in claim 1, wherein the clock domain switching circuit implements clock domain switching through a clock switching chip LMK01020.

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