CN108549751A - The layout method of register matrix - Google Patents
The layout method of register matrix Download PDFInfo
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- CN108549751A CN108549751A CN201810262652.0A CN201810262652A CN108549751A CN 108549751 A CN108549751 A CN 108549751A CN 201810262652 A CN201810262652 A CN 201810262652A CN 108549751 A CN108549751 A CN 108549751A
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- register
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- layout information
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The present invention provides a kind of layout methods of register matrix, including：It converts the logical code of register matrix to the connection relation data of functional unit, and converts address decoding circuitry to multi-level selector tree structure, the layout information of the connection relation data and multi-level selector tree structure composition register matrix；Register cell is grouped by the layout information for obtaining the register matrix according to the layout information, forms multiple register groups, and generate corresponding data path file according to the layout information；The register cell is put according to the data path file.The layout method of register matrix provided by the present invention can obviously solve the problems, such as routing congestion, optimize interconnection delay, improve working frequency.
Description
Technical field
The present invention relates to integrated circuit physical Design technical field, more particularly to a kind of layout method of register matrix.
Background technology
It is increasingly competitive with extensive and super large-scale integration universal and application, in competition
It occupies a tiny space, must just reduce chip area as far as possible, reduce cost.With the continuous diminution of process, cost is in
Exponential increase reduces the more aobvious protrusion of advantage of area.Nowadays in system on chip storage unit account for 70% to 80% area, very
To more, the area of chip can be greatly reduced by reducing the area of storage unit, reduce cost.Storage unit is generally used for data
Processing, usual timing path are critical path, and access speed often determines the performance of chip.Register matrix storage relative to
Memory storage has the characteristics that speed is fast, area is small, and utilization is more and more extensive.The use of register matrix is all adopted at present
With the mode of embedded core, this method disadvantage area is larger, cost is higher, layout is limited, sequential is poor.
Invention content
The present invention provides a kind of layout method of register matrix, that its purpose is to register matrix areas is larger,
The problem that cost is higher, layout is limited, sequential is poor.
In order to achieve the above object, the embodiment provides a kind of layout methods of register matrix, including：
It converts the logical code of register matrix to the connection relation data of functional unit, and address decoding circuitry is turned
Multi-level selector tree structure is turned to, the connection relation data and the multi-level selector tree structure form register matrix
Layout information；
The layout information for obtaining the register matrix, according to the layout information by the deposit in the register matrix
Device unit is grouped, and forms multiple register groups, and generate corresponding data path file according to the layout information；
The register cell is put according to the data path file.
Wherein, the clock of each register cell is controlled by gated clock, and each gated clock is put
In the center of register group associated there.
Wherein, the connection relation data for converting the logical code of register matrix to functional unit, and by address
Decoding circuit is converted into the step of multi-level selector tree structure and is specially：
It is assumed that the depth of register matrix is 2D(address bit wide is D), the number of bit wide B, register cell have 2D*B
It is a；
The output signal of each two adjacent register units of identical bits selects output, choosing by the selector of an alternative
It is address wire lowest order to select signal；
The output signal of each adjacent two selector is step by step believed the output of selector by address wire time low level selection output
In number access next stage selector, Mux-Tree structures are formed, the number of selector is (2D- 1) * B.
Wherein, the layout information for obtaining the register matrix divides register cell according to the layout information
Group forms multiple register groups, and the step of generating corresponding data path file according to the layout information is specially：
It is assumed that the register cell for sharing M identical bits is put into a line, a total of 2D/ M is arranged；
(2 will to be connected with M register cellM-1- 1) a selector is placed in register adjacent rows, and such 2DA deposit
Device and (2D- 1) a selector forms a register group；
The register group for differing position is divided into A1 rows A2 row, wherein A1, A2 meet A1*A2=B；
The register group origin coordinates of lowest order is (x0, y0), the height of each register cell is h, width 1, then most
The coordinate of low level k row n column register units is (x0+ l* (n-1), y0+2h*(k-1))；
Register group the height H, width L of identical bits be respectively：H=2D+1*h/M；L=M*l；
The starting point coordinate for differing a row b column register groups of position is (x0+ L* (b-1), y0+H*(a-1))；
Data path file is produced according to the starting point coordinate of register group and register cell grouping situation.
Wherein, described the step of putting the register cell according to the data path file, further includes：
If the number of the register cell and the number of the functional unit of the register matrix be not corresponding, weight is needed
Newly the register cell is grouped.
The said program of the present invention has following advantageous effect：
The layout method of register matrix described in the above embodiment of the present invention passes through the logic generation to register matrix
Code is integrated, and address decoding circuitry is integrated into multi-level selector tree structure, while the clock of each register is by gating
Clock control；Then register matrix is grouped according to the layout information of register matrix, generates corresponding data path file,
By data path file input placement-and-routing tool, register cell is put；This method is suitable for high density, register square
The placement-and-routing of battle array, can obviously solve the problems, such as routing congestion, and optimize interconnection delay, improve working frequency.
Description of the drawings
Fig. 1 is the flow diagram of the layout method of the register matrix of the present invention；
Fig. 2 is the circuit structure diagram of the register cell of the present invention；
Fig. 3 is the Mux-Tree circuit structure diagrams of the identical bit register of the present invention；
Fig. 4 is partial schematic diagram of the register cell of the present invention in placement-and-routing's tool.
Specific implementation mode
To keep the technical problem to be solved in the present invention, technical solution and advantage clearer, below in conjunction with attached drawing and tool
Body embodiment is described in detail.
The present invention is directed to the problem that existing register matrix area is larger, cost is higher, layout is limited, sequential is poor,
Provide a kind of layout method of register matrix.
As shown in Figure 1 and Figure 4, the embodiment provides a kind of layout methods of register matrix, including：
Step 1, the logical code of register matrix is converted to the connection relation data of functional unit, by address decoding electricity
Road is converted into multi-level selector tree structure, and the connection relation data and the multi-level selector tree structure form register
The layout information of matrix；
Step 2, the layout information for obtaining the register matrix, will be in the register matrix according to the layout information
Register cell grouping, form multiple register groups, and corresponding data path file is generated according to the layout information；
Step 3, the register cell is put according to the data path file.
The layout method of register matrix described in the above embodiment of the present invention passes through the logic generation to register matrix
Code is integrated, and address decoding circuitry is integrated into multi-level selector tree structure, while the clock of each register is by gating
Clock control；Then register matrix is grouped according to the layout information of register matrix, generates corresponding data path file,
By data path file input placement-and-routing tool, register cell is put；This method is suitable for high density, register square
The placement-and-routing of battle array, can obviously solve the problems, such as routing congestion, and optimize interconnection delay, improve working frequency.
Wherein, the clock of each register cell is controlled by gated clock, and each gated clock is put
In the center of register group associated there.
As shown in Figures 2 and 3, the connection relation number for converting the logical code of register matrix to functional unit
According to, and the step of converting address decoding circuitry to multi-level selector tree structure is specially：
Step 11, it is assumed that the depth of register matrix is 2D(address bit wide is D), bit wide B, the number of register cell
Have 2D* B；
Step 12, the output signal of each two adjacent register units of identical bits is selected by the selector of an alternative
Output, selection signal are address wire lowest order；
Step 13, the output signal of each adjacent two selector is by address wire time low level selection output, step by step by selector
Output signal access next stage selector in, form Mux-Tree structures, the number of selector is (2D- 1) * B.
Method described in the above embodiment of the present invention is counted by the number of the register cell to register matrix
It calculates, and is connected by the selector of the alternative, form Mux-Tree structures, avoid
Wherein, the layout information for obtaining the register matrix divides register cell according to the layout information
Group forms multiple register groups, and the step of generating corresponding data path file according to the layout information is specially：
Step 21, it is assumed that the register cell for sharing M identical bits is put into a line, and a total of 2D/ M is arranged；
Step 22, (2 will to be connected with M register cellM-1- 1) a selector is placed in register adjacent rows, in this way
2DA register and (2D- 1) a selector forms a register group；
Step 23, the register group for differing position is divided into A1 rows A2 row, wherein A1, A2 meet A1*A2=B；
Step 24, the register group origin coordinates of lowest order is (x0, y0), the height of each register cell is h, width
It is 1, then the coordinate of lowest order k rows n column register units is (x0+ l* (n-1), y0+2h*(k-1))；
Step 25, register group the height H, width L of identical bits are respectively：H=2D+1*h/M；L=M*l；
Step 26, the starting point coordinate for differing a row b column register groups of position is (x0+ L* (b-1), y0+H*(a-1))；
Step 27, data path text is produced according to the starting point coordinate of register group and register cell grouping situation
Part.
Data path file described in the above embodiment of the present invention is the object for flowing to information and functional unit of data
Relative position information is managed, the coordinate of each register cell and the starting of register group can be confirmed by the above method
Point coordinates is input in placement-and-routing's tool and is connected up.
Wherein, described the step of putting the register cell according to the data path file, further includes：
Step 4, if the number of the register cell and the number of the functional unit of the register matrix be not corresponding,
It needs again to be grouped the register cell.
The layout method of register matrix described in the above embodiment of the present invention further includes being put not to register cell
When meeting layout requirements, register packet parameters are changed, and repeat the operation of step 2, until meeting the layout of register matrix
It is required that.
The layout method of register matrix described in the above embodiment of the present invention passes through the logic generation to register matrix
Code is integrated, and address decoding circuitry is integrated into multi-level selector tree structure, while the clock of each register is by gating
Clock control；Then register matrix is grouped according to the layout information of register matrix, generates corresponding data path file,
By data path file input placement-and-routing tool, register cell is put；This method is suitable for high density, register square
The placement-and-routing of battle array, can obviously solve the problems, such as routing congestion, and optimize interconnection delay, improve working frequency.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, it can also make several improvements and retouch, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (5)
1. a kind of layout method of register matrix, which is characterized in that including：
It converts the logical code of register matrix to the connection relation data of functional unit, and converts address decoding circuitry to
Multi-level selector tree structure, the cloth of the connection relation data and multi-level selector tree structure composition register matrix
Office's information；
The layout information for obtaining the register matrix, according to the layout information by the register list in the register matrix
Member grouping forms multiple register groups, and generates corresponding data path file according to the layout information；
The register cell is put according to the data path file.
2. the layout method of register matrix according to claim 1, which is characterized in that each register cell
Clock is controlled by gated clock, and the gated clock is placed in the center of register group associated there.
3. the layout method of register matrix according to claim 1, which is characterized in that the patrolling register matrix
It collects code and is converted into the connection relation data of functional unit, and convert address decoding circuitry to multi-level selector tree structure
Step is specially：
It is assumed that the depth of register matrix is（Address bit wide is D）, the number of bit wide B, register cell has
It is a；
The output signal of each two adjacent register units of identical bits selects output, selection letter by the selector of an alternative
Number be address wire lowest order；
The output signal of each adjacent two selector is step by step connect the output signal of selector by address wire time low level selection output
Enter in next stage selector, form Mux-Tree structures, the number of selector isIt is a.
4. the layout method of register matrix according to claim 3, which is characterized in that described to obtain the register square
Register cell, is grouped according to the layout information, forms multiple register groups, and according to the layout by the layout information of battle array
Information generate corresponding data path file the step of be specially：
It is assumed that the register cell for sharing M identical bits is put into a line, it is a total ofRow；
By what is be connected with M register cellA selector is placed in register adjacent rows, in this wayIt is a to post
Storage withA selector forms a register group；
The register group for differing position is divided into A1 rows A2 row, wherein A1, A2 meets；
The register group origin coordinates of lowest order is, the height of each register cell is h, width l, then minimum
Position k row n column register units coordinate be；
Register group the height H, width L of identical bits be respectively：；；
The starting point coordinate for differing a row b column register groups of position is
；
Data path file is produced according to the starting point coordinate of register group and register cell grouping situation.
5. the layout method of register matrix according to claim 4, which is characterized in that described according to the data path
File puts the step of register cell and further includes：
If the number of the register cell and the number of the functional unit of the register matrix be not corresponding, institute is reacquired
Register cell is grouped by the layout information for stating register matrix according to the layout information, forms multiple register groups, and root
Corresponding data path file is generated according to the layout information.
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| CN116895325A (en) * | 2023-06-21 | 2023-10-17 | 合芯科技有限公司 | ICG classification method, test method and classification device for digital array register |
| CN117272893A (en) * | 2023-11-21 | 2023-12-22 | 芯来智融半导体科技(上海)有限公司 | Chip signal receiving circuit and method |
| CN116895325B (en) * | 2023-06-21 | 2024-05-07 | 合芯科技有限公司 | ICG classification method, test method and classification device for digital array register |
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| CN116895325B (en) * | 2023-06-21 | 2024-05-07 | 合芯科技有限公司 | ICG classification method, test method and classification device for digital array register |
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