CN116895325A - ICG classification method, test method and classification device for digital array register - Google Patents
ICG classification method, test method and classification device for digital array register Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
Abstract
The invention discloses an ICG classification method, a test method and a classification device of a digital array register, wherein the method comprises the following steps: obtaining design data of a digital line register and a model list of the digital line register; according to the design data and the model list, acquiring actual working condition data of each row and column of the digital row and column register and an ICG unit list corresponding to each row and column; and generating readable files of the ICG group based on the actual working condition data of each row and each column and the ICG unit list. By adopting the embodiment of the invention, the row and column data of the digital row and column registers are obtained through the design data and the model list, and the overturn signals are applied to the specific register row and column based on the row and column data, so that the overturn rate of the register row and column with pressure drop problem and the row with normal operation are realized, and the technical problem that the problematic row and column cannot be positioned due to the direct application of the overturn signals to all the rows and columns is avoided.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to an ICG (information and communication gateway) classification method, a test method and a classification device of a digital array register.
Background
Because of the limited capabilities of industry configurable memory generation tools, our processor core uses a large number of Digital Array registers of the multiple read and multiple write type to achieve high speed, high performance multi-threaded processing capabilities, but this can lead to the risk of excessive voltage drops, and these risks can be difficult to resolve with industry tools for ease of locating the problem. The reason is that: 1. the large number and duty cycle of digital array registers results in a relatively high power consumption density in the relevant area due to the high concentration; 2. in contrast to memories, digital array registers are controlled by corresponding ICGs (Integrated Clock Gating, integrated clock gating units) whose data read-out and write-in are controlled by a large number of clones in order to meet timing requirements at the back-end implementation stage, how to map to corresponding row-column register arrays, and reasonably accurate classification of these ICGs is critical to EMIR analysis. In the prior art, under the condition of limiting pressure test, the appointed turnover rate information is directly reversely marked on all ICG output ports, and for a CPU chip with a large number of digital array registers, EMIR analysis cannot locate the real problem of the chip.
Disclosure of Invention
The invention provides an ICG classification method, a test method and a classification device for a digital array register, which are used for solving the technical problem that the real problem of a chip cannot be positioned when the digital array register is tested in the prior art.
In order to solve the above technical problems, an embodiment of the present invention provides an ICG classification method for a digital array register, which is characterized by comprising:
obtaining design data of a digital line register and a model list of the digital line register;
according to the design data and the model list, acquiring actual working condition data of each row and column of the digital row and column register and an ICG unit list corresponding to each row and column;
and generating the readable file of the ICG group based on the actual working condition data of each row and each column and the ICG unit list.
According to the invention, the actual working condition of the digital row-column register and the ICG unit list are obtained through the design data and the model list; based on the actual working condition and the ICG unit list, the overturning condition of each row and column of the digital row and column register under the normal working condition can be obtained, the generated readable file of the ICG group can be used for simulating the actual working condition, and the overturning rate signal is applied to a specific register row and column, so that the technical problem that the problematic row and column cannot be positioned due to the fact that the overturning signal is directly applied to all the rows and columns is avoided.
Further, according to the design data and the model list, acquiring actual condition data of each row and column of the digital row and column register and an ICG unit list corresponding to each row and column, including:
wherein, the actual working condition data includes: the number of times of reading and writing and the overturning sequence of each row and column;
generating row and column data of the digital row and column register according to the design data and the model list;
acquiring the read-write times of each row and column in the operation of the digital row and column register from the row and column data; and determining the turning sequence of each row and column in the operation of the digital row and column register according to the row and column data, and generating an ICG unit list corresponding to each row and column.
According to the invention, the reading and writing times of each row and column of the digital row and column register and the turning sequence of each row and column of the digital row and column register are obtained through the row and column data of the digital register, and the readable file of the ICG group for simulating the turning condition of each row and column of the digital row and column register under the actual working condition can be generated according to the actual working conditions and the ICG unit list corresponding to each row and column, so that the technical problem that the problematic rows and columns cannot be positioned due to the fact that turning signals are directly applied to all the rows and columns is avoided.
Further, determining a flip order of each row and column during operation of the digital row and column register according to the row and column data, and obtaining an ICG unit list corresponding to each row and column, including:
reading a hierarchical structure module list and a keyword list from the rank data;
acquiring line width data of the digital line-column register based on the hierarchical structure module list and the keyword list;
determining the turning sequence of each row and column according to the row width data; and generating the ICG unit list according to the line width data.
According to the invention, the read-write times of the digital rank register and the integrated gating units of the actually-operated ranks are obtained based on the rank data, so that the read-write times and the inheritance gating unit list are used for generating the readable file of the ICG group for designating a certain rank to turn, the tested chip is used for carrying out the digital rank register turning rate test in a mode close to the actual working condition, the direct application of turning signals to all ranks is avoided, and the register ranks with problems are conveniently positioned.
Further, generating the ICG unit list according to the line width data includes:
acquiring a naming rule of the digital rank register and a word line rule of the digital rank register;
and determining a preset row and column of the digital row and column register which is turned over under the actual working condition according to the row width data, determining ICGs corresponding to the preset row and column according to the naming rule and the word line rule by a tracking method, and generating the ICG unit list.
The invention is based on the naming rule and word line rule of the digital line-row register, and the integrated gate control unit corresponding to the working line of the digital line-row register under the actual working condition is tracked by combining line width data; thus, a list of ICG units available for testing is obtained, so that the readable files of the ICG group formed based on the list can apply a flipping signal to a specific row and column when the readable files are executed, and the register row with problems is positioned conveniently.
Further, the tracking method includes: forward tracking, keyword searching, and word line tracking.
In another aspect, an embodiment of the present invention provides a method for testing a digital array register, including:
according to the ICG classification method of the digital array register, the readable file of the ICG group is generated;
and according to the readable file of the ICG group, applying a turnover signal to ICGs of each row and column in the digital row and column register, and performing power consumption calculation based on the turnover rate of each row and column to obtain a power consumption test result.
According to the invention, the row-column data of the digital row-column register is obtained through the design data and the model list, and the overturning signals are applied to the specific register rows based on the row-column data, so that the overturning rate of each row-column is close to that of each row-column under the normal working condition, the specific parameters such as the overturning rate, the power consumption, the pressure drop and the like of each row-column which are problematic under the normal working condition are kept under the test condition, and the technical problem that the problematic row-column cannot be positioned due to the fact that the overturning signals are directly applied to all the rows is avoided.
Further, according to the readable file of the ICG group, applying a flip signal to ICGs of each row in a digital row-column register, and performing power consumption calculation based on the flip rate of each row to obtain a power consumption test result, including:
wherein, the power consumption test result comprises: static power consumption and dynamic power consumption;
configuring static parameters and dynamic parameters according to the readable file of the ICG group;
after the VCD file is read, the digital array register is enabled to enter a standby state according to the static parameters, and static power consumption is obtained based on calculation of leakage current of the digital row-column register in the standby state; after reading the VCD file and the TWF file, applying a turnover signal to the ICG corresponding to each row according to the turnover sequence of each row and the read-write times of each row according to the dynamic parameters;
and recording the turnover rate of each row and column, and calculating the dynamic power consumption of the digital row and column register based on the turnover rate of each row and column.
According to the invention, through the readable files of the ICG group, the overturn signals are applied to the digital row-column registers according to the preset overturn sequence and read-write times, so that the digital row-column registers can perform power consumption test under the condition of approaching the actual working condition, the overturn signals are prevented from being directly applied to all rows and columns, and the rows and columns of the digital row-column registers, which are problematic under the actual working condition, can be conveniently positioned subsequently.
Further, after recording the flip rate of each row and column, and calculating the dynamic power consumption of the digital row and column register based on the flip rate of each row and column, the method includes:
and carrying out EMIR analysis on the digital array register according to the dynamic power consumption.
According to the invention, through the readable file of the ICG group, a turnover signal is applied to the digital row-column register according to a preset turnover sequence and read-write times, so that the dynamic power consumption of the digital row-column register is obtained under the condition of approaching to an actual working condition, and the rows and columns of the digital row-column register, which are problematic under the actual working condition, are positioned based on the dynamic power consumption; the direct application of the flipping signal to all rows and columns is avoided.
Further, after generating the readable file of the ICG group, it includes:
and according to the readable file of the ICG group, checking the number of the registers under the control of the integrated clock gating unit and the level of the registers under the control of the integrated clock gating unit to form a checking result.
On the other hand, the embodiment of the invention also provides a digital array register testing device, which comprises: the device comprises a data acquisition unit, a data processing unit and an ICG classification unit;
the data acquisition unit is used for acquiring design data of the digital line registers and model lists of the digital line registers;
the data processing unit is used for acquiring actual working condition data of each row and column of the digital row and column register and an ICG unit list corresponding to each row and column according to the design data and the model list;
the ICG classification unit is used for generating readable files of the ICG group based on the actual working condition data of each row and each column and the ICG unit list.
According to the invention, the actual working condition of the digital row-column register and the ICG unit list are obtained through the design data and the model list; based on the actual working condition and the ICG unit list, the overturning condition of each row and column of the digital row and column register under the normal working condition can be obtained, the generated readable file of the ICG group can be used for simulating the actual working condition, and the overturning rate signal is applied to a specific register row and column, so that the technical problem that the problematic row and column cannot be positioned due to the fact that the overturning signal is directly applied to all the rows and columns is avoided.
Drawings
FIG. 1 is a flow chart of an embodiment of a method for classifying ICG of a digital array register according to the present invention;
FIG. 2 is a flow chart of an embodiment of a method for testing a digital array register according to the present invention;
FIG. 3 is a schematic diagram of an embodiment of a digital array register ICG classification apparatus according to the present invention;
FIG. 4 is a flowchart illustrating an ICG classification method for a digital array register according to the present invention;
FIG. 5 is a flowchart illustrating a method for testing a digital rank register according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the prior art, after the P & R (Place and Route) unit devices in the digital chip back end design are automatically placed and automatically routed), ICGs (Integrated Clock Gating ) are cloned in a large number, and it is not known which ICGs are a certain row or a certain column for controlling the digital array (digital array register), so that the corresponding ICG flip setting cannot be performed, and therefore, an accurate EMIR analysis (electromigration and voltage drop analysis) cannot be performed on the digital array region. The invention provides an ICG classification method, a testing method and a classification device for a digital array register, which are used for solving the problems.
Referring to fig. 1, a flow chart of an embodiment of an ICG classification method of a digital array register according to the present invention includes steps 101-103, specifically as follows:
step 101: design data for a digital rank register and a model list for the digital rank register are obtained.
In this embodiment, the design data is the design data of the chip to be tested after winding.
Step 102: and acquiring actual working condition data of each row and column of the digital row and column register and an ICG unit list corresponding to each row and column according to the design data and the model list.
In this embodiment, step 102 includes: wherein, the actual working condition data includes: the number of times of reading and writing and the overturning sequence of each row and column; generating row and column data of the digital row and column register according to the design data and the model list; acquiring the read-write times of each row and column in the operation of the digital row and column register from the row and column data; and determining the turning sequence of each row and column in the operation of the digital row and column register according to the row and column data, and generating an ICG unit list corresponding to each row and column.
Referring to fig. 5, in this embodiment, a front-end team may obtain read/write count statistics of a digital rank register according to design data and a model list, that is, read/write count of each rank of the digital rank register in this embodiment; the back-end team then tracks the ICGs corresponding to each row and column based on the design data and the model list, thereby generating an ICG unit list corresponding to each row and column; the read-write times are actual working condition data, and are used for applying a turnover signal according to the corresponding read-write times of each row and column in the subsequent test, so that the chip to be tested is tested under the condition close to the actual working condition.
According to the embodiment, the reading and writing times of each row and column of the digital row and column register and the turning sequence of each row and column of the digital row and column register are obtained through row and column data of the digital register, and according to the actual working conditions and ICG unit lists corresponding to each row and column, a readable file of an ICG group (ICG group) for simulating the turning condition of each row and column of the digital row and column register under the actual working conditions can be generated, so that the technical problem that problematic rows and columns cannot be located due to the fact that turning signals are directly applied to all rows and columns is solved.
In this embodiment, determining, according to the rank data, a flip order of each rank during operation of the digital rank register, and obtaining an ICG unit list corresponding to each rank, including: reading a hierarchical structure module (hinst) list and a keyword (keyword) list from the rank data; acquiring line width data of the digital line-column register based on the hierarchical structure module list and the keyword list; determining the turning sequence of each row and column according to the row width data; and generating the ICG unit list according to the line width data.
According to the embodiment, the reading and writing times of the digital rank register and the integrated gating units of the actual working ranks are obtained based on the rank data, so that the read file of the ICG group which can be used for designating a certain rank to turn is generated based on the reading and writing times and the inheritance gating unit list, a tested chip is enabled to conduct the digital rank register turning rate test in a mode close to an actual working condition, the fact that turning signals are directly applied to all ranks is avoided, and the register ranks with problems are conveniently located.
In this embodiment, determining, according to the rank data, a flip order of each rank during operation of the digital rank register, and obtaining an ICG unit list corresponding to each rank, including: reading a hierarchical structure module list and a keyword list from the rank data; acquiring line width data of the digital line-column register based on the hierarchical structure module list and the keyword list; determining the turning sequence of each row and column according to the row width data; and generating the ICG unit list according to the line width data.
According to the embodiment, the reading and writing times of the digital rank register and the integrated gating units of the actual working ranks are obtained based on the rank data, so that the read file of the ICG group which can be used for designating a certain rank to turn is generated based on the reading and writing times and the inheritance gating unit list, a tested chip is enabled to conduct the digital rank register turning rate test in a mode close to an actual working condition, the fact that turning signals are directly applied to all ranks is avoided, and the register ranks with problems are conveniently located.
In this embodiment, further, generating the ICG unit list according to the line width data includes: acquiring a naming rule of the digital rank register and a word line rule of the digital rank register; and determining a preset row and column of the digital row and column register which is turned over under the actual working condition according to the row width data, determining ICGs corresponding to the preset row and column according to the naming rule and the word line rule by a tracking method, and generating the ICG unit list.
The embodiment is based on naming rules and word line rules of the digital line-row registers, and the integrated gating units corresponding to the working lines of the digital line-row registers under actual working conditions are tracked by combining line width data; thus, a list of ICG units available for testing is obtained, so that the readable files of the ICG group formed based on the list can apply a flipping signal to a specific row and column when the readable files are executed, and the register row with problems is positioned conveniently.
In this embodiment, the tracking method includes: forward tracking, keyword searching, and word line tracking.
The embodiment is based on naming rules and word line rules of the digital line-row registers, and the integrated gating units corresponding to the working lines of the digital line-row registers under actual working conditions are tracked by combining line width data; thus, an integrated gate control unit list for testing is obtained, and when the subsequent readable files of ICG groups formed based on the list are executed, the cloned digital array of which row/column is controlled by ICG can be seen from the list, and reverse marking of the inversion rate is carried out on the ICG groups.
Step 103: and generating the readable file of the ICG group based on the actual working condition data of each row and each column and the ICG unit list.
According to the embodiment, the actual working conditions of the digital row-column registers and the ICG unit list are obtained through the design data and the model list; based on the actual working condition and the ICG unit list, the overturning condition of each row and column of the digital row and column register under the normal working condition can be obtained, the generated readable file of the ICG group can be used for simulating the actual working condition, and the overturning rate signal is applied to a specific register row and column, so that the technical problem that the problematic row and column cannot be positioned due to the fact that the overturning signal is directly applied to all the rows and columns is avoided.
Referring to fig. 2, a flow chart of an embodiment of a method for testing a digital array register according to the present invention mainly includes steps 201-202.
Step 201: according to the ICG classification method of the digital array register, the readable file of the ICG group is generated.
In this embodiment, after step 201, it includes: and according to the readable file of the ICG group, checking the number of the registers under the control of the integrated clock gating unit and the level of the registers under the control of the integrated clock gating unit to form a checking result. And the number of the registers under the control of the integrated clock gating unit is inconsistent with the number of the registers calculated by the rows and columns, or when the levels of the registers under the control of the integrated clock gating unit are not in the same level, the checking result is unqualified, and the team is prompted to rework.
Step 202: and according to the readable file of the ICG group, applying a turnover signal to ICGs of each row and column in the digital row and column register, and performing power consumption calculation based on the turnover rate of each row and column to obtain a power consumption test result.
According to the embodiment, the line data of the digital line registers are obtained through the design data and the model list, and the turning signals are applied to the specific register lines based on the line data, so that the turning rate of each line is close to that of each line under the normal working condition, the specific parameters such as the turning rate, the power consumption, the voltage drop and the like of each line which are problematic under the normal working condition are kept under the test condition, and the technical problem that the problematic line cannot be positioned due to the fact that the turning signals are directly applied to all the lines is avoided.
Referring to fig. 5, a flowchart of a method for testing a digital rank register according to the present invention is shown, and step 202 includes: wherein, the power consumption test result comprises: static power consumption and dynamic power consumption; configuring static parameters and dynamic parameters according to the readable file of the ICG group; after the VCD file is read, the digital array register is enabled to enter a standby state according to the static parameters, and static power consumption is obtained based on calculation of leakage current of the digital row-column register in the standby state; after reading the VCD file and the TWF file, applying a turnover signal to the ICG corresponding to each row according to the turnover sequence of each row and the read-write times of each row according to the dynamic parameters; and recording the turnover rate of each row and column, and calculating the dynamic power consumption of the digital row and column register based on the turnover rate of each row and column.
In this embodiment, after step 202, it includes: and carrying out EMIR analysis on the digital array register according to the dynamic power consumption.
According to the embodiment, through the readable file of the ICG group, a turnover signal is applied to the digital row-column register according to a preset turnover sequence and read-write times, so that dynamic power consumption of the digital row-column register is obtained under the condition of approaching an actual working condition, and a row of a problem of the digital row-column register under the actual working condition is positioned based on the dynamic power consumption; the direct application of the flipping signal to all rows and columns is avoided.
According to the embodiment, through the readable files of the ICG group, the overturning signals are applied to the digital row-column registers according to the preset overturning sequence and the reading and writing times, so that the digital row-column registers can perform power consumption testing under the condition of approaching the actual working condition, the overturning signals are prevented from being directly applied to all rows and columns, and the rows and columns of the digital row-column registers, which are problematic under the actual working condition, can be conveniently located subsequently.
Referring to fig. 3, a schematic structural diagram of an embodiment of a digital array register ICG sorting device according to the present invention is shown, where the digital array register testing device includes: a data acquisition module 301, a data processing unit 302 and an ICG classification unit 303.
In this embodiment, the data acquisition module 301 is configured to acquire design data of a digital rank register and a model list of the digital rank register.
The data processing unit 302 is configured to obtain, according to the design data and the model list, actual condition data of each row and column of the digital row and column register and an ICG unit list corresponding to each row and column and the corresponding ICG unit list.
In the present embodiment, the data processing unit 302 includes: the system comprises a parameter configuration unit, a static test unit, a first dynamic test unit and a second dynamic test unit; wherein, the power consumption test result comprises: static power consumption and dynamic power consumption; the parameter configuration unit is used for configuring static parameters and dynamic parameters according to the readable file of the ICG group; after the static test unit is used for reading the VCD file, the digital array register is enabled to enter a standby state according to the static parameters, and static power consumption is obtained based on calculation of leakage current of the digital row-column register in the standby state; the first dynamic test unit is used for applying a turnover signal to the ICG corresponding to each row according to the turnover sequence of each row and the read-write times of each row according to the dynamic parameters after reading the VCD file and the TWF file; the second dynamic test unit is used for recording the turnover rate of each row and column, and calculating the dynamic power consumption of the digital row and column register based on the turnover rate of each row and column.
The ICG classification unit 303 is configured to generate a readable file of the ICG group based on the actual operating condition data of each row and each column and the ICG unit list.
By adopting the embodiment of the invention, the ICG group readable file is used for power consumption evaluation and EMIR analysis of the digital array. Its advantages include: the contradiction of EMIR analysis of the Digital Array region is solved from the ICG classification perspective; the method has the advantages of simple flow, full-process automatic generation of the readable file of the ICG group, and maximum shortening of the problem feedback time.
The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present invention, and are not to be construed as limiting the scope of the invention. It should be noted that any modifications, equivalent substitutions, improvements, etc. made by those skilled in the art without departing from the spirit and principles of the present invention are intended to be included in the scope of the present invention.
Claims (10)
1. An ICG sorting method of a digital array register, comprising:
obtaining design data of a digital line register and a model list of the digital line register;
according to the design data and the model list, acquiring actual working condition data of each row and column of the digital row and column register and an ICG unit list corresponding to each row and column;
and generating the readable file of the ICG group based on the actual working condition data of each row and each column and the ICG unit list.
2. The ICG classification method of a digital array register of claim 1, wherein obtaining actual operating condition data of each row and column of the digital row and column register and an ICG cell list corresponding to each row and column according to the design data and the model list comprises:
wherein, the actual working condition data includes: the number of times of reading and writing and the overturning sequence of each row and column;
generating row and column data of the digital row and column register according to the design data and the model list;
acquiring the read-write times of each row and column in the operation of the digital row and column register from the row and column data; and determining the turning sequence of each row and column in the operation of the digital row and column register according to the row and column data, and generating an ICG unit list corresponding to each row and column.
3. The ICG sorting method of a digital array register according to claim 2, wherein determining a flip order of the respective columns and rows when the digital column and row register is operated based on the column and row data, and acquiring an ICG cell list corresponding to the respective columns and rows, comprises:
reading a hierarchical structure module list and a keyword list from the rank data;
acquiring line width data of the digital line-column register based on the hierarchical structure module list and the keyword list;
determining the turning sequence of each row and column according to the row width data; and generating the ICG unit list according to the line width data.
4. The ICG sorting method of a digital array register of claim 3, wherein generating the ICG element list from the line width data comprises:
acquiring a naming rule of the digital rank register and a word line rule of the digital rank register;
and determining a preset row and column of the digital row and column register which is turned over under the actual working condition according to the row width data, determining ICGs corresponding to the preset row and column according to the naming rule and the word line rule by a tracking method, and generating the ICG unit list.
5. The ICG sorting method of digital array registers according to claim 4, wherein the tracking method includes: forward tracking, keyword searching, and word line tracking.
6. A method for testing a digital array register, comprising:
an ICG sorting method of a digital array register according to any one of claims 1-5, generating a readable file of an ICG group;
and according to the readable file of the ICG group, applying a turnover signal to ICGs of each row and column in the digital row and column register, and performing power consumption calculation based on the turnover rate of each row and column to obtain a power consumption test result.
7. The method for testing a digital array register according to claim 6, wherein applying a flip signal to the ICGs of each row in the digital row-column register according to the readable file of the ICG group, and performing power consumption calculation based on the flip rate of each row, to obtain a power consumption test result, comprises:
wherein, the power consumption test result comprises: static power consumption and dynamic power consumption;
configuring static parameters and dynamic parameters according to the readable file of the ICG group;
after the VCD file is read, the digital array register is enabled to enter a standby state according to the static parameters, and static power consumption is obtained based on calculation of leakage current of the digital row-column register in the standby state; after reading the VCD file and the TWF file, applying a turnover signal to the ICG corresponding to each row according to the turnover sequence of each row and the read-write times of each row according to the dynamic parameters;
and recording the turnover rate of each row and column, and calculating the dynamic power consumption of the digital row and column register based on the turnover rate of each row and column.
8. The method for testing a digital array register as claimed in claim 7, wherein after recording the flip rate of each of the rows and calculating the dynamic power consumption of the digital row and column register based on the flip rate of each of the rows and columns, comprising:
and carrying out EMIR analysis on the digital array register according to the dynamic power consumption.
9. A method of testing a digital array register according to any of claims 6-8, comprising, after generating the readable file of the ICG group:
and according to the readable file of the ICG group, checking the number of the registers under the control of the integrated clock gating unit and the level of the registers under the control of the integrated clock gating unit to form a checking result.
10. An ICG sorting apparatus of a digital array register, comprising: the device comprises a data acquisition unit, a data processing unit and an ICG classification unit;
the data acquisition unit is used for acquiring design data of the digital line registers and model lists of the digital line registers;
the data processing unit is used for acquiring actual working condition data of each row and column of the digital row and column register and an ICG unit list corresponding to each row and column according to the design data and the model list;
the ICG classification unit is used for generating readable files of the ICG group based on the actual working condition data of each row and each column and the ICG unit list.
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