CN110928490B - Data storage method and device - Google Patents
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- CN110928490B CN110928490B CN201911032802.XA CN201911032802A CN110928490B CN 110928490 B CN110928490 B CN 110928490B CN 201911032802 A CN201911032802 A CN 201911032802A CN 110928490 B CN110928490 B CN 110928490B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
Abstract
The application relates to a data storage method and a data storage device, wherein a first storage position of data to be written in a first storage area is determined; if the position mapping record has the identifier of the first storage position, determining the identifier of the second storage position corresponding to the identifier of the first storage position according to the position mapping record; determining a second storage location in the second storage area according to the identifier of the second storage location; and writing the data to be written into the second storage position. In the application, the position mapping record records a hard-to-write position of the first storage area, if the position mapping record records an identifier of the first storage position, data to be written into the first storage position can be written into a second storage position of the corresponding second storage area, and the second storage position is an easy-to-write position recorded in the position mapping record.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for storing data.
Background
Magnetic Random Access Memory (MRAM) is a new type of high performance Memory Magnetic. The Static Random Access Memory (SRAM) has high-speed read and write capabilities, and the Dynamic Random Access Memory (DRAM) has high integration and can be repeatedly written in infinitely. MRAM uses magnetic moment direction in nano-pillar devices made of magnetic multilayer materials to record information, and does not need external power supply to maintain the magnetic moment and the direction of the magnetic moment, so MRAM also has non-volatility of Flash Memory.
The memory bit of an MRAM is a Magnetic Tunneling Junction (MTJ) device. As shown in fig. 1, an MTJ is made up of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material. Wherein a layer of ferromagnetic material has a fixed magnetization direction, referred to as a reference layer; the magnetization direction of another layer of ferromagnetic material, called the memory layer, can be variable, and the magnetization direction of the memory layer can be parallel or antiparallel to the magnetization direction of the reference layer. The direction of the magnetic moments of the memory and reference layers may be parallel in-plane or perpendicular to the out-of-plane direction. The MTJ is a cylindrical device of a minute size formed by etching a magnetic multilayer thin film material, and can be regarded as a variable resistor whose resistance value depends on the magnetization direction of a variable magnetization layer. The resistance is low when the magnetization directions of the memory layer and the reference layer are parallel, and the resistance is high when the magnetization directions are antiparallel.
The process of reading the MRAM is to measure the resistance of the MTJ for the corresponding address. The process of writing to the MRAM is to flip the magnetic moment of the memory layer by passing a suitable current over the MTJ at the corresponding address; as shown in fig. 1, the current direction from port 2 to port 1 from bottom to top can realize the reversal of the magnetic moments from parallel to antiparallel, and the current direction from port 1 to port 2 from top to bottom can realize the reversal of the magnetic moments from antiparallel to parallel.
As shown in fig. 2, the left side of fig. 2 is the most basic unit of memory in the memory, and includes a MTJ and a switching device, the switching device is usually a field effect transistor, the switching device is used for connecting to the word line of the chip to switch on or off the unit, and the MTJ and the switching device are connected in series and connected to the bit line and the source line. The right side of fig. 2 is a memory array formed by periodically repeating basic memory cells in rows and columns, and reading and writing voltages are applied to bit lines and source lines to read or write selected memory cells. The magnetic random access memory chip is composed of one or more memory arrays, each array or several arrays share the external circuit with corresponding function, including: the device comprises a row address decoder, a column address decoder, a read-write circuit, an address control circuit and an input/output control circuit.
MRAM achieves the operation of writing data by applying a certain voltage pulse to a memory cell to flip the magnetic moment of the memory layer of the memory cell, and reads data from the memory cell by sensing the resistance change of the memory cell through a sensitive amplifying circuit. The read circuit of the MRAM needs to detect the resistance of the memory cell component MTJ. The general method is to use some memory bits written into high resistance state or low resistance state on the chip as reference cells, and compare the resistance of the memory cells and the reference cells by the Sense Amplifier (Sense Amplifier) in the read/write circuit.
In the MRAM, when writing, the magnetic moment flipping has a certain randomness, i.e., the write pulse width required for successful flipping has a wide distribution for a given write pulse amplitude. For example: 90% of the cells may flip within 20 ns, while 10% of the cells flip between 20 ns and 100 ns. Therefore, in order to ensure that all the memory cells operate normally, the circuit design needs to apply a write pulse signal to all the memory cells for a long time, which has a great negative effect on power consumption and endurance.
Disclosure of Invention
The embodiment of the application provides a data storage method and device, which can reduce the amplitude voltage and the duration of an MRAM (magnetic random Access memory) write pulse signal, further reduce the power consumption of a memory and improve the durability of the memory.
In one aspect, an embodiment of the present application provides a data storage method, including:
determining a first storage position of data to be written in a first storage area;
if the position mapping record has the identifier of the first storage position, determining the identifier of the second storage position corresponding to the identifier of the first storage position according to the position mapping record;
determining a second storage location in the second storage area according to the identifier of the second storage location;
and writing the data to be written into the second storage position.
On the other hand, an embodiment of the present application provides a data storage device, including:
the first determining module is used for determining a first storage position of data to be written in a first storage area;
the second determining module is used for determining the identifier of the second storage position corresponding to the identifier of the first storage position according to the position mapping record if the identifier of the first storage position exists in the position mapping record;
a third determining module, configured to determine, according to the identifier of the second storage location, a second storage location located in the second storage area;
and the storage module is used for writing the data to be written into the second storage position.
The data storage method and the data storage device provided by the embodiment of the application have the following beneficial effects:
determining a first storage position of data to be written in a first storage area; if the position mapping record has the identifier of the first storage position, determining the identifier of the second storage position corresponding to the identifier of the first storage position according to the position mapping record; determining a second storage location in the second storage area according to the identifier of the second storage location; and writing the data to be written into the second storage position. In the application, the position mapping record records a hard-to-write position of the first storage area, when the memory performs write operation, if the position mapping record has an identifier of the first storage position, data to be written into the first storage position can be written into a second storage position of the corresponding second storage area, and the second storage position is the easy-to-write position recorded in the position mapping record, so that the voltage amplitude and time of a write pulse required by the memory for storing the data can be reduced, the power consumption of the memory can be reduced, and the durability can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a magnetic tunnel junction device provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of a memory array and a memory unit thereof according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of an application scenario provided in an embodiment of the present application;
fig. 4 is a schematic flowchart of a data storage method according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an internal structure of a memory chip according to an embodiment of the present disclosure;
FIG. 6 is a Shmoo plot of a memory write operation provided by an embodiment of the present application;
FIG. 7 is a schematic structural diagram of a data storage device according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a redundant storage array architecture according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Referring to fig. 3, fig. 3 is a schematic diagram of an application scenario provided in an embodiment of the present application, and includes a memory 301, where the memory 301 includes a first storage area 3011, a second storage area 3012, and a location mapping record 3013.
When the memory 301 stores data, the first storage position of the data to be written in the first storage area 3011 is determined; if the location mapping record 3013 has the identifier of the first storage location, the memory 301 determines, according to the location mapping record 3013, the identifier of the second storage location corresponding to the identifier of the first storage location; the memory 301 determines a second storage location located in the second storage area 3012 according to the identifier of the second storage location, and writes the data to be written into the second storage location.
In this embodiment, the position mapping record 3013 records a hard-to-write position of the first storage region 3011, and when the memory 301 performs a write operation, if the position mapping record 3013 has an identifier of the first storage position, data to be written into the first storage position may be written into a second storage position of the corresponding second storage region 3012, where the second storage position is the easy-to-write position recorded by the position mapping record 3013, so that the voltage amplitude and time of a write pulse required when the memory 301 stores data may be reduced, thereby reducing power consumption of the memory 301 and improving durability.
Alternatively, the memory 301 may be a resistive memory such as an SRAM, a DRAM, or an MRAM, a PCRAM, or an RRAM, and a memory that performs a write operation by applying a voltage to a memory cell.
The following describes a specific embodiment of a data storage method of the present application, and fig. 4 is a flowchart of a data storage method provided in the embodiment of the present application, and the present specification provides the method operation steps as in the embodiment or the flowchart, but may include more or less operation steps based on conventional or non-inventive labor. The order of steps recited in the embodiments is merely one manner of performing the steps in a multitude of orders and does not represent the only order of execution. In practice, the system or server product may be implemented in a sequential or parallel manner (e.g., parallel processor or multi-threaded environment) according to the embodiments or methods shown in the drawings. Specifically, as shown in fig. 4, the method may include:
s401: the memory determines a first storage location of data to be written in a first storage area.
In the embodiment of the application, an address control module of a memory determines a first storage position in a first storage area where data to be written is to be written according to a received storage address sent by an external circuit.
Optionally, the first storage area may be a storage array of a memory, the storage array including a plurality of storage units; the first storage location may be one of a number of storage units.
Alternatively, the memory may be an MRAM; the first storage location may include an MTJ and a field effect transistor.
S403: and if the position mapping record has the identifier of the first storage position, the memory determines the identifier of the second storage position corresponding to the identifier of the first storage position according to the position mapping record.
In the embodiment of the application, the method further comprises the step of determining a position mapping record; the method comprises the following steps:
determining a first set of storage locations; wherein each storage location in the first set of storage locations is a storage location in the first storage area; determining a second set of storage locations, wherein each storage location in the second set of storage locations is a storage location in the second storage area; the number of storage locations in the second set of storage locations is greater than the number of storage locations in the first set of storage locations; determining a third set of storage locations from the second set of storage locations based on the number of storage locations in the first set of storage locations; the number of storage locations in the third set of storage locations is equal to the number of storage locations in the first set of storage locations; and correspondingly associating the identification of the storage position in the first storage position set with the identification of the storage position in the third storage position set one by one to generate a position mapping record.
In the embodiment of the present application, a ratio of the number of storage locations in the second storage area to the number of storage locations in the first storage area may be any value in an interval from 0.01 to 0.2.
Optionally, the second storage region and the first storage region are adjacently disposed on the same chip.
In an alternative embodiment of determining the first set of storage locations or determining the second set of storage locations, an external testing machine may be used to determine the first set of storage locations or determine the second set of storage locations.
In an alternative embodiment of determining the first set of storage locations or determining the second set of storage locations, the first set of storage locations or the second set of storage locations may be determined by a built-In Self Test circuit (built-In Self Test) of the memory.
Specifically, determining the first set of storage locations may include: writing first preset data into each storage position in the first storage area based on preset pulse duration and pulse amplitude; reading out the data in each storage location; and determining a first storage position set according to the matching degree of the data in each storage position and the first preset data.
Specifically, determining the second set of storage locations may include: writing second preset data into each storage position in the second storage area based on preset pulse duration and pulse amplitude; reading out the data in each storage location; and determining a second storage position set according to the matching degree of the data in each storage position and second preset data.
Referring to fig. 5, fig. 5 is a schematic diagram of an internal structure of a memory chip provided in an embodiment of the present application, including a memory array (a first memory region) and a redundant memory array (a second memory region). Referring to fig. 6, fig. 6 is a Shmoo diagram of a memory write operation according to an embodiment of the present application. Suppose the memory array of the memory comprises 107The write error rate of the memory array for each memory location depends on the pulse duration T and the pulse amplitude V of the write pulse. Taking the write pulse duration T1 as an example, the write pulse amplitude is greater than or equal to V8 to ensure that all storage locations in the storage array operate without errors, and the write error rate increases as the pulse amplitude decreases. When the pulse amplitude drops to V1, there is 106Fails to successfully flip the memory location at the voltage amplitude, the 10 is turned off6Is determined as a hard-to-write position (first storage position). This application is made by combining 106Replacement of hard-to-write locations in redundant memory arraysThe writable location (second storage location) can be written at the pulse amplitude V1, so that the memory can operate at a lower writing voltage, which helps to reduce the writing error rate and improve the endurance of the memory.
Based on the above example, a specific embodiment of determining the first set of storage locations (set of hard-to-write locations) is described below. The write pulses are provided with adjustable pulse amplitudes and pulse durations by a test mode of an external tester or an internal self-test circuit, the range of adjustable pulse amplitudes may be V0-V9 as shown in FIG. 6, and the range of adjustable pulse durations may be T0-T9 as shown in FIG. 6.
Firstly, initializing data of all storage positions in a storage array to be 0 by adopting an external magnetic field or adopting write operation, writing the data of all the storage positions to be 1 by configuring a write pulse duration T0 and a pulse amplitude Vn, reading the data of all the storage positions, and determining the storage positions of which the read data is not 1 as the hard-to-write positions; next, the data in all the storage positions are written to 0, the data in all the storage positions are read, and the storage position where the read data is not 0 is determined as a hard-to-write position. And if any one of the two tests is determined as the position difficult to write, determining the storage position as the position difficult to write, determining the number of all the positions difficult to write, and storing the identification of all the positions difficult to write. Alternatively, the identification may be an address of a hard-to-write location.
In practical operation, the above operation steps of write 0, read, write 1 and read may be repeated multiple times, and the storage location in the storage array is determined to be a hard-to-write location when the read data and the write data do not match each other any time. If the number of determined hard-to-write positions is far less than the capacity of the redundant memory array, reducing the pulse amplitude to Vn-1The test is repeated and the number and address of the hard-to-write locations are temporarily recorded. If the number of the determined hard-to-write positions is larger than the capacity of the redundant storage array, increasing the pulse amplitude to be Vn+1The test is repeated and the number and address of the hard-to-write locations are temporarily recorded.
The specific embodiment of determining the second set of storage locations (set of writable locations) is the same as the embodiment of determining the first set of storage locations described above. Initializing data of all storage positions in the storage array to be 0 by adopting an external magnetic field or writing operation, writing the data of all the storage positions to be 1 by configuring a writing pulse duration T0 and a pulse amplitude Vn, reading the data of all the storage positions, and determining the storage position of which the read data is 1 as a quasi-easy-to-write position; secondly, writing the data of all the storage positions into 0, reading the data of all the storage positions, and determining the storage position of which the read data is 0 as a quasi-easy-to-write position; and determining the storage positions determined as the quasi-easy-to-write positions in the two tests as the easy-to-write positions, and determining the number of the easy-to-write positions.
In practical operation, the above operation steps of write 0, read, write 1 and read may be repeated many times, and the storage location in the storage array is determined as a writable location only when the storage location is determined as a quasi-writable location in each test. If the ratio of the number of the quasi-easy-to-write positions to the capacity of the redundant storage array exceeds a preset ratio, reducing the pulse amplitude to Vn-1The test is repeated and the number and address of the quasi-writable locations are temporarily recorded. If the ratio of the number of the quasi-easy-to-write positions to the capacity of the redundant storage array is smaller than the preset ratio, increasing the pulse amplitude to be Vn+1The test is repeated and the number and address of the quasi-writable locations are temporarily recorded.
In an embodiment of the present application, the determining the criterion of the first storage location set may include: and screening the number of the first storage position sets through testing until the proportion of the number of the first storage position sets to the number of the first storage areas is within the interval of 0-0.1, and determining the first storage position sets.
In an embodiment of the present application, the determining the criterion of the second storage location set may include: and screening out the number of the second storage position sets which is greater than or equal to the number of the first storage position sets through testing.
Based on the above example description, the memory array includes 107A storage location, a redundant storage array comprising 106A storage location. When the pulse duration of the write pulse is set to T1, the pulse amplitude is set to V2,the number of hard-to-write locations in the memory array is 105The number of the easy-to-write positions in the redundant storage array is 9x105At this point it may be achieved that all the hard-to-write locations are replaced by easy-to-write locations, but the utilization of the redundant storage array is only 1/9. In actual implementation, the range of the pulse amplitude can be determined more accurately according to the Shmoo diagram of the specific memory, so that the optimal difficult-to-write position and easy-to-write position can be found by adjusting the pulse amplitude as few as possible, and the utilization rate of the redundant memory array is improved.
In an alternative embodiment after determining the location mapping record, the method may include: the first set of storage locations, the second set of storage locations, and the location mapping record are stored in a register, which may be a non-volatile register, in an address control module of the memory. The address control module may further include an address comparison module that compares the received external address with a first storage location set stored in the register, and if the external address is in the first storage location set, maps the internal physical address to a corresponding second storage location according to the location mapping record, and replaces an actually visited location with the second storage location in the second storage area.
Another optional implementation after determining the location mapping record may include: the first storage position set, the second storage position set and the position mapping record are temporarily stored in an external testing machine for caching, and a mapping relation is defined in an internal circuit of a memory chip by a one-time programming method, so that the mapping operation can be omitted in the process of performing read-write operation on the memory, and data originally written into the first storage position can be directly written into the corresponding second storage position.
S405: the memory determines a second storage location in the second storage area based on the identification of the second storage location.
S407: the memory writes the data to be written to the second storage location.
In an embodiment that an optional memory determines a second storage location in a second storage area according to an identifier of the second storage location, an address control module of the memory determines that the identifier of the first storage location exists in a location mapping record, and determines an identifier of the second storage location corresponding to the identifier of the first storage location according to the location mapping record, the address control module sends the identifier of the second storage location to a row address decoding circuit and a column address decoding circuit of the second storage area to determine the second storage location, and the memory writes data to be written into the second storage location.
In the embodiment of the present application, the method further includes a step of reading data, including: determining that the position to be read is located at a third storage position of the first storage area; if the position mapping record has the identifier of the third storage position, determining the identifier of the fourth storage position corresponding to the identifier of the third storage position according to the position mapping record; determining a fourth storage position in the second storage area according to the identifier of the fourth storage position; the fourth storage location is determined to be the target read location and data is read from the target read location. In this application, the step of reading data is the same as the method of storing data, the third storage location may correspond to the first storage location, and the fourth storage location may correspond to the second storage location, please refer to steps S401 to S407 and the optional implementation manner thereof, which are not described herein again.
An embodiment of the present application further provides a data storage method, and fig. 7 is a schematic structural diagram of a data storage device provided in the embodiment of the present application, and as shown in fig. 7, the device includes:
a first determining module 701, configured to determine a first storage location of data to be written in a first storage area;
a second determining module 702, configured to determine, according to the position mapping record, an identifier of a second storage location corresponding to the identifier of the first storage location if the identifier of the first storage location exists in the position mapping record;
a third determining module 703, configured to determine, according to the identifier of the second storage location, the second storage location in the second storage area;
and the storage module 704 is used for writing the data to be written into the second storage position.
The device and method embodiments in the embodiments of the present application are based on the same application concept.
The redundant storage array framework provided by the application can independently carry out address decoding and write-in reading on the redundant storage array, can replace the difficult-to-write position in the storage array with the easy-to-write position in the redundant storage array, and has the characteristics of high utilization rate and flexible configuration. Referring to fig. 8, fig. 8 is a schematic diagram of a redundant memory array architecture according to an embodiment of the present application. The redundant storage array architecture can be mirrored side-to-side or top-to-bottom as shown in FIG. 8, forming a scalable capacity memory.
As can be seen from the above embodiments of the data storage method and apparatus provided by the present application, in the present application, a first storage location of data to be written in a first storage area is determined; if the position mapping record has the identifier of the first storage position, determining the identifier of the second storage position corresponding to the identifier of the first storage position according to the position mapping record; determining a second storage location in the second storage area according to the identifier of the second storage location; and writing the data to be written into the second storage position. In the application, the position mapping record records a hard-to-write position of the first storage area, and when the memory performs a write operation, if the position mapping record has an identifier of the first storage position, data to be written into the first storage position can be written into a second storage position of the corresponding second storage area, and the second storage position is the easy-to-write position recorded in the position mapping record.
It should be noted that: the sequence of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. And specific embodiments thereof have been described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to part of the description of the method embodiment for relevant points.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A method for storing data, comprising:
determining a first storage position of data to be written in a first storage area; the first storage area is a storage array of a memory;
if the identifier of the first storage position exists in the position mapping record, determining the identifier of a second storage position corresponding to the identifier of the first storage position according to the position mapping record; the position mapping record comprises a first storage position set and a second storage position set, and the first storage position set and the second storage position set correspond to each other one by one; the first storage position set and the second storage position set are determined based on the reading result, and preset data are written in and read out based on preset pulse duration and pulse amplitude;
determining a second storage position in a second storage area according to the identifier of the second storage position; the second storage area is a redundant storage array of the memory;
and writing the data to be written into the second storage position.
2. The method of claim 1, further comprising the step of reading data;
the reading data comprises:
determining that the position to be read is located at a third storage position of the first storage area;
if the identifier of the third storage position exists in the position mapping record, determining the identifier of a fourth storage position corresponding to the identifier of the third storage position according to the position mapping record;
determining a fourth storage location in the second storage area according to the identifier of the fourth storage location;
determining the fourth storage location as a target read location and reading data from the target read location.
3. The method of claim 1, further comprising the step of determining the location mapping record;
the determining the location mapping record comprises:
determining a first set of storage locations; wherein each storage location in the first set of storage locations is a storage location in the first storage area;
determining a second set of storage locations, wherein each storage location in the second set of storage locations is a storage location in the second storage area; the number of storage locations in the second set of storage locations is greater than the number of storage locations in the first set of storage locations;
determining a third set of storage locations from the second set of storage locations based on the number of storage locations in the first set of storage locations; the number of storage locations in the third set of storage locations is equal to the number of storage locations in the first set of storage locations;
and correspondingly associating the identification of the storage position in the first storage position set with the identification of the storage position in the third storage position set one by one to generate the position mapping record.
4. The method of claim 3, wherein determining the first set of storage locations comprises:
writing first preset data into each storage position in the first storage area based on preset pulse duration and pulse amplitude;
reading out the data in each of the storage locations;
and determining the first storage position set according to the matching degree of the data in each storage position and first preset data.
5. The method of claim 3, wherein determining the second set of storage locations comprises:
writing second preset data into each storage position in the second storage area based on preset pulse duration and pulse amplitude;
reading out the data in each of the storage locations;
and determining the second storage position set according to the matching degree of the data in each storage position and second preset data.
6. The method of claim 1,
the ratio of the number of the storage positions of the second storage area to the number of the storage positions of the first storage area is a preset ratio.
7. An apparatus for storing data, comprising:
the first determining module is used for determining a first storage position of data to be written in a first storage area; the first storage area is a storage array of a memory;
a second determining module, configured to determine, according to a position mapping record, an identifier of a second storage location corresponding to the identifier of the first storage location if the identifier of the first storage location exists in the position mapping record; the position mapping record comprises a first storage position set and a second storage position set, and the first storage position set and the second storage position set correspond to each other one by one; the first storage position set and the second storage position set are determined based on the reading result, and preset data are written in and read out based on preset pulse duration and pulse amplitude;
a third determining module, configured to determine, according to the identifier of the second storage location, a second storage location located in a second storage area; the second storage area is a redundant storage array of the memory;
and the storage module is used for writing the data to be written into the second storage position.
8. The apparatus of claim 7, further comprising a reading module;
the first determining module is further configured to determine that the position to be read is located at a third storage position of the first storage area;
the second determining module is further configured to determine, according to the position mapping record, an identifier of a fourth storage location corresponding to the identifier of the third storage location if the identifier of the third storage location exists in the position mapping record;
the third determining module is further configured to determine a fourth storage location located in the second storage area according to the identifier of the fourth storage location; determining the fourth storage location as a target read location;
the reading module is used for reading data in the target reading position.
9. The apparatus of claim 7, further comprising a fourth determination module;
the fourth determining module is configured to determine the first set of storage locations; wherein each storage location in the first set of storage locations is a storage location in the first storage area;
the fourth determining module is further configured to determine a second storage location set, where each storage location in the second storage location set is a storage location in the second storage area; the number of storage locations in the second set of storage locations is greater than the number of storage locations in the first set of storage locations;
the fourth determining module is further configured to determine a third set of storage locations from the second set of storage locations based on the number of storage locations in the first set of storage locations; the number of storage locations in the third set of storage locations is equal to the number of storage locations in the first set of storage locations;
the fourth determining module is further configured to associate the identifier of the storage location in the first storage location set with the identifier of the storage location in the third storage location set in a one-to-one correspondence manner, and generate the location mapping record.
10. The apparatus of claim 9,
the fourth determining module is further configured to write first preset data into each storage location in the first storage area based on a preset pulse duration and a preset pulse amplitude; reading out the data in each of the storage locations; determining the first storage position set according to the matching degree of the data in each storage position and first preset data;
the fourth determining module is further configured to write second preset data into each storage location in the second storage area based on a preset pulse duration and a preset pulse amplitude; reading out the data in each of the storage locations; and determining the second storage position set according to the matching degree of the data in each storage position and second preset data.
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