CN108109668B

CN108109668B - Magnetic memory testing method and device, storage medium and electronic device

Info

Publication number: CN108109668B
Application number: CN201711215952.5A
Authority: CN
Inventors: 何世坤
Original assignee: CETHIK Group Ltd; Hikstor Technology Co Ltd
Current assignee: CETHIK Group Ltd; Hikstor Technology Co Ltd
Priority date: 2017-11-28
Filing date: 2017-11-28
Publication date: 2020-12-11
Anticipated expiration: 2037-11-28
Also published as: CN108109668A

Abstract

The invention provides a method and a device for testing a magnetic memory, a storage medium and an electronic device, wherein the method comprises the following steps: simultaneously applying a first excitation to all the magnetic memories, and performing a write operation of writing data in all the magnetic memories, wherein the excitation value of the first excitation is greater than a predetermined threshold value, and each of the magnetic memories is placed in a same state; after the write operation is completed, simultaneously applying a second stimulus to all magnetic memories, wherein a stimulus value of the second stimulus is less than the predetermined threshold; reading the data states in the respective magnetic memories after applying the second stimulus; read disturbances of the magnetic memories are determined based on the read data states in the respective magnetic memories. The invention solves the problem of long time consumption for testing the magnetic memory in the related technology, thereby achieving the effect of reducing the testing time of the magnetic memory.

Description

Magnetic memory testing method and device, storage medium and electronic device

Technical Field

The invention relates to a magnetic memory testing technology, in particular to a magnetic memory testing method, a magnetic memory testing device, a magnetic memory testing storage medium and an electronic device.

Background

Magnetic memories based on the Tunneling Magneto-Resistance (TMR) effect, such as Magnetic Tunneling Junction (MTJ) devices, are composed of two Magnetic layers and a dielectric layer between the Magnetic layers. The magnetization orientation of the first magnetic layer (fixed layer) is fixed, and the magnetization orientation of the second magnetic layer (free layer) can be changed through a magnetic field or current, so that the two magnetic layers are in parallel or antiparallel states, and can be used for storing information corresponding to a high resistance state and a low resistance state.

The Memory using the current to change the MTJ state is a Magnetic Random Access Memory (ST-MRAM), which is a novel Memory with great potential. The memory has the advantages of simple circuit design, high read-write speed, unlimited erasing and writing and the like, and has the greatest advantage of non-volatility (power-off data is not lost) compared with the traditional memory such as a Dynamic random access memory (DRAM for short). FIG. 1 is a schematic diagram of an MRAM data state in which the magnetic orientation of the free layer (magnetic recording layer) can be manipulated by an external field (H) or a write current (I). When the free layer magnetization direction and the fixed layer are parallel or antiparallel, it can correspond to data 0 or 1, respectively. The data retention time of MRAM is an indicator of product performance that must be accurately measured. Data retention time needs to be determined by device MTJ and chip testing.

In the aspect of testing the MTJ device, the dependence of the MTJ writing probability along with the writing current density or the magnetic field dependence of the magnetic flip probability can be calculated, and the traditional method can only test a single device each time and consumes much time when statistical data are to be acquired. Taking the relationship between the magnetic field flipping probability and the magnitude of the external magnetic field as an example, about 200 resistance-to-magnetic field change curves need to be tested repeatedly, each curve takes about 3 seconds, that is, the testing time of 1 device is about 10 minutes.

In chip test, together with MTJ array and address decoder, it can write information one by one quickly and then accelerate data loss and test by introducing external environment change, and the common methods are temperature acceleration method and magnetic field acceleration method. The temperature acceleration method needs to bake the sample wafer at different temperatures, and the data retention time of the product is calculated through the retention degree of the test data. The disadvantage of this method is that it requires an assumption of the temperature dependence of the stability factor with unknown error. The magnetic field acceleration method needs to be tested under different external magnetic fields to calculate the thermal stability. The disadvantage of this method is the required external magnetic field test equipment.

Aiming at the problem that the testing method of the magnetic memory in the related technology is long in time consumption, an effective solution is not provided at present.

Disclosure of Invention

The embodiment of the invention provides a method and a device for testing a magnetic memory, a storage medium and an electronic device, which are used for at least solving the problem that the method for testing the magnetic memory in the related art is long in time consumption.

According to an embodiment of the present invention, there is provided a method of testing a magnetic memory, including: simultaneously applying a first excitation to all the magnetic memories, and performing a write operation of writing data in all the magnetic memories, wherein the excitation value of the first excitation is greater than a predetermined threshold value, and each of the magnetic memories is placed in a same state; after the write operation is completed, simultaneously applying a second stimulus to all magnetic memories, wherein a stimulus value of the second stimulus is less than the predetermined threshold; reading the data states in the respective magnetic memories after applying the second stimulus; read disturbances of the magnetic memories are determined based on the read data states in the respective magnetic memories.

Optionally, determining a read disturbance of the magnetic memories from the read data states in the respective magnetic memories comprises: determining the number of the magnetic memories with changed states according to the read data states in the magnetic memories; the ratio of the number of magnetic memories in which the state changes to the number of all magnetic memories is used to determine the read disturbance of the magnetic memories.

Optionally, after determining a read disturbance of the magnetic memory, the method further comprises: determining a thermal stability factor of the magnetic memory by fitting the read disturbance and the second excitation of the magnetic memory.

Optionally, after reading the data states in the respective magnetic memories separately, the method further comprises: repeating the operations of applying the first stimulus, applying the second stimulus, and reading the data state in the respective magnetic memories; a predetermined magnetic memory read disturb is determined based on repeatedly reading data states in the respective magnetic memories.

Optionally, determining a read disturbance of a predetermined magnetic memory of all the magnetic memories according to the data state in the respective magnetic memories repeatedly read comprises: determining a total number of times that the data state in the predetermined magnetic memory is repeatedly read, and determining a number of times that the state of the predetermined magnetic memory is changed according to the repeatedly read data state in the predetermined magnetic memory; determining a read disturbance of the predetermined magnetic memory using a ratio of the number of times the state of the predetermined magnetic memory changes to the total number of times the data state in the predetermined magnetic memory is repeatedly read.

Optionally, after determining the read disturbance of the predetermined magnetic memory, the method further comprises: determining a thermal stability factor of the predetermined magnetic memory by fitting the read disturbance and the second excitation of the predetermined magnetic memory.

According to another embodiment of the present invention, there is provided a test apparatus of a magnetic memory including: the first processing module is used for applying a first excitation to all the magnetic memories and executing write operation of writing data in all the magnetic memories, wherein the excitation value of the first excitation is larger than a preset threshold value; a second processing module for applying a second stimulus to all magnetic memories after the write operation is completed, wherein a stimulus value of the second stimulus is less than the predetermined threshold; a read module for reading the data states in the respective magnetic memories after the second stimulus is applied; and the determining module is used for determining the read disturbance of the magnetic memories according to the read data states in the magnetic memories.

Optionally, the determining module includes: a first determination unit for determining the number of magnetic memories whose states change according to the data states read from the respective magnetic memories; a second determination unit for determining read disturbance of the magnetic memories using a ratio of the number of magnetic memories whose state changes to the number of all magnetic memories.

According to another embodiment of the present invention, there is provided a test apparatus of a magnetic memory including: an apparatus for testing a magnetic memory, comprising: the device comprises a cross dot matrix array, a test electrode array and a switch group, wherein the cross dot matrix array comprises a bit line BL group and a source line SL group, the BL group comprises more than two BL, the SL group comprises more than two SL, and a magnetic memory is connected between each BL in the BL group and each SL in the SL group; the test electrode array comprises more than two first electrodes, and each first electrode is connected with each BL or each SL in the cross dot matrix array one by one; the switch group comprises a first switch, a second switch, a third switch array and a fourth switch array, wherein one end of the first switch is connected to a test instrument for testing each magnetic memory, and the other end of the first switch is provided with more than two connection points which are in one-to-one correspondence with each BL in the BL group; one end of the second switch is connected to the test instrument, and the other end of the second switch is provided with more than two connection points which are in one-to-one correspondence with the SLs in the SL group; the third switch array comprises more than two third switches which are in one-to-one correspondence with each BL in the BL group, one end of each third switch is connected to the test instrument, and the other end of each third switch is connected to the BL; the fourth switch array comprises more than two fourth switches which are in one-to-one correspondence with the SLs in the SL group, one end of each fourth switch is connected to the test instrument, and the other end of each fourth switch is connected to the SL.

Optionally, the magnetic memory is divided into a magnetic memory array of n1 rows and n2 columns, the number of BLs included in the BL group is n1, and the number of SLs included in the SL group is n2, wherein: each BL is respectively connected with the top electrode of each magnetic memory in each row of magnetic memories, and each SL is respectively connected with the bottom electrode of each magnetic memory in each column of magnetic memories.

Optionally, the apparatus further includes a transistor group and a word line WL group, the WL group includes n2 WLs, the test electrode array further includes n2 second electrodes, each of the second electrodes is connected to each WL in the WL group one by one, the switch group further includes a fifth switch and a sixth switch array, one end of the fifth switch is connected to the test instrument, the other end of the fifth switch is provided with n2 connection points corresponding to the n2 WLs one by one, the sixth switch array includes more than two sixth switches corresponding to the n2 WLs one by one, and each sixth switch has one end connected to the test instrument and the other end connected to the WL, wherein each transistor in the transistor group is respectively arranged corresponding to each magnetic memory one by one, each transistor includes three pins, wherein the first pin and the second pin are respectively used for connecting the magnetic memory and the corresponding SL, the third pin is connected with WL, and each WL is respectively connected with a column of magnetic memories.

Optionally, the test meter is for: when the switch group is in a first connection state, applying a first excitation to all the magnetic memories to be tested, wherein the excitation value of the first excitation is greater than a preset threshold value; the first connection state is that the first switches are connected with the BL in the BL group in a one-to-one correspondence manner, the second switches are connected with the SL in the SL group in a one-to-one correspondence manner, all the BL in the BL group are at the same electric potential, all the SL in the SL group are at the same electric potential, and all the magnetic memories in the cross dot matrix array are in a conduction state; after the first stimulus is applied, applying a second stimulus to all memories to be tested, wherein the stimulus value of the second stimulus is smaller than the predetermined threshold value; after the second excitation is applied, the switch group is switched to a second connection state, the data states in the magnetic memories are respectively read, wherein the second connection state is that each third switch in the third switch array is connected with each BL in the BL group in a one-to-one correspondence mode, each fourth switch in the fourth switch array is connected with each SL in the SL group in a one-to-one correspondence mode, and the conduction state of each magnetic memory in the cross dot matrix array is controlled by controlling the conduction state of each switch in the third switch array and the fourth switch array.

Optionally, the test meter is for: when the switch group is in a third connection state, applying a first excitation to all the magnetic memories to be tested, wherein the excitation value of the first excitation is greater than a preset threshold value, the third connection state is the third connection state, the first switches are connected with the BL in the BL group in a one-to-one correspondence manner, the second switches are connected with the SL in the SL group in a one-to-one correspondence manner, the fifth switches are connected with the WL in the WL group in a one-to-one correspondence manner, all the BL in the BL group, all the SL in the SL group and all the WL in the WL group in a one-to-one correspondence manner, and all the magnetic memories in the cross dot matrix array are in a conduction state; after the first stimulus is applied, applying a second stimulus to all memories to be tested, wherein the stimulus value of the second stimulus is smaller than the predetermined threshold value; after the second excitation is applied and when the switch group is in a fourth connection state, reading the data state in each magnetic memory respectively, wherein the fourth connection state is that each third switch in the third switch array is connected with each BL in the BL group in a one-to-one correspondence manner, each fourth switch in the fourth switch array is connected with each SL in the SL group in a one-to-one correspondence manner, each sixth switch in the sixth switch array is connected with each WL in the WL group in a one-to-one correspondence manner, and the conduction state of each magnetic memory in the cross-point array is controlled by controlling the conduction state of each switch in the third switch array, the fourth switch array and the sixth switch array.

According to yet another embodiment of the present invention, there is also provided a storage medium including a stored program, wherein the program performs any one of the above methods when executed.

According to yet another embodiment of the present invention, there is also provided an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the method of any one of the above by the computer program.

By the invention, the magnetic memories are simultaneously excited to change the data storage state, and then the data of the magnetic memories are respectively read to change the state, so that the simultaneous excitation and time-sharing reading of all the magnetic memories can be realized. Because the excitation time required by a single magnetic memory is far longer than the reading time, the problem that the magnetic memory testing method in the related technology consumes long time can be solved, and the effect of reducing the magnetic memory testing time is achieved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

FIG. 1 is a schematic diagram of an MRAM data state according to an embodiment of the invention;

FIG. 2 is a schematic diagram of an early MTJ magnetic orientation according to an embodiment of the present invention;

FIG. 3 is a flow chart of a method of testing a magnetic memory according to an alternative embodiment of the present invention;

FIG. 4Is an ln (P) and write voltage (V) according to an alternative embodiment of the invention_read/V_c) Is a linear relation diagram;

FIG. 5 is a block diagram of a first apparatus for testing a magnetic memory according to an alternative embodiment of the present invention;

FIG. 6 is a block diagram of a second type of magnetic memory testing apparatus, in accordance with an alternative embodiment of the present invention;

FIG. 7 is a flow chart of a method for testing a magnetic memory in accordance with an alternative embodiment of the present invention;

FIG. 8 is a block diagram of a third apparatus for testing a magnetic memory according to an alternative embodiment of the present invention.

Detailed Description

Early magnetic memories, such as MTJs, were magnetically oriented in-plane with thin films (as shown in fig. 2), and nonvolatile properties were introduced by shape anisotropy. The MTJ bit is elliptical or rectangular, and the data retention time for switching between the parallel and antiparallel states depends on the difference in demagnetization energy of the free layer along the in-plane short side direction and the in-plane long side direction, i.e., the potential barrier between the free layer along the A or B orientation in FIG. 2. This design corresponds to a larger memory cell size. Therefore, high density MRAM requires the use of perpendicular magnetization materials, such as MgO | CFB | Ta system. Wherein, the covering layer is metal. The transition between the two states of the perpendicular magnetic tunnel junction P-MTJ requires overcoming a potential barrier as an energy difference between the perpendicular magnetization and the in-plane magnetization of the free layer (top left diagram in fig. 2). The retention time of the data can be calculated based on the thermal activation theory as: τ ═ τ₀ exp(Δ_T) In which τ is₀＝1/f₀Depending on the material characteristic frequency. The data retention time is thus determined by the thermal stability factor Δ (thermal stability), i.e. the ratio between the energy barrier and the thermal activation energy between the two states mentioned above (0 or 1, corresponding to the flat state and the antiparallel state respectively): Δ ═ E_b/k_BAnd T. Wherein T is temperature, k_BBoltzmann constant. Wherein E_b＝H_kM_sV/2, proportional to the equivalent anisotropy field H_kSaturation magnetization M_sAnd a magnetic recording layer volume V ═ t × S. By testing the raw magnetic film, M can be obtained_sAnd H_KIt is estimated, however, that there may be large differences in the characteristic parameters and films when the materials are processed into devices. E.g. H_KDirectly related to the demagnetization factor of the material, wherein the demagnetization factor is determined by the geometric shape, and the H corresponding to different MTJs is measured at the nanoscale_KThis will be a large difference. Therefore, the data retention time needs to be determined by the device MTJ test.

On the other hand, the chip must minimize read disturb (e.g., read a day with a disturb probability P < 10)^-6) Thus, determining read disturb requires long testing at low voltages, and single magnetic memory devices (e.g., single MTJs) or chip-level testing for device-by-device or memory cell read operations is time consuming to obtain statistical cell information (large number of device or bit results).

The invention designs a set of magnetic storage testing device and a corresponding magnetic storage testing method, and can simultaneously conduct the states of all magnetic storage devices (such as MTJ) in a matrix to be tested through the design of a switch matrix. Testing the magnetic memory state is very fast (on the order of 10 ns) due to the long actuation time (minutes or longer). The method solves the problem that the data storage time and the read disturbance probability test time consumption are caused in the traditional test method. Compared with the traditional method, the method has the advantages that: (1) the measurement is quick: by the method, all the single device thermal disturbance and thermal stability factors in one array can be obtained, and the statistical information of the thermal disturbance and the thermal stability factors in the array can also be obtained. Compared with a device array with independent testing electrodes for each MTJ and a chip with an address decoder, the testing efficiency is remarkably improved. With an array size of N, (e.g., typically N may be between 100 and 10000, with a read state time much less than the actuation time, corresponding efficiency improvements of 10 to 10³Multiple). (2) The related parameters can be obtained by using standard semiconductor electrical parameter testing equipment without additional instruments and equipment. (3) The method is still applicable to different temperatures and different magnetic fields.

The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

The key point in the embodiment of the invention is that aiming at the problem that the testing method of the magnetic memory in the related technology consumes long time, the testing device of the magnetic memory provided by the invention can reduce the testing time of the magnetic memory. The invention is illustrated below with reference to examples:

in an embodiment of the present invention, a method for testing a magnetic memory is provided, and fig. 3 is a flowchart of a method for testing a magnetic memory according to an embodiment of the present invention, as shown in fig. 3, the method includes the following steps:

step S302, applying a first excitation to all the magnetic memories, and executing write operation of writing data in all the magnetic memories, wherein the excitation value of the first excitation is larger than a preset threshold value;

step S304, after the write operation is completed, applying a second excitation to all the magnetic memories, wherein the excitation value of the second excitation is smaller than the predetermined threshold value;

step S306, after the second excitation is applied, reading the data state in each magnetic memory respectively;

step S308, determining read disturbance of the magnetic memories according to the read data states in the magnetic memories.

By the above-described embodiments, simultaneous excitation and time-shared reading of all the magnetic memories can be achieved since excitation is applied to the magnetic memories simultaneously to change their data storage states, and then the data of the magnetic memories are read separately to change the states. Because the excitation time required by a single magnetic memory is far longer than the reading time, the problem that the magnetic memory testing method in the related technology consumes long time can be solved, and the effect of reducing the magnetic memory testing time is achieved.

In an alternative embodiment, determining a read disturbance for the magnetic memories based on the data states read from the respective magnetic memories comprises: determining the number of the magnetic memories with changed states according to the read data states in the magnetic memories; the ratio of the number of magnetic memories in which the state changes to the number of all magnetic memories is used to determine the read disturbance of the magnetic memories. In this embodiment, for a single test, the read disturb P of the array is the number of magnetic memories that change state/total number of magnetic memories.

In an alternative embodiment, after determining the read disturbance of the magnetic memory, the method further comprises: determining a thermal stability factor of the magnetic memory by fitting the read disturbance and the second excitation of the magnetic memory. In this embodiment, since the current writing of STT-MRAM has random characteristics, there is a certain probability that a small voltage (or current) will change the data state when reading data, which is called read disturb, and according to the thermal disturb theory and STT effect, the read disturb probability (P) and the voltage value V_readIs the read voltage and the duration t_readThe following steps are involved:

wherein V_cThe critical voltage, t is the pulse width corresponding to the read voltage, and it can be seen from the dependence formula that the read disturbance is also directly related to the thermal stability factor Δ.

In the read disturb test: p < 1

ln(1-P)＝-t/{τ₀exp(Δ(1-V/V_c))}

P＝t/{τ₀exp(Δ(1-V/V_c))}

ln(P)＝ln(t/τ₀)-Δ(1-V/V_c) (3)

When the stimulus is a voltage or current, P is the read disturbance versus read voltage or read current. In the formula (3), ln (P) and write voltage (V/V)_c) Is a linear relationship (as shown in FIG. 4, where V_read/V_cCorresponding to V/V_c) Scale factorIs Δ. Linear fitting of the data can result in the thermal stability factor Δ (fitted line slope) for a single MTJ or a statistical average of the thermal stability factors for the array. Mixing ln, (P) and (V/V)_c) Linear fitting was performed and the thermal stability factor Δ is fitted to the slope of the line. The data storage time is as follows: τ ═ τ₀exp (. DELTA.) wherein.tau₀1ns is the material characteristic time.

In an alternative embodiment, after separately reading the data states in the respective magnetic memories, the method further comprises: repeating the operations of applying the first stimulus, applying the second stimulus, and reading the data state in the respective magnetic memories; a predetermined magnetic memory read disturb is determined based on repeatedly reading data states in the respective magnetic memories.

In an alternative embodiment, determining a read disturbance for a predetermined one of all of the magnetic memories based on the repeatedly read data states in the respective magnetic memories comprises: determining a total number of times that the data state in the predetermined magnetic memory is repeatedly read, and determining a number of times that the state of the predetermined magnetic memory is changed according to the repeatedly read data state in the predetermined magnetic memory; determining a read disturbance of the predetermined magnetic memory using a ratio of the number of times the state of the predetermined magnetic memory changes to the total number of times the data state in the predetermined magnetic memory is repeatedly read. In this embodiment, for multiple repeated tests, the read disturbance P of a single magnetic memory is the number of state changes/number of repeated tests.

In an alternative embodiment, after determining the read disturbance for the predetermined magnetic memory, the method further comprises: determining a thermal stability factor of the predetermined magnetic memory by fitting the read disturbance and the second excitation of the predetermined magnetic memory.

The embodiment of the present invention further provides a device for testing a magnetic memory, where the device is used to implement the steps in the above method embodiments and preferred embodiments, and details of which have been already described are omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

Fig. 5 is a block diagram of a first apparatus for testing a magnetic memory according to an embodiment of the present invention, as shown in fig. 5, the apparatus includes the following modules:

a first processing module 52, configured to apply a first excitation to all the magnetic memories, and perform a write operation of writing data in all the magnetic memories, wherein an excitation value of the first excitation is greater than a predetermined threshold; a second processing module 54, connected to the first processing module 52, for applying a second excitation to all the magnetic memories after the write operation is completed, wherein an excitation value of the second excitation is smaller than the predetermined threshold; a reading module 56, connected to the second processing module 54, for reading the data states in the respective magnetic memories after the second stimulus is applied; and a determining module 58, connected to the reading module 56, for determining read disturbances of the magnetic memories according to the read data states in the respective magnetic memories.

In an alternative embodiment, the determining module 58 includes: a first determination unit for determining the number of magnetic memories whose states change according to the data states read from the respective magnetic memories; a second determination unit for determining read disturbance of the magnetic memories using a ratio of the number of magnetic memories whose state changes to the number of all magnetic memories.

In an alternative embodiment, after determining the read disturbance of the magnetic memory, the method further comprises: determining a thermal stability factor of the magnetic memory by fitting the read disturbance and the second excitation of the magnetic memory.

In an alternative embodiment, determining a read disturbance for a predetermined one of all of the magnetic memories based on the repeatedly read data states in the respective magnetic memories comprises: determining a total number of times that the data state in the predetermined magnetic memory is repeatedly read, and determining a number of times that the state of the predetermined magnetic memory is changed according to the repeatedly read data state in the predetermined magnetic memory; determining a read disturbance of the predetermined magnetic memory using a ratio of the number of times the state of the predetermined magnetic memory changes to the total number of times the data state in the predetermined magnetic memory is repeatedly read.

In an optional embodiment, after determining the read disturbance of the predetermined magnetic memory, the method further comprises: determining a thermal stability factor of the predetermined magnetic memory by fitting the read disturbance and the second excitation of the predetermined magnetic memory.

A second testing apparatus for a magnetic memory is also provided in the embodiment of the present invention, referring to fig. 6, which is a schematic diagram of a testing apparatus for a magnetic memory provided in the embodiment of the present invention, the testing apparatus may include a cross-point matrix array (corresponding to 101 in fig. 6), a testing electrode array (corresponding to 102 in fig. 6), and a switch set (corresponding to 103 and 104 in fig. 6), where the cross-point matrix array includes a bit line BL set (corresponding to BL in fig. 6)₁,BL₂BL_N) And source line SL group (corresponding to SL in FIG. 6)₁,SL₂SL_N) Wherein, the BL group comprises more than two BLs, the SL group comprises more than two SLs, and a magnetic memory (corresponding to MTJ in fig. 6) is connected between each BL in the BL group and each SL in the SL group; the test electrode array (corresponding to TE in FIG. 6)₁,TE₂TE_2N) The array comprises more than two first electrodes, wherein each first electrode is connected with each BL or each SL in the cross lattice array one by one; the switch group comprises a first switch (corresponding to switch B in FIG. 6), a second switch (corresponding to switch D in FIG. 6), and a third switch array (corresponding to switch A in FIG. 6)₁,A₂A_N) And a fourth switch array (corresponding to switch C in fig. 6)₁,C₂C_N) Wherein one end of the first switch is connected to each magnetThe other end of the test instrument for testing the memory is provided with more than two connection points which are in one-to-one correspondence with each BL in the BL group; one end of the second switch is connected to the test instrument, and the other end of the second switch is provided with more than two connection points which are in one-to-one correspondence with the SLs in the SL group; the third switch array comprises more than two third switches which are in one-to-one correspondence with each BL in the BL group, one end of each third switch is connected to the test instrument, and the other end of each third switch is connected to the BL; the fourth switch array comprises more than two fourth switches which are in one-to-one correspondence with the SLs in the SL group, one end of each fourth switch is connected to the test instrument, and the other end of each fourth switch is connected to the SL. In this embodiment, the magnetic memory (e.g., MTJ) is composed of a magnetic free layer, an insulating layer, and a magnetic pinned layer. The magnetization direction of the fixed layer is fixed, and the free layer has two different orientations and can be controlled by voltage or current; the two magnetization directions of the free layer are respectively parallel (data 0) or antiparallel (data 1) corresponding to the two magnetization directions. Each bit line BL is respectively connected with 1 row of MTJ top electrodes; every 1 source line SL is respectively connected with 1 column of MTJ bottom electrodes. Thereby forming an MTJ array (101). Thus, a MTJ device at a uniquely selected intersection can be passed through 1 bit line and 1 source line. Each bit line or source line is connected to 1 test electrode (102). The test electrodes may be compatible with standard electrical parameter test (WAT), and the test electrodes may be arranged in a row according to fig. 6, or may have any other arrangement. The test electrodes are connected to a switch matrix (103) by means of probes. The bit lines BL1 through BLN are connected to the switch matrix 104 through switches a1 through AN, and may also be connected together through B and then to the switch matrix 104. The source lines SL1 to SLN are connected to the switch matrix 104 through the switches C1 to CN, or may be connected together through D and then connected to the switch matrix 104. The switch matrix 104 enables interconnection of the test meter and the array to apply voltage signals or read each MTJ state.

Switch matrices

103 and 104 may be a single switch matrix, performing the function of both matrices. The 103 and 104 functions may be integrated together and replaced by a single module.

In an alternative embodiment, the magnetic memory is divided into a magnetic memory array of n1 rows and n2 columns, the number of BLs included in the BL group is n1, and the number of SLs included in the SL group is n2, where: each BL is respectively connected with the top electrode of each magnetic memory in each row of magnetic memories, and each SL is respectively connected with the bottom electrode of each magnetic memory in each column of magnetic memories.

In an alternative embodiment, a first stimulus is applied to all magnetic memories when the switch set is in a first connection state, wherein the stimulus value of the first stimulus is greater than a predetermined threshold value, so that all magnetic memory cells are in some same state. The first connection state is that the first switches are connected with the BL in the BL group in a one-to-one correspondence manner, the second switches are connected with the SL in the SL group in a one-to-one correspondence manner, all the BL in the BL group are connected with all the SL in the SL group in a one-to-one correspondence manner, and all the magnetic memories in the cross dot matrix array are in a conduction state; applying a second stimulus to all magnetic memories after applying said first stimulus, wherein said second stimulus has a stimulus value less than said predetermined threshold value, which stimulus has a probability of changing the state of an individual memory cell; after the second excitation is applied and when the switch group is in a second connection state, reading the data state in each magnetic memory respectively, wherein the second connection state is that each third switch in the third switch array is connected with each BL in the BL group in a one-to-one correspondence mode, each fourth switch in the fourth switch array is connected with each SL in the SL group in a one-to-one correspondence mode, and the conducting state of each magnetic memory in the cross dot matrix array is controlled by controlling the conducting state of each switch in the third switch array and the fourth switch array. And controlling the connection state of the magnetic memories in the cross point array by controlling the connection state of the switches in the first switch, the second switch, the third switch array and the fourth switch array, so as to test the magnetic memories. In this embodiment, the switch matrix 103 is in the B and D positions so that all bit lines and all source lines are connected together, respectively. All the MTJ upper and lower (BL, SL) electrodes are turned on by the switch matrix 2(104), respectively. All MTJ array states are written (initialized). At the current read voltage value, a voltage stimulus is applied to all MTJs for a specified length of time, which may be one or more stimuli. Switch matrix 1 is selected as A1 … AN, C1 … CN. By turning on the single MTJ one by the switch matrix 2, all MTJ states are read, and when a1 to AN, C1 to CN, and T1 to TN in the switch matrix 103 are turned on, the single MTJ can be selected by the switch matrix 104, for example: turning on A1, C1, T1 uniquely selects the magnetic memory device in the upper left corner of FIG. 6. Repeating the following steps (2) - (5) for different read voltage values or according to the test times. The variation of array or single MTJ read disturbance with read condition is obtained. (read voltage, time length, accumulated time length, etc.) data analysis is performed according to the correlation model. The thermal stability factor and data retention time were calculated using the thermal perturbation theory. The present invention is described below with reference to a specific embodiment, and fig. 7 is a flowchart of a method for testing a magnetic memory according to the present invention, and the following steps of testing the magnetic memory according to the present embodiment are described with reference to the flowchart: (1) and (5) initializing the test, and generating a test excitation condition list. Such as the excitation voltage, the pulse width, the number of repeated applications, and the like (corresponding to S701 in fig. 7). (2) The switch matrix 1 is selected to be B, D. All the MTJ upper and lower (BL, SL) electrodes are turned on by the switch matrix 2, respectively (corresponding to S702 in fig. 7). (3) All MTJ array states are written (initialized) (corresponding to S703 in fig. 7). (4) Under the current read stimulus conditions, a stimulus is applied to all MTJs (corresponding to S704 in FIG. 7). (5) Switch matrix 1 is selected as A1 … AN, C1 … CN. The switch matrix 2 is used to turn on the individual MTJs one by one and read all MTJ states. The turn-on sequence is arbitrary (corresponding to S705 in fig. 7). (6) The step operations (2) - (5) are performed with different excitation conditions according to the condition list (corresponding to S706 in fig. 7). (7) The variation of read disturb (MTJ ratio of state change) with excitation condition is obtained. (excitation voltage, time length, accumulated time length, etc.) data analysis is performed according to the correlation model. Including but not limited to using thermal perturbation theory to calculate the thermal stability factor and data retention time. Other theories may also be used for data analysis (corresponding to S707 in fig. 7).

In the embodiment of the present invention, a third testing apparatus for a magnetic memory is further provided, and referring to fig. 8, a schematic diagram of another testing apparatus for a magnetic memory according to the embodiment of the present invention is provided, and the testing apparatus may include a cross-point array(corresponding to 101 in fig. 8), a test electrode array (corresponding to 102 in fig. 8), and a switch set (corresponding to 103 and 104 in fig. 8), wherein the cross-point array comprises a bit line BL set (corresponding to BL in fig. 8)₁,BL₂BL_N) And source line SL group (corresponding to SL in FIG. 8)₁,SL₂SL_N) Wherein, the BL group comprises more than two BLs, the SL group comprises more than two SLs, and a magnetic memory (corresponding to MTJ in fig. 8) is connected between each BL in the BL group and each SL in the SL group; the test electrode array comprises more than two first electrodes, and each first electrode is connected with each BL or each SL in the cross dot matrix array one by one; the switch group comprises a first switch (corresponding to switch B in FIG. 8), a second switch (corresponding to switch D in FIG. 8), and a third switch array (corresponding to switch A in FIG. 8)₁,A₂A_N) And a fourth switch array (corresponding to switch C in fig. 8)₁,C₂C_N) One end of the first switch is connected to a test instrument for testing each magnetic memory, and the other end of the first switch is provided with more than two connection points which are in one-to-one correspondence with each BL in the BL group; one end of the second switch is connected to the test instrument, and the other end of the second switch is provided with more than two connection points which are in one-to-one correspondence with the SLs in the SL group; the third switch array comprises more than two third switches which are in one-to-one correspondence with each BL in the BL group, one end of each third switch is connected to the test instrument, and the other end of each third switch is connected to the BL; the fourth switch array comprises more than two fourth switches which are in one-to-one correspondence with the SLs in the SL group, one end of each fourth switch is connected to the test instrument, and the other end of each fourth switch is connected to the SL.

In an alternative implementationIn one example, the device further includes a transistor group and a word line WL group (corresponding to WL in FIG. 8)₁,WL₂WL_N) The WL group comprises n2 WLs, the test electrode array further comprises n2 second electrodes, each second electrode is respectively connected with each WL in the WL group in a one-to-one mode, the switch group further comprises a fifth switch (corresponding to the switch U in FIG. 8) and a sixth switch array (corresponding to the switch T in FIG. 8)₁,T₂T_N) The fifth switch has one end connected to the test instrument and the other end provided with n2 connection points corresponding to the n2 WLs, the sixth switch array includes two or more sixth switches corresponding to the n2 WLs, and each sixth switch has one end connected to the test instrument and the other end connected to the WL, wherein:

each transistor in the transistor group is respectively arranged in one-to-one correspondence with each magnetic memory, each transistor comprises three pins, wherein a first pin (drain) and a second pin (source) are respectively used for connecting the magnetic memories and the corresponding SL, a third pin (grid) is connected with WLs, and each WL is respectively connected with one column of magnetic memories.

In an optional embodiment, when the switch group is in a third connection state, a first excitation is applied to all the magnetic memories, wherein an excitation value of the first excitation is greater than a predetermined threshold value, the third connection state is that the first switch is connected with each BL in the BL group in a one-to-one correspondence manner, the second switch is connected with each SL in the SL group in a one-to-one correspondence manner, the fifth switch is connected with each WL in the WL group in a one-to-one correspondence manner, all BLs in the BL group, all SLs in the SL group, and all WLs in the WL group in a one-to-one correspondence manner, and all the magnetic memories in the cross-point array are in a conducting state; applying a second stimulus to all magnetic memories after applying the first stimulus, wherein a stimulus value of the second stimulus is less than the predetermined threshold; after the second excitation is applied and when the switch group is in a fourth connection state, reading the data state in each magnetic memory respectively, wherein the fourth connection state is that each third switch in the third switch array is connected with each BL in the BL group in a one-to-one correspondence manner, each fourth switch in the fourth switch array is connected with each SL in the SL group in a one-to-one correspondence manner, each sixth switch in the sixth switch array is connected with each WL in the WL group in a one-to-one correspondence manner, and the conduction state of each magnetic memory in the cross-point array is controlled by controlling the conduction state of each switch in the third switch array, the fourth switch array and the sixth switch array. In this embodiment, when B, D, U in switch matrix 103 is on, all MTJs may be simultaneously stressed and voltage applied through switch matrix 104. When the switches A1 to AN, C1 to CN, and T1 to TN in the switch matrix 103 are turned on, the single MTJ can be selected by the switch matrix 104. For example: turning on A1, C1 and T1 selects only the top left MTJ device.

It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.

An embodiment of the present invention further provides a storage medium including a stored program, where the program executes any one of the methods described above.

Optionally, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing program codes, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

An embodiment of the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes any one of the methods described above through the computer program.

It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An apparatus for testing a magnetic memory, comprising: a cross lattice array, a test electrode array, a switch group, wherein,

the cross dot matrix array comprises bit line BL groups and source line SL groups, wherein the BL groups comprise more than two BL, the SL groups comprise more than two SL, and a magnetic memory is connected between each BL in the BL groups and each SL in the SL groups;

the test electrode array comprises more than two first electrodes, and each first electrode is connected with each BL or each SL in the cross dot matrix array one by one;

the switch group comprises a first switch, a second switch, a third switch array and a fourth switch array, wherein one end of the first switch is connected to a test instrument for testing each magnetic memory, and the other end of the first switch is provided with more than two connection points which are in one-to-one correspondence with each BL in the BL group; one end of the second switch is connected to the test instrument, and the other end of the second switch is provided with more than two connection points which are in one-to-one correspondence with the SLs in the SL group; the third switch array comprises more than two third switches which are in one-to-one correspondence with each BL in the BL group, one end of each third switch is connected to the test instrument, and the other end of each third switch is connected to the BL; the fourth switch array comprises more than two fourth switches which are in one-to-one correspondence with the SLs in the SL group, one end of each fourth switch is connected to the test instrument, and the other end of each fourth switch is connected to the SL.

2. The apparatus for testing a magnetic memory according to claim 1, wherein the magnetic memory is divided into a magnetic memory array of n1 rows, n2 columns, the number of BLs included in the BL group is n1, the number of SLs included in the SL group is n2, wherein:

each BL is respectively connected with the top electrode of each magnetic memory in each row of magnetic memories, and each SL is respectively connected with the bottom electrode of each magnetic memory in each column of magnetic memories.

3. The apparatus for testing a magnetic memory according to claim 2, further comprising a transistor group and a word line WL group, wherein the WL group comprises n2 WLs, the test electrode array further comprises n2 second electrodes, each of the second electrodes is respectively connected to each WL in the WL group, the switch group further comprises a fifth switch and a sixth switch array, one end of the fifth switch is connected to the test instrument, the other end of the fifth switch is provided with n2 connection points corresponding to the n2 WLs, the sixth switch array comprises more than two sixth switches corresponding to the n2 WLs, one end of each sixth switch is connected to the test instrument, the other end of each sixth switch is connected to the WL, and the sixth switch is connected to the test instrument,

each transistor in the transistor group is respectively in one-to-one correspondence with each magnetic memory, each transistor comprises three pins, wherein the first pin and the second pin are respectively used for connecting the magnetic memories and the corresponding SL, the third pin is connected with the WL, and each WL is respectively connected with one row of the magnetic memories.

4. A test apparatus for a magnetic memory as claimed in claim 2, wherein the test meter is configured to:

applying a first excitation to all magnetic memories when the switch set is in a first connection state, wherein an excitation value of the first excitation is greater than a predetermined threshold; the first connection state is that the first switches are connected with the BL in the BL group in a one-to-one correspondence manner, the second switches are connected with the SL in the SL group in a one-to-one correspondence manner, all the BL in the BL group are at the same electric potential, all the SL in the SL group are at the same electric potential, and all the magnetic memories in the cross dot matrix array are in a conduction state;

applying a second stimulus to all magnetic memories after applying the first stimulus, wherein a stimulus value of the second stimulus is less than the predetermined threshold;

after the second excitation is applied, the switch group is switched to a second connection state, the data states in the magnetic memories are respectively read, wherein the second connection state is that each third switch in the third switch array is connected with each BL in the BL group in a one-to-one correspondence mode, each fourth switch in the fourth switch array is connected with each SL in the SL group in a one-to-one correspondence mode, and the conduction state of each magnetic memory in the cross dot matrix array is controlled by controlling the conduction state of each switch in the third switch array and the fourth switch array.

5. A test apparatus for a magnetic memory according to claim 3, wherein the test meter is configured to:

when the switch group is in a third connection state, applying a first excitation to all the magnetic memories, wherein an excitation value of the first excitation is greater than a predetermined threshold value, the third connection state is the third connection state, the first switches are connected with the BL in the BL group in a one-to-one correspondence manner, the second switches are connected with the SL in the SL group in a one-to-one correspondence manner, the fifth switches are connected with the WL in the WL group in a one-to-one correspondence manner, all the BL in the BL group, all the SL in the SL group and all the WLs in the WL group in a one-to-one correspondence manner, and all the magnetic memories in the cross dot matrix array are in a conduction state;

after the second excitation is applied and when the switch group is in a fourth connection state, reading the data state in each magnetic memory respectively, wherein the fourth connection state is that each third switch in the third switch array is connected with each BL in the BL group in a one-to-one correspondence manner, each fourth switch in the fourth switch array is connected with each SL in the SL group in a one-to-one correspondence manner, each sixth switch in the sixth switch array is connected with each WL in the WL group in a one-to-one correspondence manner, and the conduction state of each magnetic memory in the cross-point array is controlled by controlling the conduction state of each switch in the third switch array, the fourth switch array and the sixth switch array.