CN108694262A - A kind of decoupling capacitor optimization method and device - Google Patents
A kind of decoupling capacitor optimization method and device Download PDFInfo
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- CN108694262A CN108694262A CN201710232092.XA CN201710232092A CN108694262A CN 108694262 A CN108694262 A CN 108694262A CN 201710232092 A CN201710232092 A CN 201710232092A CN 108694262 A CN108694262 A CN 108694262A
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Abstract
The embodiment of the invention discloses a kind of decoupling capacitor optimization method, corresponding first capacitance of maximum loop inductance in first via power supply is determined in PCB, the PCB includes at least power supply all the way, and the first via power supply is at least arbitrary power supply all the way in power supply all the way;The first impedance of the first via power supply after deleting first capacitance is calculated according to the model of PCB;When first impedance meets preset condition, determine that first capacitance is the deletion capacitance in the first via power supply, so that carrying out decoupling capacitor optimization to the first via power supply by deleting first capacitance in the first via power supply.The embodiment of the present invention also provides a kind of decoupling capacitor optimization device simultaneously.
Description
Technical field
The present invention relates to electronic technology field more particularly to a kind of decoupling capacitor optimization methods and device.
Background technology
With the development of very large scale integration technology, chip channel dimensions inevitably further contract in proportion
Small, the supply voltage of integrated circuit will continue to reduce, and cause chip Ripple Noise thresholding and design capacity to reduce, higher letter
Number rate makes power supply noise to parasitisms such as encapsulation, printed circuit board (PCB, Printed Circuit Board) cabling, vias
Parameter is more sensitive.Therefore, chip how is ensured under different process, voltage and temperature condition, and in various businesses pattern
Lower normal work is all huge challenge for Power Integrity design.Power Integrity design needs to meet three big targets, point
It is not chip level, power supply that is clean, stablizing is provided for chip;Veneer level provides the reference of Low ESR, low noise for signal
Circuit, it is ensured that impedance continuity and reduction crosstalk;System level avoids electromagnetic interference emission, and power supply noise is as electromagnetic interference
The important component of (EMI, Electromagnetic Interference), analyzes it and inhibits.
Power distribution network (PDN) is made of power ground cabling, plane and decoupling capacitor, due to there is parasitic electricity
The parasitic parameters such as resistance, inductance, capacitance, impedance are simultaneously not zero, and need the resonance characteristic using decoupling capacitor, pass through different capacitances
The parallel combination of the capacitor of value is less than target impedance to obtain minimum input impedance, there are one proof load chips stablizes,
Lasting power supply supply.But the prior art is in the project, the appearance of the decoupling capacitor of usual power distribution network (PDN) above
Value and quantity are designed according to the reference of master chip manufacturer, as long as the AC impedance of each power supply and DC impedance are imitative
Even if true result is qualified in the range of standard value.In off-the-shelf item, the capacitance and quantity of the coupled capacitor around chip are ginsengs
The design of chip producer is examined, how many puts how many, and power ground cabling maximizes design according to the layout area of coupled capacitor, still
It is such to design a large amount of areas for not only occupying veneer while also increasing cost, using target impedance method, as long as emulation is logical
Even if crossing qualification, the optimization of capacitance, so more coupled capacitors are not considered further that, the big quantity space of veneer is not only occupied, also increases
Cost is added.
The selection of prior art decoupling capacitor mainly has big " V ", Decade Methods methods and Flat
Response methods, still, these methods have some limitations, as big " V " method needs much in the design process
The capacitance of capacitance identical in this way, amount of redundancy is big, increases the layout area of veneer;Decade Methods methods and Flat
It is limited using capacitance number and type in response methods, it can not necessarily reach the requirement of the target impedance of power supply.
Invention content
To solve existing technical problem, a kind of decoupling capacitor optimization method of offer of the embodiment of the present invention and device,
On the basis of ensureing impedance, the rational capacitance size and number for arranging capacitance reduces arrangement space, cost-effective.
In order to achieve the above objectives, the technical solution of the embodiment of the present invention is realized in:
The embodiment of the present invention provides a kind of decoupling capacitor optimization method, the method includes:
Determine that corresponding first capacitance of maximum loop inductance, the PCB include in first via power supply in printing board PCB
At least power supply all the way, the first via power supply are at least arbitrary power supply all the way in power supply all the way;
The first impedance of the first via power supply after deleting first capacitance is calculated according to the model of PCB;
When first impedance meets preset condition, determine that first capacitance is the deletion in the first via power supply
Capacitance, so that carrying out decoupling capacitor to the first via power supply by deleting first capacitance in the first via power supply
Optimization.
Further, the maximum loop inductance corresponding first in first via power supply in the determining printing board PCB
Before capacitance, the method further includes:
The PCB is obtained, the PCB is imported into emulation tool, is determined at least one in the PCB by the emulation tool
The loop inductance of the coupled capacitor of road power supply.
Further, first resistance that the first via power supply after deleting first capacitance is calculated according to preset model
It is anti-, including:
The model that the PCB is determined by emulation tool obtains predeterminated frequency range internal impedance according to the model of the PCB
Size curve determines the first impedance of the first via power supply after deleting first capacitance according to the impedance magnitude curve.
Further, it described when first impedance meets preset condition, determines by deleting the first via electricity
Before first capacitance in source carries out decoupling capacitor optimization to the first via power supply, the method further includes:
First impedance and the target impedance of the first via power supply are compared;
When first impedance is less than the target impedance of the first via power supply, it is default to determine that first impedance meets
Condition.
Further, before the acquisition PCB, including:
It obtains in the power distribution network of the PCB per the target impedance of power supply all the way.
Further, described when first impedance meets preset condition, determine that first capacitance is described the
All the way after the deletion capacitance in power supply, the method further includes:
Determine it is described at least all the way in power supply per the deletion capacitance in power supply all the way, it is described per in power supply all the way by deleting
Deletion capacitance to the PCB carry out decoupling capacitor optimization.
The embodiment of the present invention provides a kind of decoupling capacitor optimization device, and described device includes:Determination unit, processing unit,
Wherein,
The determination unit, for determining in printing board PCB maximum loop inductance corresponding in first via power supply
One capacitance, the PCB include at least power supply all the way, and the first via power supply is described at least arbitrary electric all the way in power supply all the way
Source;
The processing unit, for calculating the first via power supply after deleting first capacitance according to the model of PCB
One impedance;
The determination unit is additionally operable to, when first impedance meets preset condition, determine first capacitance for institute
The deletion capacitance in first via power supply is stated, so that by deleting first capacitance in the first via power supply to described the
Power supply carries out decoupling capacitor optimization all the way.
Further, described device further includes:The PCB is imported emulation work by acquiring unit for obtaining the PCB
Tool;
The determination unit, for determining in the PCB at least coupled capacitor of power supply all the way by the emulation tool
Loop inductance.
Further, the determination unit, specifically for determining the model of the PCB by emulation tool, according to described
The model of PCB obtains predeterminated frequency range internal impedance size curve, is determined according to the impedance magnitude curve and deletes described first
First impedance of the first via power supply after capacitance.
Further, the processing unit, for by the target impedance of first impedance and the first via power supply into
Row comparison;
The determination unit is used to, when first impedance is less than the target impedance of the first via power supply, determine institute
It states the first impedance and meets preset condition.
Further, the acquiring unit, per the target of power supply all the way in the power distribution network for obtaining the PCB
Impedance.
Further, the determination unit, it is described at least all the way in power supply per the deletion electricity in power supply all the way for determining
Hold, decoupling capacitor optimization is carried out to the PCB by deleting the deletion capacitance per in power supply all the way.
An embodiment of the present invention provides a kind of decoupling capacitor optimization method and devices, determine first in printing board PCB
Corresponding first capacitance of maximum loop inductance in the power supply of road, the PCB include that at least power supply, the first via power supply are institute all the way
State at least arbitrary power supply all the way in power supply all the way;The first via electricity after deleting first capacitance is calculated according to the model of PCB
First impedance in source;When first impedance meets preset condition, determine that first capacitance is in the first via power supply
Deletion capacitance so that being gone to the first via power supply by deleting first capacitance in the first via power supply
Coupling capacitance optimizes.Decoupling capacitor optimization method and device provided in an embodiment of the present invention, in the power distribution network for ensureing PCB
The target impedance of PDN simultaneously, removes the coupling that loop inductance is bigger and the corresponding power supply of placement position off-chip piece is distant
Capacitance so that the whole loop inductance above power distribution network is reduced, and reduces PCB arrangement spaces, cost-effective.
Description of the drawings
In attached drawing (it is not necessarily drawn to scale), similar reference numeral phase described in different views
As component.Similar reference numerals with different letter suffix can indicate the different examples of similar component.Attached drawing with example and
Unrestricted mode generally shows each embodiment discussed herein.
Fig. 1 is decoupling capacitor optimization method flow diagram one provided in an embodiment of the present invention;
Fig. 2 is equivalent circuit exemplary plot one provided in an embodiment of the present invention;
Fig. 3 is equivalent circuit exemplary plot two provided in an embodiment of the present invention;
Fig. 4 is decoupling capacitor optimization method flow diagram two provided in an embodiment of the present invention;
Fig. 5 is loop inductance exemplary plot provided in an embodiment of the present invention;
Fig. 6 is impedance curve exemplary plot provided in an embodiment of the present invention;
Fig. 7 is that decoupling capacitor provided in an embodiment of the present invention optimizes apparatus structure schematic diagram one;
Fig. 8 is that decoupling capacitor provided in an embodiment of the present invention optimizes apparatus structure schematic diagram two.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes.
The embodiment of the present invention provides a kind of decoupling capacitor optimization method, as shown in Figure 1, the method includes:
Step 101 determines in PCB corresponding first capacitance of maximum loop inductance in first via power supply.
Wherein, the PCB includes at least power supply all the way, and the first via power supply is described at least arbitrary in power supply all the way
Power supply all the way.
The executive agent of decoupling capacitor optimization method provided in an embodiment of the present invention is that decoupling capacitor optimizes device, that is, is decoupled
Capacitance optimization device determines in printing board PCB corresponding first capacitance of maximum loop inductance in first via power supply.
Wherein, PCB (Printed Circuit Board), Chinese is printed circuit board, also known as printed wiring board,
It is important electronic unit, is the supporter of electronic component, is the carrier of electronic component electrical connection.Since it is to use
What electron printing made, therefore be referred to as " printing " circuit board.
Further, corresponding first capacitance of maximum loop inductance in first via power supply in determining printing board PCB
Before, the method can also include:
It obtains in the power distribution network of PCB per the target impedance of power supply all the way.
Wherein, power distribution network (PDN) refer to from power supply (VRM) to the path of active device (IC) or interconnection,
Its impedance includes active internal resistance itself, the impedance in PCB trace, decoupling capacitor and IC package.
As shown in Fig. 2, right figure is the simple equivalent circuit figure of left figure in Fig. 2, AB is impedance observation point, i.e. on target IC
Network equivalent between 2 points of AB is a current source by power supply and earth point, and Z is its output impedance, and the size of Z determines core
The size of the power supply noise of piece.For a stable power supply system, change regardless of the load transient electric current of AB point-to-point transmissions,
It is required for ensureing the voltage change range very little of AB point-to-point transmissions, so low, the PDN for also just needing the impedance Z of power-supply system enough
Impedance design need the resonance characteristic of decoupling capacitor, minimum input impedance is obtained by the parallel combination of capacitor.
It can obtain according to fig. 2:Δ V (ω)=Z (ω) * Δs I (ω)
Wherein, Δ V (ω) is voltage, and Z is impedance, and Δ I is electric current.
Equivalent Z=ESR+j2 π f × ESL+1/ (j2 π f × C)
Wherein, ESR is equivalent resistance, and ESL is equivalent inductance, and C is capacitor's capacity.
For the PCB of actual items, target impedance formula be difficult quote in practice because the electric current above pcb board and
Frequency range is all difficult to determine, also without and frequency clear correspondence, in actual items, chip producer generally can clearly give
Go out the target impedance value of the PCB grades of IC chip, wherein the calculation formula of target impedance is:
During actual optimization, need the PCB after guarantee optimization design by emulation, obtained result is in target impedance
In the range of.
Capacitance is most important source impedance control optimizer part, and decoupling capacitor is all welded to pcb board above, in addition to
The equivalent resistance ESR and equivalent inductance ESL of capacitance itself can also be introduced additional due to cabling, via, pad, welding etc.
Parasitic parameter, the parasitic parameter of these parasitic parameters and capacitance itself influences the resonant frequency of capacitance, to affect together
The sphere of action of capacitance.
As shown in figure 3, right figure is the simple equivalent circuit figure of left figure in Fig. 3, it is main in the additional parasitic parameter being introduced into
Be exactly parasitic inductance, the effective loop inductance that can be equivalent in figure.Effective loop inductance Lpcb1 weakens Cde-
Cap is to the decoupling effects of Pwr and Gnd point-to-point transmissions, and effectively loop inductance (Lpcb+Lpcb1) weakens Cbulk to Pwr and Gnd two
Decoupling effect between point.It follows that the size of loop inductance directly affects the decoupling effect of capacitance.
Core of the invention is to control the loop inductance of decoupling capacitor, and the loop inductance of decoupling capacitor is determined by emulation,
It determines the bigger capacitance of loop inductance, removes that loop inductance is bigger and placement position power supply PIN corresponding from MSM chips
The distant coupled capacitor of foot, the capacitance of capacitance that change loop inductance is taken second place so that whole above power distribution network
Loop inductance is reduced, and targetedly adjusts the size and number held per road power supply electrifying, to reach cost-effective, reduces range of distribution
Long-pending purpose.
Step 102, the first impedance that the first via power supply after deleting first capacitance is calculated according to the model of PCB.
Specifically, determining the model of PCB by emulation tool, obtained within the scope of predeterminated frequency according to the model of the PCB
Impedance magnitude curve determines the first resistance of the first via power supply after deleting first capacitance according to the impedance magnitude curve
It is anti-.
Step 103, when first impedance meets preset condition, determine first capacitance be the first via power supply
In deletion capacitance so that being carried out to the first via power supply by deleting first capacitance in the first via power supply
Decoupling capacitor optimizes.
Specifically, when the first impedance is less than the target impedance of the first via power supply, determine that first impedance meets
Preset condition determines that first capacitance is the deletion capacitance in the first via power supply.
Optionally, it described when first impedance meets preset condition, determines by deleting the first via power supply
In first capacitance to the first via power supply carry out decoupling capacitor optimization before, the method further includes:
First impedance and the target impedance of the first via power supply are compared;
When first impedance is less than the target impedance of the first via power supply, it is default to determine that first impedance meets
Condition.
Optionally, described when first impedance meets preset condition, determine that first capacitance is described first
After deletion capacitance in the power supply of road, the method further includes:
Determine it is described at least all the way in power supply per the deletion capacitance in power supply all the way, it is described per in power supply all the way by deleting
Deletion capacitance to the PCB carry out decoupling capacitor optimization.
Decoupling capacitor optimization method provided in an embodiment of the present invention, in the target resistance for ensureing the power distribution network PDN of PCB
Resist simultaneously, remove the coupled capacitor that loop inductance is bigger and the corresponding power supply of placement position off-chip piece is distant so that electricity
The whole loop inductance that source is distributed above network is reduced, and reduces PCB arrangement spaces, cost-effective.
The embodiment of the present invention provides a kind of decoupling capacitor optimization method, as shown in figure 4, the method includes:
Target impedance in step 201, the power distribution network of decoupling capacitor optimization device acquisition PCB per power supply all the way.
Wherein, power distribution network (PDN) is the mesh for the power distribution network for being provided chip producer by frequency-domain analysis
Mark impedance setting is reference standard, and the target impedance design method of power distribution network (PDN) requires to input resistance from the point of view of IC
Resist and be both less than target impedance in the frequency range of concern, that is, low impedance characteristic is presented, is hindered using the antiresonance point of decoupling capacitor
The feature of anti-minimum reduces the input impedance of PDN.
Specifically, the power distribution network of PCB includes multiple power supplies, according to the data that PCB master chips producer provides, determine
The target impedance of the roads power distribution network (PDN) Zhong Mei power supply, this is as comparison reference standard.
Step 202, decoupling capacitor optimization device obtain the PCB, the PCB are imported emulation tool, by described imitative
True tool determines in the PCB at least loop inductance of the coupled capacitor of power supply all the way.
Step 203, decoupling capacitor optimization device determine in PCB corresponding first electricity of maximum loop inductance in first via power supply
Hold.
Wherein, the PCB includes at least power supply all the way, and the first via power supply is described at least arbitrary in power supply all the way
Power supply all the way.
Specifically, after designing PCB, emulation tool is imported, the lamination of PCB, capacitor model are set according to design requirement
Deng calculating the loop inductance of the coupled capacitor of original each road power supply, data as shown in table 1 below can by emulation tool
Clearly intuitively to check the size of each coupled capacitor above power supply, as shown in figure 5, bar shaped column coupled capacitor identified above
Sizes values, according to the emulation of emulation tool it can be seen that distribution of the big coupled capacitor of loop inductance on PCB, it is seen that ring
The placement position and distance of road inductance and load, it is smaller according to decoupling capacitor value in conjunction with two parts, it needs to be placed on loop inductance
The frequency of smaller position, effect is higher, on the contrary, capacitance is bigger, can be placed on distance and load remoter place, the frequency of effect
Rate is lower, and the big and coupled capacitor far from load of loop inductance is deleted, while it is close to change distance load, but loop inductance
The capacitance of slightly big coupled capacitor.
Table 1
| Capacitance | To the loop inductance (nH) of master chip |
| C1101 | 0.41 |
| C1102 | 0.14 |
| C1103 | 0.29 |
| C1104 | 0.3 |
| C1105 | 0.38 |
| C1106 | 0.17 |
| C1107 | 0.33 |
| C1108 | 0.31 |
| C1109 | 0.45 |
| C1110 | 0.31 |
| C1112 | 0.19 |
| C1113 | 0.38 |
| C1114 | 0.33 |
| C1140 | 0.22 |
| C1141 | 0.25 |
| C2313 | 0.37 |
Step 204, decoupling capacitor optimization device calculate the first via electricity after deleting first capacitance according to the model of PCB
First impedance in source.
Step 205, decoupling capacitor optimization device carry out the target impedance of first impedance and the first via power supply
Comparison.
Step 206, when first impedance be less than the first via power supply target impedance when, decoupling capacitor optimize device
It determines that first impedance meets preset condition, determines that first capacitance is the deletion capacitance in the first via power supply.
Specifically, proposing the .snp models of PCB by emulation tool, computing impedance size is obtained in certain frequency range
Interior impedance magnitude curve, impedance curve as shown in FIG. 6 find the impedance magnitude of corresponding frequency band, below respective frequencies
Target impedance is compared, and in range, sees if there is enough amount of redundancy, enough, using measure after modification.
Step 207, decoupling capacitor optimization device determine at least every deletion capacitance in power supply all the way in power supply all the way,
Decoupling capacitor optimization is carried out to the PCB by deleting the deletion capacitance per in power supply all the way.
Specifically, decoupling capacitor optimization device takes corresponding optimization method to other power supplys successively, it is final to determine
The numerical value and quantity of decoupling capacitor achieve the purpose that optimize decoupling capacitor, Optimal Curve comparison.
Decoupling capacitor optimization method provided in an embodiment of the present invention, in the target resistance for ensureing the power distribution network PDN of PCB
Resist simultaneously, remove the coupled capacitor that loop inductance is bigger and the corresponding power supply of placement position off-chip piece is distant so that electricity
The whole loop inductance that source is distributed above network is reduced, and reduces PCB arrangement spaces, cost-effective.
The embodiment of the present invention provides a kind of decoupling capacitor optimization device 30, as shown in fig. 7, described device includes:It determines single
Member 301, processing unit 302, wherein
The determination unit 301, for determining, maximum loop inductance is corresponding in first via power supply in printing board PCB
First capacitance, the PCB include at least power supply all the way, the first via power supply be it is described at least all the way in power supply it is arbitrary all the way
Power supply;
The processing unit 302, for calculating the first via power supply after deleting first capacitance according to the model of PCB
First impedance;
The determination unit 301 is additionally operable to when first impedance meets preset condition, determines that first capacitance is
Deletion capacitance in the first via power supply, so that by deleting first capacitance in the first via power supply to described
First via power supply carries out decoupling capacitor optimization.
Optionally, as shown in figure 8, described device further includes:Acquiring unit 303, for obtaining the PCB, by the PCB
Import emulation tool;
The determination unit 301, for determining that at least the coupling of power supply is electric all the way in the PCB by the emulation tool
The loop inductance of appearance.
Optionally, the determination unit 301, specifically for determining the model of the PCB by emulation tool, according to described
The model of PCB obtains predeterminated frequency range internal impedance size curve, is determined according to the impedance magnitude curve and deletes described first
First impedance of the first via power supply after capacitance.
Optionally, the processing unit 302, for by the target impedance of first impedance and the first via power supply into
Row comparison;
The determination unit 301 is used to, when first impedance is less than the target impedance of the first via power supply, determine
First impedance meets preset condition.
Optionally, the acquiring unit 303, per the mesh of power supply all the way in the power distribution network for obtaining the PCB
Mark impedance.
Optionally, the determination unit 301, it is described at least all the way in power supply per the deletion electricity in power supply all the way for determining
Hold, decoupling capacitor optimization is carried out to the PCB by deleting the deletion capacitance per in power supply all the way.
Specifically, the understanding of decoupling capacitor optimization device provided in an embodiment of the present invention can be excellent with reference to above-mentioned decoupling capacitor
Change the explanation of embodiment of the method, details are not described herein for the embodiment of the present invention.
Decoupling capacitor provided in an embodiment of the present invention optimizes device, in the target resistance for ensureing the power distribution network PDN of PCB
Resist simultaneously, remove the coupled capacitor that loop inductance is bigger and the corresponding power supply of placement position off-chip piece is distant so that electricity
The whole loop inductance that source is distributed above network is reduced, and reduces PCB arrangement spaces, cost-effective.
It should be understood by those skilled in the art that, the embodiment of the present invention can be provided as method, system or computer program
Product.Therefore, the shape of hardware embodiment, software implementation or embodiment combining software and hardware aspects can be used in the present invention
Formula.Moreover, the present invention can be used can use storage in the computer that one or more wherein includes computer usable program code
The form for the computer program product implemented on medium (including but not limited to magnetic disk storage and optical memory etc.).
The present invention be with reference to according to the method for the embodiment of the present invention, the flow of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that can be realized by computer program instructions every first-class in flowchart and/or the block diagram
The combination of flow and/or box in journey and/or box and flowchart and/or the block diagram.These computer programs can be provided
Instruct the processor of all-purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine so that the instruction executed by computer or the processor of other programmable data processing devices is generated for real
The device for the function of being specified in present one flow of flow chart or one box of multiple flows and/or block diagram or multiple boxes.
These computer program instructions, which may also be stored in, can guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works so that instruction generation stored in the computer readable memory includes referring to
Enable the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one box of block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device so that count
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, in computer or
The instruction executed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in a box or multiple boxes.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.
Claims (12)
1. a kind of decoupling capacitor optimization method, which is characterized in that the method includes:
Determine that corresponding first capacitance of maximum loop inductance, the PCB include at least in first via power supply in printing board PCB
Power supply all the way, the first via power supply are at least arbitrary power supply all the way in power supply all the way;
The first impedance of the first via power supply after deleting first capacitance is calculated according to the model of PCB;
When first impedance meets preset condition, determine that first capacitance is the deletion electricity in the first via power supply
Hold, so that excellent to first via power supply progress decoupling capacitor by deleting first capacitance in the first via power supply
Change.
2. according to the method described in claim 1, it is characterized in that, in the determining printing board PCB first via power supply
Before corresponding first capacitance of middle maximum loop inductance, the method further includes:
The PCB is obtained, the PCB is imported into emulation tool, is determined by the emulation tool at least electric all the way in the PCB
The loop inductance of the coupled capacitor in source.
3. according to the method described in claim 1, it is characterized in that, described calculated according to preset model deletes first capacitance
First impedance of first via power supply afterwards, including:
The model that the PCB is determined by emulation tool obtains predeterminated frequency range internal impedance size according to the model of the PCB
Curve determines the first impedance of the first via power supply after deleting first capacitance according to the impedance magnitude curve.
4. method according to any one of claims 1 to 3, which is characterized in that described when first impedance meets in advance
If when condition, determining and carrying out decoupling electricity to the first via power supply by deleting first capacitance in the first via power supply
Before holding optimization, the method further includes:
First impedance and the target impedance of the first via power supply are compared;
When first impedance is less than the target impedance of the first via power supply, determines that first impedance meets and preset item
Part.
5. according to the method described in claim 2, it is characterized in that, it is described obtain the PCB before, including:
It obtains in the power distribution network of the PCB per the target impedance of power supply all the way.
6. according to the method described in claim 1, it is characterized in that, described when first impedance meets preset condition,
After determining first capacitance for the deletion capacitance in the first via power supply, the method further includes:
Determine it is described at least all the way in power supply per the deletion capacitance in power supply all the way, pass through delete it is described per deleting in power supply all the way
Except capacitance carries out decoupling capacitor optimization to the PCB.
7. a kind of decoupling capacitor optimizes device, which is characterized in that described device includes:Determination unit, processing unit, wherein
The determination unit, for determining in printing board PCB corresponding first electricity of maximum loop inductance in first via power supply
Hold, the PCB includes at least power supply all the way, and the first via power supply is at least arbitrary power supply all the way in power supply all the way;
The processing unit, the first resistance for calculating the first via power supply after deleting first capacitance according to the model of PCB
It is anti-;
The determination unit is additionally operable to when first impedance meets preset condition, determines that first capacitance is described the
Deletion capacitance in power supply all the way, so that by deleting first capacitance in the first via power supply to the first via
Power supply carries out decoupling capacitor optimization.
8. device according to claim 7, which is characterized in that described device further includes:Acquiring unit, it is described for obtaining
The PCB is imported emulation tool by PCB;
The determination unit, for determining in the PCB at least ring of the coupled capacitor of power supply all the way by the emulation tool
Road inductance.
9. device according to claim 7, which is characterized in that the determination unit is specifically used for true by emulation tool
The model of the fixed PCB obtains predeterminated frequency range internal impedance size curve, according to the impedance according to the model of the PCB
Size curve determines the first impedance of the first via power supply after deleting first capacitance.
10. device according to any one of claims 7 to 9, which is characterized in that
The processing unit, for comparing first impedance and the target impedance of the first via power supply;
The determination unit when target impedance for being less than the first via power supply when first impedance, determines described the
One impedance meets preset condition.
11. device according to claim 8, which is characterized in that the acquiring unit, the power supply for obtaining the PCB
It distributes in network per the target impedance of power supply all the way.
12. device according to claim 7, which is characterized in that the determination unit, at least electric all the way described in determination
Per the deletion capacitance in power supply all the way in source, the PCB is gone by deleting the deletion capacitance per in power supply all the way
Coupling capacitance optimizes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710232092.XA CN108694262B (en) | 2017-04-11 | 2017-04-11 | Decoupling capacitor optimization method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710232092.XA CN108694262B (en) | 2017-04-11 | 2017-04-11 | Decoupling capacitor optimization method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108694262A true CN108694262A (en) | 2018-10-23 |
| CN108694262B CN108694262B (en) | 2023-09-29 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109526194A (en) * | 2018-11-29 | 2019-03-26 | 安徽江淮汽车集团股份有限公司 | A kind of reduction onboard instruments electromagnetic disturbance method |
| CN111563356A (en) * | 2020-04-21 | 2020-08-21 | 苏州浪潮智能科技有限公司 | PDN impedance flattening simulation method, device, equipment and medium |
| CN112231866A (en) * | 2019-06-28 | 2021-01-15 | 浙江宇视科技有限公司 | Capacitance selection method, device, server and medium for power distribution network |
| CN112668275A (en) * | 2020-12-31 | 2021-04-16 | 芯和半导体科技(上海)有限公司 | Method for searching optimal substitute target capacitance in given capacitance set |
| CN114580340A (en) * | 2022-03-01 | 2022-06-03 | 格兰菲智能科技有限公司 | Chip power supply decoupling simulation optimization method and device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1294365A (en) * | 1999-10-28 | 2001-05-09 | 日本电气株式会社 | Power source deoupling circuit design method |
| JP2001167139A (en) * | 1999-12-06 | 2001-06-22 | Nec Corp | Power source decouipling designing method and design support system |
| CN1858751A (en) * | 2005-11-08 | 2006-11-08 | 华为技术有限公司 | Method for printed circuit board power completeness simulation |
| CN101872377A (en) * | 2010-06-12 | 2010-10-27 | 清华大学 | Method for restraining integrated circuit electricity supply network noise by using decoupling capacitance |
| CN102419790A (en) * | 2012-01-04 | 2012-04-18 | 西安电子科技大学 | Quick capacitor select algorithm-based power distribution network design method |
| US8166447B1 (en) * | 2009-02-04 | 2012-04-24 | Altera Corporation | Power delivery network calculator tool for printed circuit board capacitors |
| CN103049586A (en) * | 2011-10-12 | 2013-04-17 | 无锡江南计算技术研究所 | Simulation method of power-supply distribution system and obtaining method of target impedance |
| CN104112048A (en) * | 2014-07-15 | 2014-10-22 | 西安电子科技大学 | Method for selecting decoupling capacitors from power supply distribution network on basis of maximum anti-resonance point |
| CN106156396A (en) * | 2015-04-24 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of Method and circuits structure detecting crystal-oscillator circuit whether starting of oscillation |
| CN106484946A (en) * | 2016-09-08 | 2017-03-08 | 西安电子科技大学 | Based on the PDN electric capacity optimization method that lossless resonator power supply ground level is modeled |
-
2017
- 2017-04-11 CN CN201710232092.XA patent/CN108694262B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1294365A (en) * | 1999-10-28 | 2001-05-09 | 日本电气株式会社 | Power source deoupling circuit design method |
| JP2001167139A (en) * | 1999-12-06 | 2001-06-22 | Nec Corp | Power source decouipling designing method and design support system |
| CN1858751A (en) * | 2005-11-08 | 2006-11-08 | 华为技术有限公司 | Method for printed circuit board power completeness simulation |
| US8166447B1 (en) * | 2009-02-04 | 2012-04-24 | Altera Corporation | Power delivery network calculator tool for printed circuit board capacitors |
| CN101872377A (en) * | 2010-06-12 | 2010-10-27 | 清华大学 | Method for restraining integrated circuit electricity supply network noise by using decoupling capacitance |
| CN103049586A (en) * | 2011-10-12 | 2013-04-17 | 无锡江南计算技术研究所 | Simulation method of power-supply distribution system and obtaining method of target impedance |
| CN102419790A (en) * | 2012-01-04 | 2012-04-18 | 西安电子科技大学 | Quick capacitor select algorithm-based power distribution network design method |
| CN104112048A (en) * | 2014-07-15 | 2014-10-22 | 西安电子科技大学 | Method for selecting decoupling capacitors from power supply distribution network on basis of maximum anti-resonance point |
| CN106156396A (en) * | 2015-04-24 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of Method and circuits structure detecting crystal-oscillator circuit whether starting of oscillation |
| CN106484946A (en) * | 2016-09-08 | 2017-03-08 | 西安电子科技大学 | Based on the PDN electric capacity optimization method that lossless resonator power supply ground level is modeled |
Non-Patent Citations (5)
| Title |
|---|
| 汪泉弟;王赢聪;高锋;: "电源分配网络阻抗分析及去耦电容优化" * |
| 沙斐: "多层印制电路板电源去耦的研究" * |
| 王腾飞: "基于电源完整性的去耦网络设计方法研究" * |
| 韦素芬;梁宇;: "深亚微米SOC设计的去耦电容优化方法学" * |
| 龚纯,陈伟,黄秋元: "去耦电容在高速电路EM C设计中的研究与应用" * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109526194A (en) * | 2018-11-29 | 2019-03-26 | 安徽江淮汽车集团股份有限公司 | A kind of reduction onboard instruments electromagnetic disturbance method |
| CN109526194B (en) * | 2018-11-29 | 2020-10-09 | 安徽江淮汽车集团股份有限公司 | Method for reducing electromagnetic disturbance of vehicle-mounted instrument |
| CN112231866A (en) * | 2019-06-28 | 2021-01-15 | 浙江宇视科技有限公司 | Capacitance selection method, device, server and medium for power distribution network |
| CN112231866B (en) * | 2019-06-28 | 2024-02-02 | 浙江宇视科技有限公司 | Capacitance selection method, device, server and medium of power distribution network |
| CN111563356A (en) * | 2020-04-21 | 2020-08-21 | 苏州浪潮智能科技有限公司 | PDN impedance flattening simulation method, device, equipment and medium |
| CN112668275A (en) * | 2020-12-31 | 2021-04-16 | 芯和半导体科技(上海)有限公司 | Method for searching optimal substitute target capacitance in given capacitance set |
| CN112668275B (en) * | 2020-12-31 | 2023-12-19 | 芯和半导体科技（上海）股份有限公司 | Method for searching optimal substitute target capacitance in given capacitance set |
| CN114580340A (en) * | 2022-03-01 | 2022-06-03 | 格兰菲智能科技有限公司 | Chip power supply decoupling simulation optimization method and device |
| CN114580340B (en) * | 2022-03-01 | 2023-11-28 | 格兰菲智能科技有限公司 | Chip power decoupling simulation optimization method and device |
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