CN108694262B - Decoupling capacitor optimization method and device - Google Patents
Decoupling capacitor optimization method and device Download PDFInfo
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Abstract
The embodiment of the invention discloses a decoupling capacitor optimization method, which is used for determining a first capacitor corresponding to the maximum loop inductance in a first power supply in a PCB (printed circuit board), wherein the PCB comprises at least one power supply, and the first power supply is any power supply in the at least one power supply; calculating a first impedance of the first power supply after deleting the first capacitor according to a model of the PCB; and when the first impedance meets a preset condition, determining the first capacitor as a deleted capacitor in the first path of power supply, so that decoupling capacitor optimization is performed on the first path of power supply by deleting the first capacitor in the first path of power supply. The embodiment of the invention also provides a decoupling capacitor optimizing device.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a decoupling capacitor optimization method and apparatus.
Background
With the development of ultra-large-scale integrated circuit technology, the channel size of the chip is inevitably further scaled down, the power supply voltage of the integrated circuit is continuously reduced, the ripple noise threshold and design margin of the chip are reduced, and the higher signal rate makes the power supply noise more sensitive to parasitic parameters such as package, printed circuit board (PCB, printed Circuit Board) routing, via hole and the like. Therefore, how to ensure that chips operate properly under different process, voltage, and temperature conditions, and under various traffic patterns, is a great challenge for power integrity design. The power integrity design needs to meet three targets, namely a chip level, and provides a clean and stable power supply for a chip; a single board layer provides a low-impedance and low-noise reference loop for signals, ensures impedance continuity and reduces crosstalk; at the system level, electromagnetic interference emissions are avoided, and power supply noise is used as an important component of electromagnetic interference (EMI, electromagnetic Interference) to analyze and suppress the electromagnetic interference.
The Power Distribution Network (PDN) is composed of a power ground wire, a plane and a decoupling capacitor, and the impedance of the power distribution network is not zero due to parasitic parameters such as parasitic resistance, inductance and capacitance, the resonance characteristic of the decoupling capacitor is needed to be utilized, the lowest input impedance is obtained through the parallel combination of capacitors with different capacitance values, the input impedance is lower than the target impedance, and the load chip is ensured to have stable and continuous power supply. However, in the prior art, in general, the capacitance and number of decoupling capacitors on a Power Distribution Network (PDN) are designed according to a main chip manufacturer reference, so long as the ac impedance and dc impedance simulation results of the respective power supplies are within the standard value range. In the existing project, the capacity and the number of the coupling capacitors around the chip are designed by referring to the chip manufacturer, the number of the coupling capacitors is more than that of the coupling capacitors, and the power ground wiring is designed according to the maximization of the layout area of the coupling capacitors, but the design occupies a large amount of area of a single board, and meanwhile, the cost is increased.
The decoupling capacitors in the prior art mainly comprise a big 'V', a Decade Methods method and a Flat response method, but the Methods have certain limitations, for example, the big 'V' method requires a plurality of capacitors with the same capacitance value in the design process, the redundancy quantity is large, and the layout area of a single board is increased; the Decade Methods and the Flat response Methods have limited number and types of capacitors, and are not necessarily capable of meeting the requirement of the target impedance of the power supply.
Disclosure of Invention
In order to solve the existing technical problems, the embodiment of the invention provides a decoupling capacitor optimization method and device, which are used for reasonably arranging the capacitance values and the quantity of capacitors on the basis of ensuring impedance, reducing layout space and saving cost.
In order to achieve the above object, the technical solution of the embodiment of the present invention is as follows:
the embodiment of the invention provides a decoupling capacitor optimization method, which comprises the following steps:
determining a first capacitor corresponding to a maximum loop inductance in a first power supply in a Printed Circuit Board (PCB), wherein the PCB comprises at least one power supply, and the first power supply is any power supply in the at least one power supply;
calculating a first impedance of the first power supply after deleting the first capacitor according to a model of the PCB;
and when the first impedance meets a preset condition, determining the first capacitor as a deleted capacitor in the first path of power supply, so that decoupling capacitor optimization is performed on the first path of power supply by deleting the first capacitor in the first path of power supply.
Further, before determining the first capacitor corresponding to the maximum loop inductance in the first path of power supply in the printed circuit board PCB, the method further includes:
and acquiring the PCB, guiding the PCB into a simulation tool, and determining the loop inductance of the coupling capacitance of at least one power supply in the PCB through the simulation tool.
Further, the calculating, according to a preset model, the first impedance of the first path of power supply after the first capacitor is deleted includes:
and determining a model of the PCB through a simulation tool, obtaining an impedance magnitude curve in a preset frequency range according to the model of the PCB, and determining a first impedance of the first path of power supply after deleting the first capacitor according to the impedance magnitude curve.
Further, before determining that decoupling capacitance optimization is performed on the first path power supply by deleting the first capacitance in the first path power supply when the first impedance meets a preset condition, the method further includes:
comparing the first impedance with a target impedance of the first path of power supply;
and when the first impedance is smaller than the target impedance of the first path of power supply, determining that the first impedance meets a preset condition.
Further, before the obtaining the PCB, the method includes:
and obtaining the target impedance of each power supply in the power supply distribution network of the PCB.
Further, after determining that the first capacitor is the deleted capacitor in the first path of power supply when the first impedance meets a preset condition, the method further includes:
determining the deleting capacitance in each power supply in the at least one power supply, and optimizing the decoupling capacitance of the PCB by deleting the deleting capacitance in each power supply.
The embodiment of the invention provides a decoupling capacitor optimizing device, which comprises the following components: a determining unit, a processing unit, wherein,
the determining unit is used for determining a first capacitor corresponding to the maximum loop inductance in a first path of power supply in a Printed Circuit Board (PCB), wherein the PCB comprises at least one path of power supply, and the first path of power supply is any path of power supply in the at least one path of power supply;
the processing unit is used for calculating first impedance of the first path of power supply after deleting the first capacitor according to the model of the PCB;
and the determining unit is further configured to determine that the first capacitor is a deleted capacitor in the first path of power supply when the first impedance meets a preset condition, so that decoupling capacitor optimization is performed on the first path of power supply by deleting the first capacitor in the first path of power supply.
Further, the apparatus further comprises: the acquisition unit is used for acquiring the PCB and guiding the PCB into a simulation tool;
and the determining unit is used for determining loop inductance of coupling capacitance of at least one power supply in the PCB through the simulation tool.
Further, the determining unit is specifically configured to determine, by using a simulation tool, a model of the PCB, obtain an impedance magnitude curve in a preset frequency range according to the model of the PCB, and determine, according to the impedance magnitude curve, a first impedance of the first power supply after the first capacitor is deleted.
Further, the processing unit is configured to compare the first impedance with a target impedance of the first path of power supply;
the determining unit is configured to determine that the first impedance meets a preset condition when the first impedance is smaller than a target impedance of the first path of power supply.
Further, the obtaining unit is configured to obtain a target impedance of each power supply in the power distribution network of the PCB.
Further, the determining unit is configured to determine a deletion capacitance in each power supply of the at least one power supply, and optimize the decoupling capacitance of the PCB by deleting the deletion capacitance in each power supply.
The embodiment of the invention provides a decoupling capacitor optimization method and a decoupling capacitor optimization device, which are used for determining a first capacitor corresponding to the maximum loop inductance in a first power supply in a Printed Circuit Board (PCB), wherein the PCB comprises at least one power supply, and the first power supply is any power supply in the at least one power supply; calculating a first impedance of the first power supply after deleting the first capacitor according to a model of the PCB; and when the first impedance meets a preset condition, determining the first capacitor as a deleted capacitor in the first path of power supply, so that decoupling capacitor optimization is performed on the first path of power supply by deleting the first capacitor in the first path of power supply. According to the decoupling capacitor optimization method and device provided by the embodiment of the invention, the coupling capacitor with relatively large loop inductance and relatively far layout position from the power supply corresponding to the chip is removed while the target impedance of the power supply distribution network PDN of the PCB is ensured, so that the overall loop inductance on the power supply distribution network is reduced, the layout space of the PCB is reduced, and the cost is saved.
Drawings
In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.
Fig. 1 is a schematic flow chart of a decoupling capacitor optimization method according to an embodiment of the present invention;
FIG. 2 is a diagram showing an equivalent circuit according to an embodiment of the present invention;
FIG. 3 is a diagram showing an equivalent circuit example according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of a decoupling capacitor optimization method according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating an example loop inductance provided in an embodiment of the present invention;
FIG. 6 is an exemplary graph of an impedance curve provided by an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a decoupling capacitor optimizing device according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a decoupling capacitor optimizing device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
An embodiment of the present invention provides a decoupling capacitor optimization method, as shown in fig. 1, where the method includes:
step 101, determining a first capacitor corresponding to a maximum loop inductance in a first path of power supply in the PCB.
The PCB comprises at least one power supply, and the first power supply is any power supply in the at least one power supply.
The main execution body of the decoupling capacitor optimization method provided by the embodiment of the invention is a decoupling capacitor optimization device, namely the decoupling capacitor optimization device determines a first capacitor corresponding to the maximum loop inductance in a first path of power supply in a Printed Circuit Board (PCB).
The PCB (Printed Circuit Board) Chinese name printed circuit board, also called printed circuit board, is an important electronic component, is a support for electronic components, and is a carrier for electrical connection of electronic components. It is called a "printed" circuit board because it is made using electronic printing.
Further, before determining the first capacitor corresponding to the maximum loop inductance in the first path of power supply in the printed circuit board PCB, the method may further include:
and obtaining the target impedance of each power supply in the power supply distribution network of the PCB.
Where a Power Distribution Network (PDN) refers to a path or interconnect from a power supply (VRM) to an active device (IC), its impedance includes the active internal resistance itself, the PCB routing, decoupling capacitance, and impedance on the IC package.
As shown in fig. 2, the right diagram in fig. 2 is a simplified equivalent circuit diagram of the left diagram, AB is an impedance observation point, that is, a power supply and a ground point on the target IC, a network between the two points AB is equivalent to a current source, Z is an output impedance thereof, and the magnitude of Z determines the magnitude of power supply noise of the chip. For a stable power supply system, no matter how the load transient current between the two points AB changes, the voltage change range between the two points AB needs to be ensured to be small, so that the impedance Z of the power supply system needs to be low enough, the impedance design of PDN needs the resonance characteristic of decoupling capacitors, and the lowest input impedance is obtained through the parallel combination of the capacitors.
From fig. 2, it can be derived that: Δv (ω) =z (ω) ×Δi (ω)
Where DeltaV (ω) is voltage, Z is impedance, deltaI is current.
Equivalent z=esr+j2pi×esl+1/(j2pi f×c)
Wherein ESR is equivalent resistance, ESL is equivalent inductance, and C is capacitance value.
For a PCB of an actual project, a target impedance formula is difficult to be cited in practice, because the current and the frequency range on the PCB are difficult to be determined, and there is no clear correspondence with the frequency, in the actual project, a chip manufacturer generally clearly gives a target impedance value of the PCB level of the IC chip, where the calculation formula of the target impedance is as follows:
in the actual optimization process, the PCB after the optimization design needs to be ensured to be in the range of target impedance through simulation.
The capacitor is the most important power supply impedance control optimizing device, the decoupling capacitor is welded on the PCB, and besides the equivalent resistance ESR and equivalent inductance ESL of the capacitor, additional parasitic parameters are introduced due to wiring, via holes, bonding pads, welding and the like, and influence the resonance frequency of the capacitor together with the parasitic parameters of the capacitor, so that the action range of the capacitor is influenced.
As shown in fig. 3, the right diagram in fig. 3 is a simplified equivalent circuit diagram of the left diagram, and the parasitic inductance is the foremost of the additional parasitic parameters introduced, and can be equivalently the effective loop inductance in the diagram. The effective loop inductance Lpcb1 weakens the decoupling effect of Cde-cap on both Pwr and Gnd, while the effective loop inductance (Lpcb+Lpcb 1) weakens the decoupling effect of Cbulk on both Pwr and Gnd. It is clear from this that the magnitude of the loop inductance directly influences the decoupling effect of the capacitor.
The core of the invention is to control the loop inductance of the decoupling capacitor, determine the loop inductance of the decoupling capacitor through simulation, determine the capacitor with larger loop inductance, remove the coupling capacitor with larger loop inductance and farther layout position from the power PIN PIN corresponding to the MSM chip, change the capacitance value of the capacitor with inferior loop inductance, reduce the overall loop inductance on the power distribution network, and adjust the size and quantity of the capacitor on each power supply in a targeted way, so as to achieve the purposes of saving cost and reducing layout area.
And 102, calculating the first impedance of the first power supply after deleting the first capacitor according to the model of the PCB.
Specifically, a model of the PCB is determined through a simulation tool, an impedance magnitude curve in a preset frequency range is obtained according to the model of the PCB, and a first impedance of the first path of power supply after the first capacitor is deleted is determined according to the impedance magnitude curve.
And 103, when the first impedance meets a preset condition, determining that the first capacitor is a deleted capacitor in the first path of power supply, so that decoupling capacitor optimization is performed on the first path of power supply by deleting the first capacitor in the first path of power supply.
Specifically, when the first impedance is smaller than the target impedance of the first path of power supply, determining that the first impedance meets a preset condition, and determining that the first capacitor is a deleted capacitor in the first path of power supply.
Optionally, before determining that the decoupling capacitance of the first path power supply is optimized by deleting the first capacitance in the first path power supply when the first impedance meets a preset condition, the method further includes:
comparing the first impedance with a target impedance of the first path of power supply;
and when the first impedance is smaller than the target impedance of the first path of power supply, determining that the first impedance meets a preset condition.
Optionally, after determining that the first capacitor is the deleted capacitor in the first path power supply when the first impedance meets a preset condition, the method further includes:
determining the deleting capacitance in each power supply in the at least one power supply, and optimizing the decoupling capacitance of the PCB by deleting the deleting capacitance in each power supply.
According to the decoupling capacitor optimization method provided by the embodiment of the invention, the coupling capacitor with relatively large loop inductance and relatively far layout position from the power supply corresponding to the chip is removed while the target impedance of the power supply distribution network PDN of the PCB is ensured, so that the overall loop inductance on the power supply distribution network is reduced, the layout space of the PCB is reduced, and the cost is saved.
The embodiment of the invention provides a decoupling capacitor optimization method, as shown in fig. 4, which comprises the following steps:
step 201, a decoupling capacitor optimizing device obtains target impedance of each power supply in a power supply distribution network of a PCB.
The Power Distribution Network (PDN) sets a target impedance of the power distribution network provided by a chip manufacturer as a reference standard through frequency domain analysis, and the target impedance design method of the Power Distribution Network (PDN) requires that the input impedance is smaller than the target impedance in a frequency range of interest from the IC perspective, that is, the power distribution network exhibits a low impedance characteristic, and reduces the input impedance of the PDN by using the characteristic that the antiresonance point impedance of the decoupling capacitor is minimum.
Specifically, the power distribution network of the PCB includes multiple power supplies, and the target impedance of each power supply in the Power Distribution Network (PDN) is determined according to the data provided by the main chip manufacturer of the PCB, which is used as a reference standard for comparison.
Step 202, a decoupling capacitor optimizing device acquires the PCB, the PCB is led into a simulation tool, and loop inductance of coupling capacitors of at least one power supply in the PCB is determined through the simulation tool.
Step 203, the decoupling capacitor optimizing device determines a first capacitor corresponding to the maximum loop inductance in the first path of power supply in the PCB.
The PCB comprises at least one power supply, and the first power supply is any power supply in the at least one power supply.
Specifically, after the PCB is designed, a simulation tool is introduced, a stack layer of the PCB and a capacitance model are set according to design requirements, loop inductance of coupling capacitance of each path of power supply is calculated, data shown in table 1 below can be clearly and intuitively checked through the simulation tool, as shown in fig. 5, the magnitude of each coupling capacitance on the power supply is shown on a bar column, distribution of coupling capacitance with large loop inductance on the PCB can be seen according to simulation of the simulation tool, placement position and distance of the loop inductance and a load are seen, and in combination of the two parts, the smaller the decoupling capacitance value is, the smaller the loop inductance is required to be placed, the higher the frequency of action is, the larger the capacitance value is, the larger the loop inductance is placed at a place with a larger distance from the load, the lower the frequency of action is, the coupling capacitance with a large loop inductance and a distance from the load is deleted, and meanwhile, the capacitance value of the coupling capacitance with a small loop inductance is modified.
TABLE 1
| Capacitance device | Loop inductance (nH) to main chip |
| C1101 | 0.41 |
| C1102 | 0.14 |
| C1103 | 0.29 |
| C1104 | 0.3 |
| C1105 | 0.38 |
| C1106 | 0.17 |
| C1107 | 0.33 |
| C1108 | 0.31 |
| C1109 | 0.45 |
| C1110 | 0.31 |
| C1112 | 0.19 |
| C1113 | 0.38 |
| C1114 | 0.33 |
| C1140 | 0.22 |
| C1141 | 0.25 |
| C2313 | 0.37 |
And 204, calculating the first impedance of the first power supply after deleting the first capacitor by the decoupling capacitor optimizing device according to the model of the PCB.
Step 205, the decoupling capacitor optimizing device compares the first impedance with the target impedance of the first path of power supply.
And 206, when the first impedance is smaller than the target impedance of the first path of power supply, determining that the first impedance meets a preset condition by the decoupling capacitor optimizing device, and determining that the first capacitor is a deleted capacitor in the first path of power supply.
Specifically, a snp model of the PCB is provided by a simulation tool, the impedance magnitude is calculated, an impedance magnitude curve in a certain frequency range is obtained, an impedance curve shown in fig. 6 is obtained, the impedance magnitude of a corresponding frequency band is found, the impedance magnitude is compared with a target impedance under the corresponding frequency, whether enough redundancy exists in the range or not is judged, and if enough, a modified measure is adopted.
Step 207, a decoupling capacitor optimizing device determines a deletion capacitor in each power supply of the at least one power supply, and optimizes the decoupling capacitor of the PCB by deleting the deletion capacitor in each power supply.
Specifically, the decoupling capacitor optimizing device sequentially adopts a corresponding optimizing method for other power supplies, and finally determines the numerical value and the number of the decoupling capacitors, so that the purpose of optimizing the decoupling capacitors is achieved, and curve comparison is optimized.
According to the decoupling capacitor optimization method provided by the embodiment of the invention, the coupling capacitor with relatively large loop inductance and relatively far layout position from the power supply corresponding to the chip is removed while the target impedance of the power supply distribution network PDN of the PCB is ensured, so that the overall loop inductance on the power supply distribution network is reduced, the layout space of the PCB is reduced, and the cost is saved.
An embodiment of the present invention provides a decoupling capacitor optimizing device 30, as shown in fig. 7, including: a determining unit 301, a processing unit 302, wherein,
the determining unit 301 is configured to determine a first capacitor corresponding to a maximum loop inductance in a first power supply of a printed circuit board PCB, where the PCB includes at least one power supply, and the first power supply is any one power supply of the at least one power supply;
the processing unit 302 is configured to calculate, according to a model of the PCB, a first impedance of the first power supply after the first capacitor is deleted;
the determining unit 301 is further configured to determine that the first capacitor is a deleted capacitor in the first power supply when the first impedance meets a preset condition, so that decoupling capacitance optimization is performed on the first power supply by deleting the first capacitor in the first power supply.
Optionally, as shown in fig. 8, the apparatus further includes: an obtaining unit 303, configured to obtain the PCB and import the PCB into a simulation tool;
the determining unit 301 is configured to determine, by using the simulation tool, a loop inductance of a coupling capacitance of at least one power supply in the PCB.
Optionally, the determining unit 301 is specifically configured to determine, by using a simulation tool, a model of the PCB, obtain an impedance magnitude curve in a preset frequency range according to the model of the PCB, and determine, according to the impedance magnitude curve, a first impedance of the first power supply after the first capacitor is deleted.
Optionally, the processing unit 302 is configured to compare the first impedance with a target impedance of the first power supply;
the determining unit 301 is configured to determine that the first impedance meets a preset condition when the first impedance is smaller than a target impedance of the first path of power supply.
Optionally, the obtaining unit 303 is configured to obtain a target impedance of each power supply in the power distribution network of the PCB.
Optionally, the determining unit 301 is configured to determine a deletion capacitance in each of the at least one power supply, and optimize the decoupling capacitance of the PCB by deleting the deletion capacitance in each of the at least one power supply.
Specifically, the decoupling capacitor optimizing device provided in the embodiment of the present invention may refer to the description of the decoupling capacitor optimizing method embodiment, and the embodiment of the present invention is not repeated here.
According to the decoupling capacitor optimizing device provided by the embodiment of the invention, the target impedance of the power distribution network PDN of the PCB is ensured, and meanwhile, the coupling capacitor with relatively large loop inductance and relatively far layout position from the power supply corresponding to the chip is removed, so that the overall loop inductance on the power distribution network is reduced, the layout space of the PCB is reduced, and the cost is saved.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention.
Claims (12)
1. A method of optimizing decoupling capacitance, the method comprising:
determining a first capacitor corresponding to the largest loop inductance in a first power supply in a Printed Circuit Board (PCB), wherein the PCB comprises at least one power supply, and the first power supply is any power supply in the at least one power supply;
calculating a first impedance of the first power supply after deleting the first capacitor according to a model of the PCB;
when the first impedance is smaller than the target impedance of the first path of power supply, determining that the first impedance meets a preset condition, and determining that the first capacitor is a deleted capacitor in the first path of power supply, so that decoupling capacitor optimization is performed on the first path of power supply by deleting the first capacitor in the first path of power supply.
2. The method of claim 1, wherein prior to determining the first capacitance corresponding to the largest loop inductance in the first power supply of the printed circuit board PCB, the method further comprises:
and acquiring the PCB, guiding the PCB into a simulation tool, and determining the loop inductance of the coupling capacitance of at least one power supply in the PCB through the simulation tool.
3. The method of claim 1, wherein calculating the first impedance of the first power supply with the first capacitor removed according to the model of the PCB comprises:
and determining a model of the PCB through a simulation tool, obtaining an impedance magnitude curve in a preset frequency range according to the model of the PCB, and determining a first impedance of the first path of power supply after deleting the first capacitor according to the impedance magnitude curve.
4. A method according to any one of claims 1 to 3, wherein, before determining that the first impedance satisfies a preset condition when the first impedance is smaller than a target impedance of the first power supply, determining that decoupling capacitance of the first power supply is optimized by deleting the first capacitance in the first power supply, the method further comprises:
comparing the first impedance with a target impedance of the first path of power supply;
and when the first impedance is smaller than the target impedance of the first path of power supply, determining that the first impedance meets a preset condition.
5. The method of claim 2, comprising, prior to said acquiring said PCB:
and obtaining the target impedance of each power supply in the power supply distribution network of the PCB.
6. The method of claim 1, wherein after determining that the first capacitance is a deleted capacitance in the first power supply when the first impedance satisfies a preset condition, the method further comprises:
determining the deleting capacitance in each power supply in the at least one power supply, and optimizing the decoupling capacitance of the PCB by deleting the deleting capacitance in each power supply.
7. A decoupling capacitance optimization apparatus, the apparatus comprising: a determining unit, a processing unit, wherein,
the determining unit is used for determining a first capacitor corresponding to the largest loop inductance in a first path of power supply in a Printed Circuit Board (PCB), wherein the PCB comprises at least one path of power supply, and the first path of power supply is any path of power supply in the at least one path of power supply;
the processing unit is used for calculating first impedance of the first path of power supply after deleting the first capacitor according to the model of the PCB;
the determining unit is further configured to determine that the first impedance meets a preset condition when the first impedance is smaller than a target impedance of the first power supply, and determine that the first capacitor is a deleted capacitor in the first power supply, so that decoupling capacitance optimization is performed on the first power supply by deleting the first capacitor in the first power supply.
8. The apparatus of claim 7, wherein the apparatus further comprises: the acquisition unit is used for acquiring the PCB and guiding the PCB into a simulation tool;
and the determining unit is used for determining loop inductance of coupling capacitance of at least one power supply in the PCB through the simulation tool.
9. The apparatus according to claim 7, wherein the determining unit is specifically configured to determine, by using a simulation tool, a model of the PCB, obtain an impedance magnitude curve in a preset frequency range according to the model of the PCB, and determine, according to the impedance magnitude curve, a first impedance of the first power supply after the first capacitor is deleted.
10. The device according to any one of claims 7 to 9, wherein,
the processing unit is used for comparing the first impedance with the target impedance of the first path of power supply;
the determining unit is configured to determine that the first impedance meets a preset condition when the first impedance is smaller than a target impedance of the first path of power supply.
11. The apparatus of claim 8, wherein the obtaining unit is configured to obtain a target impedance of each power supply in the power distribution network of the PCB.
12. The apparatus of claim 7, wherein the determining unit is configured to determine a deletion capacitance in each of the at least one power supply, and to optimize the decoupling capacitance of the PCB by deleting the deletion capacitance in each of the at least one power supply.
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| CN112231866B (en) * | 2019-06-28 | 2024-02-02 | 浙江宇视科技有限公司 | Capacitance selection method, device, server and medium of power distribution network |
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