CN108631583B - Layout method of multiphase DC-DC power module and power module thereof - Google Patents
Layout method of multiphase DC-DC power module and power module thereof Download PDFInfo
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- CN108631583B CN108631583B CN201810524028.3A CN201810524028A CN108631583B CN 108631583 B CN108631583 B CN 108631583B CN 201810524028 A CN201810524028 A CN 201810524028A CN 108631583 B CN108631583 B CN 108631583B
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- 230000001939 inductive effect Effects 0.000 abstract 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
Abstract
The embodiment of the application provides a layout method of a multi-phase DC-DC power supply module, which comprises the following steps: determining a first phase MOS bonding pad position and a first phase MOS ground bonding pad position; determining a first isolation region corresponding to a first-phase MOS power supply according to the position and the size of a first-phase MOS bonding pad, placing a first inductance input bonding pad in the first isolation region, and determining a first inductance output bonding pad according to the first inductance input bonding pad; two rows of power supply through holes are respectively arranged on the upper side and the lower side of the first inductance output bonding pad, and the two rows of power supply through holes are arranged in a staggered mode; placing a first large-capacity capacitor power supply bonding pad under two rows of power supply through holes on the lower side of the first inductor output bonding pad, and determining the position of the first large-capacity capacitor ground bonding pad; arranging two rows of power supply through holes on the lower side of the first large-capacity capacitor power supply bonding pad, wherein the two rows of power supply through holes are arranged in a staggered manner; arranging a second inductance output bonding pad on the lower side of the first large-capacity capacitance power supply bonding pad, and determining a second inductance input bonding pad; a second phase MOS pad position and a second phase MOS ground pad position are determined from the second inductive input pad.
Description
Technical Field
The present application relates to the field of power supply, and more particularly, to a layout method of a multi-phase DC-DC power module and a power module thereof.
Background
With the rapid development of the internet and big data and the coming of the cloud computing era, cloud computing centers and big data centers are rapidly developed and grown, and the demand and the use of servers and storage are more and more. The server and the storage are used as supports for cloud computing and data processing and storage of big data, and the stability of the whole system is directly determined.
As the functional requirements of the server and the storage design become more and more, the design of the Printed Circuit Board (PCB) becomes more and more complex, especially for the PCB power supply design, and the increasing current requirement thereof brings new challenges to the power supply design of the PCB. How to design a power supply meeting requirements in a limited PCB space and to enable the power supply to work stably is called one of the major research directions of subsequent power supply design.
Therefore, a layout method of a multi-phase direct current to direct current (DC-DC) power module is needed.
Disclosure of Invention
The application provides a layout method of a DC-DC power supply module, which can improve the working stability of the power supply module.
In a first aspect, a method for layout of a multiphase DC-DC power module is provided, the method comprising: determining a first phase MOS bonding pad position and a first phase MOS ground bonding pad position; determining a first isolation region corresponding to the first-phase MOS power supply according to the position and the size of the first-phase MOS bonding pad, placing a first inductance input bonding pad in the first isolation region, and determining a first inductance output bonding pad according to the first inductance input bonding pad; two rows of power supply through holes are respectively arranged on the upper side and the lower side of the first inductance output bonding pad, and the two rows of power supply through holes are arranged in a staggered mode; placing a first large-capacity capacitance power supply bonding pad under two rows of power supply through holes at the lower side of the first inductance output bonding pad, and determining the position of the first large-capacity capacitance ground bonding pad; arranging two rows of power supply through holes on the lower side of the first large-capacity capacitor power supply bonding pad, wherein the two rows of power supply through holes are arranged in a staggered manner; arranging a second inductance output bonding pad on the lower side of the first large-capacity capacitance power supply bonding pad, and determining the second inductance input bonding pad; and determining a second phase MOS bonding pad position and a second phase MOS grounding bonding pad position according to the second inductance input bonding pad.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the method further includes: and determining the positions of a power supply bonding pad of a second large-capacity capacitor and a ground bonding pad of the second large-capacity capacitor according to the position of the second phase MOS bonding pad.
With reference to the first aspect and the foregoing implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the method further includes: determining a third inductance input bonding pad and a third inductance output bonding pad according to the positions of the second large-capacity power supply bonding pad and the second large-capacity capacitance ground bonding pad; determining the position of a third phase MOS bonding pad and the position of a third phase MOS ground bonding pad according to the third inductance input bonding pad and the third inductance output bonding pad; and determining the power supply pad position of a third large-capacity capacitor and the ground pad position of the third large-capacity capacitor according to the third phase MOS pad position and the third phase MOS ground pad position.
With reference to the first aspect and the foregoing implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the method further includes:
and arranging power supply bonding pads of a fourth large-capacity capacitor on the two rows of power supply through holes on the upper side of the first inductance output bonding pad, and determining the positions of the ground bonding pads of the fourth large-capacity capacitor.
With reference to the first aspect and the foregoing implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the method further includes: and a row of three power supply through holes are arranged below the power supply bonding pad of the third large-capacity capacitor, and a row of 3 power supply through holes are arranged above the power supply bonding pad of the fourth large-capacity capacitor.
In a second aspect, a multi-line DC-DC power module is provided, where the power module includes a ground plane PCB board and a power plane PCB board, and the ground plane PCB board is at least used for placing a first-phase MOS pad and a first-phase MOS ground pad, a first inductance input pad, a first large-capacity capacitance ground pad, a second-phase MOS pad and a second-phase MOS ground pad, a second inductance input pad, a second large-capacity capacitance ground pad, a third-phase MOS pad and a third-phase MOS ground pad, a third inductance input pad, a third large-capacity capacitance ground pad, and a fourth large-capacity capacitance ground pad; the power plane PCB board is at least used for placing a first inductance output bonding pad, a first large-capacity capacitance power bonding pad, a second inductance output bonding pad, a second large-capacity capacitance power bonding pad, a third inductance output bonding pad, a third large-capacity capacitance power bonding pad and a fourth large-capacity capacitance power bonding pad; the first-phase MOS ground pad is adjacent to the first inductance input pad, the second-phase MOS ground pad is adjacent to the second inductance input pad, the third-phase MOS ground pad is adjacent to the third inductance input pad, two rows of power supply through holes are formed between the first inductance output pad and the first large-capacity capacitance power supply pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode; two rows of power supply through holes are formed between the first large-capacity capacitor power supply bonding pad and the second inductor output bonding pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode; two rows of power supply through holes are formed between the second inductance output bonding pad and the second large-capacity capacitance power supply bonding pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode; two rows of power supply through holes are formed between the second large-capacity capacitor power supply bonding pad and the third inductor output bonding pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode; two rows of power supply through holes are formed between the third inductance output bonding pad and the third large-capacity capacitance power supply bonding pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode; two rows of power supply through holes are formed between the first inductance output bonding pad and the fourth large-capacity capacitance power supply bonding pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode.
With reference to the second aspect, in a first possible implementation manner of the second aspect, there are 3 power vias above the fourth large-capacity capacitor power pad; and 3 power supply through holes are formed below the third large-capacity capacitor power supply pad.
With reference to the second aspect and the foregoing implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the ground vias on the ground plane PCB are arranged in a staggered manner.
With reference to the second aspect and the foregoing implementation manner, in a third possible implementation manner of the second aspect, the power plane PCB is further configured to place at least a first small-capacity capacitive power pad, a first small-capacity capacitive ground pad, a second small-capacity capacitive power pad, a second small-capacity capacitive ground pad, a third small-capacity capacitive power pad, a third small-capacity capacitive ground pad, a fourth small-capacity capacitive power pad, a fourth small-capacity capacitive ground pad, a fifth small-capacity capacitive power pad, and a fifth small-capacity capacitive ground pad; a power supply through hole between the first inductance output bonding pad and the fourth large-capacity capacitance power supply bonding pad is adjacent to the first small-capacity capacitance power supply bonding pad, and two power supply through holes are arranged on two sides of the first small-capacity capacitance ground bonding pad; a power supply through hole between the first inductance output bonding pad and the first large-capacity capacitance power supply bonding pad is adjacent to the second small-capacity capacitance power supply bonding pad, and two power supply through holes are arranged on two sides of the second small-capacity capacitance ground bonding pad; a power supply through hole between the second inductance output bonding pad and the first large-capacity capacitance power supply bonding pad is adjacent to a third small-capacity capacitance power supply bonding pad, and two power supply through holes are arranged on two sides of the third small-capacity capacitance ground bonding pad; a power supply through hole between the second inductance output bonding pad and the second large-capacity capacitance power supply bonding pad is adjacent to the fourth small-capacity capacitance power supply bonding pad, and two power supply through holes are arranged on two sides of the fourth small-capacity capacitance ground bonding pad; and a power supply through hole between the third inductance output bonding pad and the second large-capacity capacitance power supply bonding pad is adjacent to the fifth small-capacity capacitance power supply bonding pad, and two power supply through holes are arranged on two sides of the fifth small-capacity capacitance ground bonding pad.
The application may have the following beneficial effects:
1. the layout of the output end of the multi-phase DC-DC power supply can bring corresponding power supply design improvement after the layout is applied.
2. By the aid of the staggered arrangement method of the through holes at the inductor output end, current passing through each through hole is more uniform, and the risk of bursting of the through holes is effectively avoided.
And 3, through hole arrangement of the MOS ground bonding pads and through hole arrangement of the ground of the ground plane, the current of the through holes is more uniform. .
4. The position of the large-capacity capacitor is just in the middle of the through holes on the two sides of the inductance bonding pad, and the design avoids the risk that a power supply or a ground plane is penetrated by the through holes in a large scale.
5. And at the position of the small-capacity capacitor, the capacitor shares an output through hole of the inductor, and the through hole does not need to be punched again at the position of the capacitor power supply pad.
6. The through hole, the electric capacity pad, the through hole, the inductance pad, the through hole, the electric capacity pad, the arrangement of through hole, more reasonable overall arrangement space.
Drawings
Fig. 1 shows a schematic diagram of a prior art multi-phase DC-DC module placement and routing scheme.
Fig. 2 is a schematic flow chart of a method of an embodiment of the present application.
Fig. 3 shows a schematic diagram of a power supply module of another embodiment of the present application.
Detailed Description
The technical solution in the present application will be described below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a conventional multi-phase DC-DC layout scheme. The layout and wiring of the inductor input end, the inductor output end, the small-capacity capacitor, the large-capacity capacitor and the via hole are shown in the figure, wherein the via hole, the large-capacity capacitor, the small-capacity capacitor and the like are not fixed and can be placed only according to the space.
The capacitor can not play the due maximum role according to the spatial arrangement, the through holes can cause the passing current of each through hole to be uneven according to the existing spatial arrangement, and the through holes can be burnt out due to overheating seriously.
The vias fill the entire current path, which can cause the power and ground planes on the inner layers of the PCB to be interrupted by the vias, thereby affecting the current flow in the power circuit.
In order to solve the above problem, an embodiment of the present application proposes a layout method of a multi-phase DC-DC power module, as shown in fig. 2, the method includes:
It should be understood that the first and second mentioned in the embodiments of the present application are only for distinguishing different capacitors, inductors, and the like, and the order is not limited.
Optionally, as an embodiment of the present application, the method further includes: and determining the positions of a power supply bonding pad of a second large-capacity capacitor and a ground bonding pad of the second large-capacity capacitor according to the position of the second phase MOS bonding pad.
Optionally, as an embodiment of the present application, the method further includes: determining a third inductance input bonding pad and a third inductance output bonding pad according to the positions of the second large-capacity power bonding pad and the second large-capacity ground bonding pad; determining the position of the third phase MOS bonding pad and the position of the third phase MOS ground bonding pad according to the third inductance input bonding pad and the third inductance output bonding pad; and determining the power supply pad position of a third large-capacity capacitor and the ground pad position of the third large-capacity capacitor according to the third phase MOS pad position and the third phase MOS ground pad position.
Optionally, as an embodiment of the present application, the method further includes: and arranging power supply bonding pads of a fourth large-capacity capacitor on the two rows of power supply through holes on the upper side of the first inductance output bonding pad, and determining the positions of the ground bonding pads of the fourth large-capacity capacitor.
Optionally, as an embodiment of the present application, the method further includes: and a row of three power supply through holes are arranged below the power supply bonding pad of the third large-capacity capacitor, and a row of 3 power supply through holes are arranged above the power supply bonding pad of the fourth large-capacity capacitor.
That is to say, the method provided by the embodiment of the application can reasonably arrange and evaluate the capacitor, the inductor, the via hole and the like in advance, and reasonably arrange the capacitor according to the arrangement evaluation result, so that the capacitor is arranged at the position with the optimal effect on the circuit. Meanwhile, the positions of the via holes are reasonably arranged according to the evaluation result, so that the via holes are reasonably distributed, and the area of other layers of the PCB perforated by the via holes is reduced as much as possible, so that more current paths are provided for current. The current of the via hole is uniformly distributed as much as possible, and the problem of via hole bursting caused by nonuniform current is prevented. Thereby improving the stability of the power supply system.
Fig. 3 shows a schematic diagram of a power supply module of another embodiment of the present application.
The layout and wiring diagram is shown. The inductor mainly comprises a power plane, a power via hole, a small-capacity capacitor (comprising a small-capacity capacitor ground pad and a small-capacity capacitor power pad), a large-capacity capacitor (comprising a large-capacity capacitor ground pad (5,6,7,8) and a large-capacity capacitor power pad (1,2,3,4)), an inductor (comprising an inductor input end pad (12,13,14) and an inductor output end pad (9,10,11)), a ground plane, an MOS ground pad, a ground via hole, an MOS pad (15,16,17) connected with an inductor input end, an isolation region and the like.
The layout and wiring implementation mode is as follows:
in the layout of the PCB designed by the multi-phase DC-DC power supply, the position of one of the phase power supply MOS is determined, and after the MOS position corresponding to the MOS pad 15 shown in fig. 3 is determined, the positions of the MOS ground pads and the like are fixed, a copper-laying space within the isolation region is designed in the region corresponding to 15 according to the size of the inductor pad used for design, and then the inductor input pad 12 is placed in the middle of the region, and the position of the inductor output pad 9 is also fixed.
2 rows of power supply through holes are drilled below the bonding pad 9, the positions of the two rows of through holes are staggered, the middle position of two through holes close to the bonding pad 9 corresponds to one through hole of the other row, and therefore currents passing through the two rows of through holes are relatively uniform, and the reliability of the power supply through holes is improved.
After the via hole below the inductance pad 9 is determined, the capacitors corresponding to the pads 2 and 6 are placed in the position shown in the figure, the distance between two rows of via holes is reserved below the pad 2, and the inductors corresponding to the inductance pads 10 and 13 are placed. After the position of the inductor is determined, two rows of through holes are respectively punched on the upper part and the lower part of the bonding pad 10, and the through holes are arranged in a staggered manner.
Then, according to the positions corresponding to 13 and 16, the MOS corresponding to the bonding pad 16 is placed. Placing the bonding pads 3 and 7 corresponding to capacitors, the bonding pads 11 and 14 corresponding to inductors, the bonding pad 17 corresponding to MOS, the bonding pads 4 and 8 corresponding to capacitors, and the bonding pads 1 and 5 corresponding to capacitors according to the steps, and respectively punching holes at two ends of the bonding pad at the output end of the inductor in a staggered manner according to the diagram.
3 power supply through holes are punched above the large-capacity capacitor bonding pad 1, and 3 power supply through holes are punched below the large-capacity capacitor 4. Two rows of through holes are vertically drilled in the MOS ground pad area, and the two rows of through holes are staggered left and right relatively. 4 rows of through holes are punched on the right sides of the large-capacity capacitors 5,6,7 and 8, and the through holes are staggered up and down relatively.
Then, a small capacity capacitor: a small-capacity capacitor power supply bonding pad is arranged in the middle of the power supply through hole above and below the inductor, punching is not needed, and ground holes are punched on the left side and the right side of the ground bonding pad on the other side of the capacitor.
It should be noted that the illustration shows only the sizes of the inductor, capacitor, and MOS pad, and the actual device is large. The large-capacity capacitors (corresponding to the bonding pads 1, 5, 2, 6, 3, 7, 4 and 8) are positioned at the bottom layer of the PCB, and the other capacitors are arranged at the top layer of the PCB.
With reference to fig. 3, the implementation steps of the method are as follows:
1) determining the position of one phase power supply MOS, for example, after the position of the MOS corresponding to the MOS pad 15 shown in FIG. 3 is determined, the positions of the MOS ground pads and the like are all fixed;
2) designing a copper laying space in the isolation area in the area corresponding to the area 15 according to the size of the inductance bonding pad used for design, and then placing the inductance input bonding pad 12 in the middle position of the area, so that the position of the inductance output bonding pad 9 is also fixed;
3) 2 rows of power supply through holes are drilled below the 9, and the positions of the two rows of through holes are staggered;
4) after the through holes below the inductance bonding pads 9 are determined, capacitors corresponding to the bonding pads 2 and 6 are placed in the positions shown in the figure, the distance between two rows of through holes is reserved below the bonding pads 2, and inductors corresponding to the inductance bonding pads 10 and 13 are placed;
5) after the position of the inductor is determined, two rows of through holes are respectively punched on the upper part and the lower part of the bonding pad 10, and the through holes are arranged in a staggered manner;
6) placing the MOS corresponding to the bonding pad 16 according to the positions corresponding to the positions 13 and 16;
7) placing the bonding pads 3 and 7 corresponding to capacitors, the bonding pads 11 and 14 corresponding to inductors, the bonding pad 17 corresponding to an MOS, the bonding pads 4 and 8 corresponding to capacitors, and the bonding pads 1 and 5 corresponding to capacitors according to the steps, and ensuring that holes are respectively punched at two ends of the bonding pads at the output ends of all inductors in a staggered manner;
8) punching 3 power supply through holes above the large-capacity capacitor bonding pad 1, and punching 3 power supply through holes below the large-capacity capacitor 4;
9) vertically punching two rows of through holes in the MOS ground pad area, wherein the two rows of through holes are staggered left and right relatively;
10) 4 rows of through holes are punched on the right sides of the large-capacity capacitors 5,6,7 and 8, and the through holes are staggered up and down relatively;
11) placing a small-capacity capacitor: a small-capacity capacitor power supply bonding pad is arranged in the middle of the power supply through hole above and below the inductor, punching is not needed, and ground holes are punched on the left side and the right side of the ground bonding pad on the other side of the capacitor.
According to the steps, the layout and wiring method of the output end of the multi-phase DC-DC power supply can be completed.
Therefore, according to the method, the power supply components are reasonable in layout, the via holes are arranged in a staggered mode, and the via hole current is relatively uniform. Compared with the traditional design, the power supply and the ground plane reflow plane are greatly increased, and the reliability of the power supply design is improved. The large-capacity capacitor is closer to the power supply adjusting chip, and the power supply circuit is more stable.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a second device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A method of layout of a multi-phase DC-DC power module, the method comprising:
determining a first phase MOS bonding pad position and a first phase MOS ground bonding pad position;
determining a first isolation region corresponding to the first-phase MOS power supply according to the position and the size of the first-phase MOS bonding pad, placing a first inductance input bonding pad in the first isolation region, and determining a first inductance output bonding pad according to the first inductance input bonding pad;
two rows of power supply through holes are respectively arranged on the upper side and the lower side of the first inductance output bonding pad, and the two rows of power supply through holes are arranged in a staggered mode;
placing a first large-capacity capacitance power supply bonding pad under two rows of power supply through holes at the lower side of the first inductance output bonding pad, and determining the position of the first large-capacity capacitance ground bonding pad;
arranging two rows of power supply through holes on the lower side of the first large-capacity capacitor power supply bonding pad, wherein the two rows of power supply through holes are arranged in a staggered manner;
arranging a second inductance output bonding pad under two rows of power via holes at the lower side of the first large-capacity capacitance power bonding pad, and determining a second inductance input bonding pad;
and determining a second phase MOS bonding pad position and the second phase MOS grounding bonding pad position according to the second inductance input bonding pad.
2. The method of claim 1, further comprising:
and determining the positions of a second large-capacity capacitance power supply bonding pad and a second large-capacity capacitance ground bonding pad according to the position of the second phase MOS bonding pad.
3. The method of claim 2, further comprising:
determining a third inductance input bonding pad and a third inductance output bonding pad according to the positions of the second large-capacity capacitance power supply bonding pad and the second large-capacity capacitance ground bonding pad;
determining the position of a third phase MOS bonding pad and the position of a third phase MOS ground bonding pad according to the third inductance input bonding pad and the third inductance output bonding pad;
and determining the position of a third large-capacity capacitance power supply bonding pad and the position of a third large-capacity capacitance grounding bonding pad according to the position of the third phase MOS bonding pad and the position of the third phase MOS grounding bonding pad.
4. The method of claim 3, further comprising:
and arranging a fourth large-capacity capacitance power supply bonding pad on the two rows of power supply through holes on the upper side of the first inductance output bonding pad, and determining the position of the fourth large-capacity capacitance ground bonding pad.
5. The method of claim 4, further comprising:
and a row of three power supply through holes is arranged below the third large-capacity capacitor power supply pad, and a row of 3 power supply through holes is arranged above the fourth large-capacity capacitor power supply pad.
6. A multi-phase DC-DC power module is characterized in that the power module comprises a ground plane PCB board and a power plane PCB board, wherein the ground plane PCB board is at least used for placing a first-phase MOS bonding pad, a first-phase MOS grounding bonding pad, a first inductance input bonding pad, a first large-capacity capacitance grounding bonding pad, a second-phase MOS grounding bonding pad, a second inductance input bonding pad, a second large-capacity capacitance grounding bonding pad, a third-phase MOS bonding pad, a third large-capacity capacitance grounding bonding pad and a fourth large-capacity capacitance grounding bonding pad;
the power plane PCB board is at least used for placing a first inductance output bonding pad, a first large-capacity capacitance power bonding pad, a second inductance output bonding pad, a second large-capacity capacitance power bonding pad, a third inductance output bonding pad, a third large-capacity capacitance power bonding pad and a fourth large-capacity capacitance power bonding pad;
the first-phase MOS ground pad is adjacent to the first inductance input pad, the second-phase MOS ground pad is adjacent to the second inductance input pad, the third-phase MOS ground pad is adjacent to the third inductance input pad, two rows of power supply through holes are formed between the first inductance output pad and the first large-capacity capacitance power supply pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode;
two rows of power supply through holes are formed between the first large-capacity capacitor power supply bonding pad and the second inductor output bonding pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode;
two rows of power supply through holes are formed between the second inductance output bonding pad and the second large-capacity capacitance power supply bonding pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode;
two rows of power supply through holes are formed between the second large-capacity capacitor power supply bonding pad and the third inductor output bonding pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode;
two rows of power supply through holes are formed between the third inductance output bonding pad and the third large-capacity capacitance power supply bonding pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode;
two rows of power supply through holes are formed between the first inductance output bonding pad and the fourth large-capacity capacitance power supply bonding pad, and the two rows of power supply through holes are arranged on the power supply plane PCB in a staggered mode.
7. The power supply module of claim 6, wherein there are 3 power vias above the fourth bulk capacitance power pad; and 3 power supply through holes are formed below the third large-capacity capacitor power supply pad.
8. The power supply module of claim 6 or 7, wherein the ground vias on the ground plane PCB board are staggered.
9. The power module as claimed in claim 8, wherein the power plane PCB board is further configured to place at least a first small-capacity capacitive power pad, a first small-capacity capacitive ground pad, a second small-capacity capacitive power pad, a second small-capacity capacitive ground pad, a third small-capacity capacitive power pad, a third small-capacity capacitive ground pad, a fourth small-capacity capacitive power pad, a fourth small-capacity capacitive ground pad, a fifth small-capacity capacitive power pad, and a fifth small-capacity capacitive ground pad;
a power supply through hole between the first inductance output bonding pad and the fourth large-capacity capacitance power supply bonding pad is adjacent to the first small-capacity capacitance power supply bonding pad, and two power supply through holes are arranged on two sides of the first small-capacity capacitance ground bonding pad;
a power supply through hole between the first inductance output bonding pad and the first large-capacity capacitance power supply bonding pad is adjacent to the second small-capacity capacitance power supply bonding pad, and two power supply through holes are arranged on two sides of the second small-capacity capacitance ground bonding pad;
a power supply through hole between the second inductance output bonding pad and the first large-capacity capacitance power supply bonding pad is adjacent to a third small-capacity capacitance power supply bonding pad, and two power supply through holes are arranged on two sides of the third small-capacity capacitance ground bonding pad;
a power supply through hole between the second inductance output bonding pad and the second large-capacity capacitance power supply bonding pad is adjacent to the fourth small-capacity capacitance power supply bonding pad, and two power supply through holes are arranged on two sides of the fourth small-capacity capacitance ground bonding pad;
and a power supply through hole between the third inductance output bonding pad and the second large-capacity capacitance power supply bonding pad is adjacent to the fifth small-capacity capacitance power supply bonding pad, and two power supply through holes are arranged on two sides of the fifth small-capacity capacitance ground bonding pad.
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| US7449956B2 (en) * | 2006-06-30 | 2008-11-11 | Nokia Corporation | Semiconductor device |
| JP2010171188A (en) * | 2009-01-22 | 2010-08-05 | Ngk Insulators Ltd | Small inductor and method of manufacturing the same |
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| CN107785361B (en) * | 2016-08-26 | 2020-06-30 | 台达电子企业管理（上海）有限公司 | Power integration module |
| CN103491720B (en) * | 2013-09-16 | 2017-06-20 | 华为技术有限公司 | The preparation method and printed circuit board (PCB) of a kind of printed circuit board (PCB) |
| US9236347B2 (en) * | 2013-10-09 | 2016-01-12 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Operating and manufacturing a DC-DC converter |
| CN104157634B (en) * | 2014-07-25 | 2017-04-26 | 西安交通大学 | Low-parasitic-inductance GaN power integration module distributed in middle of separating capacitor |
| US9831666B2 (en) * | 2015-05-15 | 2017-11-28 | Analog Devices, Inc. | Apparatus and methods for electrostatic discharge protection of radio frequency interfaces |
| US10050528B2 (en) * | 2015-06-29 | 2018-08-14 | Infineon Technologies Austria Ag | Current distribution in DC-DC converters |
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